On Fri, 5 Mar 2021 at 23:54, Keith Packard <kei...@keithp.com> wrote: > > Peter Maydell <peter.mayd...@linaro.org> writes: > > > For semihosting for Arm what matters is "what state is the core > > in at the point where it makes the semihosting SVC/HLT/etc insn?". > > Ok, that means we *aren't* talking about -mabi=ilp32, which is good -- > in my current picolibc implementation, the semihosting code uses a pure > 64-bit interface for aarch64 targets, even when using ilp32 ABI.
ILP32 for AArch64 is a zombie target -- it is kinda-sorta supported in some toolchains but has no support in eg the Linux syscall ABI. The semihosting ABI does not implement any kind of ILP32 variant -- you can have A32/T32 (AArch32) semihosting, where register and field sizes are 32 bit, or you can have A64 (AArch64) semihosting, where register and field sizes are 64 bit. > > How does RISCV specify it? > > Because the ISA is identical between 64- and 32- bit (and 128-bit) > execution modes, the only difference between the two is the Machine XLEN > value which encodes the native base integer ISA width. You switch modes > by modifying this value. I meant, how does the RISCV semihosting ABI specify what the field size is? To answer my own question, I just looked at the spec doc and it says "depends on whether the caller is 32-bit or 64-bit", which implies that we need to look at the current state of the CPU in some way. > I don't know of any implementation in hardware or software that supports > modifying this value. I'm not sure we need to support this in the > semihosting code for qemu as I'm pretty sure getting qemu to support > dynamic XLEN values would be a large project (a project which I don't > personally feel would offer much value). Part of why I asked is that the current RISCV implementation is just looking at sizeof(target_ulong); but the qemu-system-riscv64 executable AIUI now supports emulating both "this is a 64 bit guest CPU" and "this is a 32 bit host CPU", and so looking at a QEMU-compile-time value like "sizeof(target_ulong)" will produce the wrong answer for 32-bit CPUs emulated in the qemu-system-riscv64 binary. My guess is maybe it should be looking at the result of riscv_cpu_is_32bit() instead. thanks -- PMM