On 3/22/21 2:27 PM, Claudio Fontana wrote: > XXX > --- > accel/accel-common.c | 9 +++++++++ > hw/core/cpu.c | 3 ++- > include/hw/core/accel-cpu.h | 2 ++ > include/qemu/accel.h | 6 ++++++ > target/i386/cpu.c | 4 ---- > target/i386/kvm/kvm-cpu.c | 6 ++++++ > 6 files changed, 25 insertions(+), 5 deletions(-) > > > This surprisingly works without moving cpu_reset() to a > specific_ss module, even though > > accel-common.c is specific_ss, > hw/core/cpu.c is common_ss. > > How come the call to accel_reset_cpu works?
Each CPU optionally calls cpu_reset() manually? $ git grep register_reset.*cpu hw/arm/armv7m.c:334: qemu_register_reset(armv7m_reset, cpu); hw/arm/boot.c:1290: qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); hw/cris/boot.c:101: qemu_register_reset(main_cpu_reset, cpu); hw/lm32/lm32_boards.c:162: qemu_register_reset(main_cpu_reset, reset_info); hw/lm32/lm32_boards.c:289: qemu_register_reset(main_cpu_reset, reset_info); hw/lm32/milkymist.c:238: qemu_register_reset(main_cpu_reset, reset_info); hw/m68k/q800.c:247: qemu_register_reset(main_cpu_reset, cpu); hw/m68k/virt.c:132: qemu_register_reset(main_cpu_reset, cpu); hw/microblaze/boot.c:134: qemu_register_reset(main_cpu_reset, cpu); hw/mips/cps.c:107: qemu_register_reset(main_cpu_reset, cpu); hw/mips/fuloong2e.c:269: qemu_register_reset(main_cpu_reset, cpu); hw/mips/jazz.c:195: qemu_register_reset(main_cpu_reset, cpu); hw/mips/loongson3_virt.c:545: qemu_register_reset(main_cpu_reset, cpu); hw/mips/malta.c:1185: qemu_register_reset(main_cpu_reset, cpu); hw/mips/mipssim.c:170: qemu_register_reset(main_cpu_reset, reset_info); hw/moxie/moxiesim.c:120: qemu_register_reset(main_cpu_reset, cpu); hw/nios2/boot.c:138: qemu_register_reset(main_cpu_reset, cpu); hw/openrisc/openrisc_sim.c:160: qemu_register_reset(main_cpu_reset, cpus[n]); hw/ppc/e500.c:903: qemu_register_reset(ppce500_cpu_reset, cpu); hw/ppc/e500.c:907: qemu_register_reset(ppce500_cpu_reset_sec, cpu); hw/ppc/mac_newworld.c:156: qemu_register_reset(ppc_core99_reset, cpu); hw/ppc/mac_oldworld.c:118: qemu_register_reset(ppc_heathrow_reset, cpu); hw/ppc/ppc440_bamboo.c:192: qemu_register_reset(main_cpu_reset, cpu); hw/ppc/ppc4xx_devs.c:75: qemu_register_reset(ppc4xx_reset, cpu); hw/ppc/ppc_booke.c:369: qemu_register_reset(ppc_booke_timer_reset_handle, cpu); hw/ppc/prep.c:270: qemu_register_reset(ppc_prep_reset, cpu); hw/ppc/sam460ex.c:306: qemu_register_reset(main_cpu_reset, cpu); hw/ppc/spapr_cpu_core.c:245: qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); hw/ppc/spapr_cpu_core.c:326: qemu_register_reset(spapr_cpu_core_reset_handler, sc); hw/ppc/virtex_ml507.c:233: qemu_register_reset(main_cpu_reset, cpu); hw/riscv/riscv_hart.c:51: qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); hw/sh4/r2d.c:251: qemu_register_reset(main_cpu_reset, reset_info); hw/sparc/leon3.c:213: qemu_register_reset(main_cpu_reset, reset_info); hw/sparc/sun4m.c:828: qemu_register_reset(sun4m_cpu_reset, cpu); hw/sparc64/sparc64.c:357: qemu_register_reset(main_cpu_reset, reset_info); hw/xtensa/sim.c:68: qemu_register_reset(sim_reset, cpu); hw/xtensa/xtfpga.c:270: qemu_register_reset(xtfpga_reset, cpu); target/i386/cpu.c:6859: qemu_register_reset(x86_cpu_machine_reset_cb, cpu); target/i386/cpu.c:6942: qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); target/i386/hax/hax-all.c:230: qemu_register_reset(hax_reset_vcpu_state, (CPUArchState *) (cpu->env_ptr)); target/s390x/cpu.c:232: qemu_register_reset(s390_cpu_machine_reset_cb, cpu); target/s390x/cpu.c:319: qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
