On Wed, Apr 21, 2021 at 2:20 PM <frank.ch...@sifive.com> wrote: > > From: Kito Cheng <kito.ch...@sifive.com> > > Signed-off-by: Kito Cheng <kito.ch...@sifive.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn32.decode | 2 ++ > target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d64326fd864..938c23088eb 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -598,6 +598,8 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > clz 011000 000000 ..... 001 ..... 0010011 @r2 > ctz 011000 000001 ..... 001 ..... 0010011 @r2 > cpop 011000 000010 ..... 001 ..... 0010011 @r2 > +sext_b 011000 000100 ..... 001 ..... 0010011 @r2 > +sext_h 011000 000101 ..... 001 ..... 0010011 @r2 > > andn 0100000 .......... 111 ..... 0110011 @r > orn 0100000 .......... 110 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc > b/target/riscv/insn_trans/trans_rvb.c.inc > index 2aa4515fe31..1496996a660 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a) > return gen_arith(ctx, a, tcg_gen_umax_tl); > } > > +static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, tcg_gen_ext8s_tl); > +} > + > +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_unary(ctx, a, tcg_gen_ext16s_tl); > +} > + > /* RV64-only instructions */ > #ifdef TARGET_RISCV64 > > -- > 2.17.1 > >