On Wed, Apr 21, 2021 at 2:19 PM <frank.ch...@sifive.com> wrote: > > From: Kito Cheng <kito.ch...@sifive.com> > > Signed-off-by: Kito Cheng <kito.ch...@sifive.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn32.decode | 4 ++++ > target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 7f32b8c6d15..d64326fd864 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -605,3 +605,7 @@ xnor 0100000 .......... 100 ..... 0110011 @r > pack 0000100 .......... 100 ..... 0110011 @r > packu 0100100 .......... 100 ..... 0110011 @r > packh 0000100 .......... 111 ..... 0110011 @r > +min 0000101 .......... 100 ..... 0110011 @r > +minu 0000101 .......... 101 ..... 0110011 @r > +max 0000101 .......... 110 ..... 0110011 @r > +maxu 0000101 .......... 111 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc > b/target/riscv/insn_trans/trans_rvb.c.inc > index 2d24dafac09..2aa4515fe31 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a) > return gen_arith(ctx, a, gen_packh); > } > > +static bool trans_min(DisasContext *ctx, arg_min *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_arith(ctx, a, tcg_gen_smin_tl); > +} > + > +static bool trans_max(DisasContext *ctx, arg_max *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_arith(ctx, a, tcg_gen_smax_tl); > +} > + > +static bool trans_minu(DisasContext *ctx, arg_minu *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_arith(ctx, a, tcg_gen_umin_tl); > +} > + > +static bool trans_maxu(DisasContext *ctx, arg_maxu *a) > +{ > + REQUIRE_EXT(ctx, RVB); > + return gen_arith(ctx, a, tcg_gen_umax_tl); > +} > + > /* RV64-only instructions */ > #ifdef TARGET_RISCV64 > > -- > 2.17.1 > >