Signed-off-by: Alexey Baturo <space.monkey.deliv...@gmail.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0682410f5d..fecc64d7ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY env->mmte |= PM_EXT_INITIAL; #endif + target_misa |= RVJ; } if (cpu->cfg.ext_v) { target_misa |= RVV; @@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), -- 2.20.1