> -----Original Message-----
> From: Alessandro Di Federico <ale.q...@rev.ng>
> Sent: Saturday, June 19, 2021 3:37 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson <tsimp...@quicinc.com>; Brian Cain
> <bc...@quicinc.com>; bab...@rev.ng; ni...@rev.ng; phi...@redhat.com;
> richard.hender...@linaro.org; Alessandro Di Federico <a...@rev.ng>
> Subject: [PATCH v5 09/14] target/hexagon: import lexer for idef-parser
>
> From: Paolo Montesel <bab...@rev.ng>
>
> Signed-off-by: Alessandro Di Federico <a...@rev.ng>
> Signed-off-by: Paolo Montesel <bab...@rev.ng>
> ---
> target/hexagon/idef-parser/idef-parser.h | 262 ++++++++
> target/hexagon/idef-parser/idef-parser.lex | 597 ++++++++++++++++++
> target/hexagon/meson.build | 4 +
> tests/docker/dockerfiles/alpine.docker | 1 +
> tests/docker/dockerfiles/centos8.docker | 1 +
> tests/docker/dockerfiles/debian-amd64.docker | 1 +
> tests/docker/dockerfiles/debian10.docker | 1 +
> .../dockerfiles/fedora-i386-cross.docker | 1 +
> .../dockerfiles/fedora-win32-cross.docker | 1 +
> .../dockerfiles/fedora-win64-cross.docker | 1 +
> tests/docker/dockerfiles/fedora.docker | 1 +
> tests/docker/dockerfiles/opensuse-leap.docker | 1 +
> tests/docker/dockerfiles/ubuntu.docker | 1 +
> tests/docker/dockerfiles/ubuntu1804.docker | 1 +
> tests/docker/dockerfiles/ubuntu2004.docker | 3 +-
> 15 files changed, 876 insertions(+), 1 deletion(-) create mode 100644
> target/hexagon/idef-parser/idef-parser.h
> create mode 100644 target/hexagon/idef-parser/idef-parser.lex
>
> diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef-
> parser/idef-parser.h
> new file mode 100644
> +/**
> + * Types of control registers, assigned to the HexReg.id field */
> +typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType;
Where is this used? SP, FP, LR are not control registers - they are general
purpose registers.
> diff --git a/target/hexagon/idef-parser/idef-parser.lex
> b/target/hexagon/idef-parser/idef-parser.lex
> new file mode 100644
> +"fREAD_SP()" |
> +"SP" { yylval->rvalue.type = REGISTER;
> + yylval->rvalue.reg.type = CONTROL;
> + yylval->rvalue.reg.id = SP;
> + yylval->rvalue.reg.bit_width = 32;
> + yylval->rvalue.bit_width = 32;
> + return REG; }
> +"fREAD_FP()" |
> +"FP" { yylval->rvalue.type = REGISTER;
> + yylval->rvalue.reg.type = CONTROL;
> + yylval->rvalue.reg.id = FP;
> + yylval->rvalue.reg.bit_width = 32;
> + yylval->rvalue.bit_width = 32;
> + return REG; }
> +"fREAD_LR()" |
> +"LR" { yylval->rvalue.type = REGISTER;
> + yylval->rvalue.reg.type = CONTROL;
> + yylval->rvalue.reg.id = LR;
> + yylval->rvalue.reg.bit_width = 32;
> + yylval->rvalue.bit_width = 32;
> + return REG; }
This looks like the use where you are treating these as control registers.
Just lex them as general purpose registers with numbers 29, 30, 31.
