On Fri, 20 Aug 2021 at 03:36, Li, Chunming <chunming...@verisilicon.com> wrote: > > The current SMMU V3 device model only support PCI/PCIe devices, > so we update it to support non-PCI/PCIe devices. > > hw/arm/smmuv3: > . Create IOMMU memory regions for non-PCI/PCIe devices based on their > SID > . Add sid-map property to store non-PCI/PCIe devices SID > . Update implementation of CFGI commands based on device SID > hw/arm/smmu-common: > . Differentiate PCI/PCIe and non-PCI/PCIe devices SID getting strategy > hw/arm/virt: > . Add PL330 DMA controller and connect with SMMUv3 for testing > . Add smmuv3_sidmap for non-PCI/PCIe devices SID setting
Please don't try to do all these things in one big patch -- put together a patchseries with several smaller patches, each of which does one self-contained thing. > Signed-off-by: Chunming Li <chunming...@verisilicon.com> > Signed-off-by: Renwei Liu <renwei....@verisilicon.com> > --- > This patch depends on PL330 memory region connection patch: > https://patchew.org/QEMU/4c23c17b8e87e74e906a25a3254a03f4fa1fe...@shasxm03.verisilicon.com/ If you have a patch that depends on another, it's usually better to send them as a patchseries. I was wondering what the reason for that PL330 patch was... thanks -- PMM
