As of today, when booting upstream U-Boot for Xilinx Zynq, the UART does not receive anything. Debugging shows that the UART input clock frequency is zero which prevents the UART from receiving anything as. per the logic in uart_receive().
Note the U-Boot can still output data to the UART tx fifo, which should not happen, as the design seems to prevent the data transmission when clock is not enabled but somehow it only applies to the Rx side. For anyone who is interested to give a try, here is the U-Boot defconfig: $ make xilinx_zynq_virt_defconfig and QEMU commands to test U-Boot: $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \ -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0 Note U-Boot used to boot properly in QEMU 4.2.0 which is the QEMU version used in current U-Boot's CI testing. The UART clock changes were introduced by the following 3 commits: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts") b636db306e06 ("hw/char/cadence_uart: add clock support") 5b49a34c6800 ("hw/arm/xilinx_zynq: connect uart clocks to slcr") Changes in v3: - new patch: hw/char: cadence_uart: Log a guest error when unclocked or in reset Changes in v2: - avoid declaring variables mid-scope - new patch: hw/char: cadence_uart: Convert to memop_with_attrs() ops - new patch: hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read,write}() Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read,write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset hw/char/cadence_uart.c | 61 +++++++++++++++++++++++++++++------------- hw/misc/zynq_slcr.c | 31 ++++++++++++--------- 2 files changed, 61 insertions(+), 31 deletions(-) -- 2.25.1