From: Alistair Francis <alistair.fran...@wdc.com>
Populate mtval and stval when taking an illegal instruction exception if the features are set for the CPU. Alistair Francis (3): target/riscv: Set the opcode in DisasContext target/riscv: Implement the stval/mtval illegal instruction target/riscv: Set mtval and stval support target/riscv/cpu.h | 6 +++++- target/riscv/cpu.c | 6 +++++- target/riscv/cpu_helper.c | 10 +++++++++ target/riscv/translate.c | 43 +++++++++++++++++++++------------------ 4 files changed, 43 insertions(+), 22 deletions(-) -- 2.31.1
