On Wed, Sep 8, 2021 at 12:54 PM Alistair Francis <alistair.fran...@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > The stval and mtval registers can optionally contain the faulting > instruction on an illegal instruction exception. This patch adds support > for setting the stval and mtval registers based on the CPU feature. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > target/riscv/cpu.h | 5 ++++- > target/riscv/cpu_helper.c | 10 ++++++++++ > target/riscv/translate.c | 31 +++++++++++++++++-------------- > 3 files changed, 31 insertions(+), 15 deletions(-) >
Reviewed-by: Bin Meng <bmeng...@gmail.com>
