Signed-off-by: liweiwei <liwei...@iscas.ac.cn> Signed-off-by: wangjunqiang <wangjunqi...@iscas.ac.cn> --- target/riscv/cpu.c | 9 ++++++--- target/riscv/cpu.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d53125dbc..0f03d3efba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) error_setg(errp, "I and E extensions are incompatible"); return; - } + } if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); return; - } + } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) { warn_report("Setting G will also set IMAFD"); @@ -639,6 +639,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), + DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false), + DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false), + DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..f9f4437efc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,6 +309,9 @@ struct RISCVCPU { bool ext_zbb; bool ext_zbc; bool ext_zbs; + bool ext_zbkb; + bool ext_zbkc; + bool ext_zbkx; bool ext_counters; bool ext_ifencei; bool ext_icsr; -- 2.17.1