On Tue, 7 Dec 2021 at 13:05, Damien Hedde <damien.he...@greensocs.com> wrote: > On 12/7/21 13:45, Philippe Mathieu-Daudé wrote: > > On 12/7/21 10:44, Damien Hedde wrote: > >> According to the "Arm Generic Interrupt Controller Architecture > >> Specification GIC architecture version 3 and 4" (version G: page 345 > >> for aarch64 or 509 for aarch32): > >> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and > >> ICH_HCR.EOIcount is non-zero. > >> > >> When only LRENPIE was set (and EOI count was zero), the LRENP bit was > >> wrongly set and MISR value was wrong. > >> > >> As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, > >> the maintenance interrupt was constantly fired. It happens since patch > >> 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") > >> which fixed another bug about maintenance interrupt (most significant > >> bits of misr, including this one, were ignored in the interrupt trigger). > >> > >> Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system > >> registers") > > > > This commit predates 6.1 release, so technically this is not > > a regression for 6.2. > > Do you mean "Fixes:" is meant only for regression or simply that this > patch should not go for 6.2 ?
Fixes: is fine in all situations where the commit is fixing a bug that was introduced in the commit hash it mentions. Separately, given where we are in the release cycle, a patch has to hit a very high bar to go into 6.2: at least "this breaks a real world use case that worked fine in 6.1", and probably also "a use case that we expect a fair number of users to be using". -- PMM