On Tue, 7 Dec 2021 at 09:44, Damien Hedde <damien.he...@greensocs.com> wrote: > > According to the "Arm Generic Interrupt Controller Architecture > Specification GIC architecture version 3 and 4" (version G: page 345 > for aarch64 or 509 for aarch32): > LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and > ICH_HCR.EOIcount is non-zero. > > When only LRENPIE was set (and EOI count was zero), the LRENP bit was > wrongly set and MISR value was wrong. > > As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, > the maintenance interrupt was constantly fired. It happens since patch > 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") > which fixed another bug about maintenance interrupt (most significant > bits of misr, including this one, were ignored in the interrupt trigger). > > Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system > registers") > Signed-off-by: Damien Hedde <damien.he...@greensocs.com> > --- > The gic doc is available here: > https://developer.arm.com/documentation/ihi0069/g > > v2: identical resend because subject screw-up (sorry)
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> I won't try to put this into 6.2 unless you have a common guest that runs into this bug. thanks -- PMM