On Mon, Mar 28, 2022 at 7:30 AM Alistair Francis <alistai...@gmail.com>
wrote:
> On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI <research_tra...@irq.a4lg.com>
> wrote:
> >
> > Some bits in RISC-V `misa' CSR should not be reflected in the ISA
> > string. For instance, `S' and `U' (represents existence of supervisor
> > and user mode, respectively) in `misa' CSR must not be copied since
> > neither `S' nor `U' are valid single-letter extensions.
>
> Thanks for the patch.
>
> >
> > This commit restricts which bits to copy from `misa' CSR to ISA string
> > with another fix: `C' extension should be preceded by `L' extension.
>
> The L extension has been removed, so it probably makes more sense to
> just remove it at this stage instead of fixing the order.
>
> >
> > It also clarifies that RISC-V extension order string is actually a
> > single-letter extension order list.
> >
> > Signed-off-by: Tsukasa OI <research_tra...@irq.a4lg.com>
> > ---
> > target/riscv/cpu.c | 10 +++++-----
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index ddda4906ff..84877cf24a 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -34,7 +34,7 @@
> >
> > /* RISC-V CPU definitions */
> >
> > -static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
> > +static const char riscv_single_letter_exts[] = "IEMAFDQLCBJTPVNH";
>
> What about K?
>
> Why not use IEMAFDQCBKJTPVNH instead?
>
> Alistair
>
The RISC-V ISA Manual (version 20191213) is quite old.
Where "L" was not removed and "K" was not introduced.
It seems Unprivileged spec is not "ratified" as often as Privileged spec
does (most of them are drafts...).
But I agree that it's better to remove "L" and add "K" into ISA string.
Regards,
Frank Chang
>
> >
> > const char * const riscv_int_regnames[] = {
> > "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> > @@ -901,12 +901,12 @@ static void riscv_cpu_class_init(ObjectClass *c,
> void *data)
> > char *riscv_isa_string(RISCVCPU *cpu)
> > {
> > int i;
> > - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> > + const size_t maxlen = sizeof("rv128") +
> sizeof(riscv_single_letter_exts);
> > char *isa_str = g_new(char, maxlen);
> > char *p = isa_str + snprintf(isa_str, maxlen, "rv%d",
> TARGET_LONG_BITS);
> > - for (i = 0; i < sizeof(riscv_exts); i++) {
> > - if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> > - *p++ = qemu_tolower(riscv_exts[i]);
> > + for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
> > + if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
> > + *p++ = qemu_tolower(riscv_single_letter_exts[i]);
> > }
> > }
> > *p = '\0';
> > --
> > 2.32.0
> >
> >
>
>
