On 2022/03/28 8:29, Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI <research_tra...@irq.a4lg.com> > wrote: >> >> [This is the same patch as previous ones] > > Hello, > > Thanks for the patch! > >> <https://lists.nongnu.org/archive/html/qemu-riscv/2022-02/msg00098.html> >> (qemu-riscv only) > > This never made it to the QEMU mailing list > >> <https://lists.nongnu.org/archive/html/qemu-riscv/2022-02/msg00097.html> >> (resent due to configuration error of my mail server; qemu-riscv only) > > and neither did this
Ah, that was the reason! I'm happy to know that. > >> >> I hope this is applied before the QEMU 7.0 release. > > Unfortunately you have missed the window for 7.0. This patch will need > to be reviewed then applied for the next QEMU release. Understood. > >> >> Signed-off-by: Tsukasa OI <research_tra...@irq.a4lg.com> >> Reviewed-by: Frank Chang <frank.ch...@sifive.com> >> >> S and U are misa bits but not extensions (instead, they are supported >> privilege modes). Thus, they should not be copied to the ISA string. >> >> I am truly surprised that this patchset is the THIRD attempt to fix this >> longstanding problem. > > I'm sorry you feel this way, but this is the first time this patch has > been sent to the list since 2019. > > I'm not sure why (1) wasn't applied, but (2) and (3) don't appear to > have been sent to the QEMU mailing list. > > The separate RISC-V mailing list is confusing, but patches should be > sent to qemu-devel, as described at: > https://wiki.qemu.org/Contribute/MailingLists > > Alistair Thanks for letting me know. From the next time, I will follow this. > >> >> (1) August 2019: by Palmer Dabbelt >> <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00165.html> >> <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00141.html> >> <https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00259.html> >> >> (2) April 2021: by Emmanuel Blot >> <https://lists.nongnu.org/archive/html/qemu-riscv/2021-04/msg00248.html> >> >> (3) February 2022: by me (this patchset) >> >> I feel this is urgent to eliminate this bug now considering it required >> a workaround to RISC-V Linux kernel as I pointed out: >> <http://lists.infradead.org/pipermail/linux-riscv/2022-February/012252.html> >> >> >> Though my patchset is first developed independently, this submitted >> version is influenced by (2) Emmanuel Blot's patchset. Thanks to this, >> constant "[n]" can now be variable "[]". >> >> It also fixes an ordering issue where 'C' should be preceded by 'L' >> (order: 'L' -> 'C') as per the RISC-V ISA Manual (version 20191213), >> Table 27.1. >> >> It clarifies the role of `riscv_exts'. It's a single-letter extrension >> ordering list. >> >> >> >> >> Tsukasa OI (1): >> target/riscv: misa to ISA string conversion fix >> >> target/riscv/cpu.c | 10 +++++----- >> 1 file changed, 5 insertions(+), 5 deletions(-) >> >> >> base-commit: f345abe36527a8b575482bb5a0616f43952bf1f4 >> -- >> 2.32.0 >> >> >