On Mon, Jul 11 2022, Víctor Colombo <victor.colo...@eldorado.org.br> wrote:
> Implementation for instructions hashst and hashchk, which were added
> in Power ISA 3.1B.
>
> It was decided to implement the hash algorithm from ground up in this
> patch exactly as described in Power ISA.
>
> Signed-off-by: Víctor Colombo <victor.colo...@eldorado.org.br>
> ---
> linux-headers/asm-powerpc/kvm.h | 2 +
> target/ppc/cpu.h | 1 +
> target/ppc/cpu_init.c | 4 ++
> target/ppc/excp_helper.c | 80 ++++++++++++++++++++++
> target/ppc/helper.h | 2 +
> target/ppc/insn32.decode | 8 +++
> target/ppc/translate.c | 5 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
> 8 files changed, 134 insertions(+)
>
> diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
> index 9f18fa090f..dd58d574bf 100644
> --- a/linux-headers/asm-powerpc/kvm.h
> +++ b/linux-headers/asm-powerpc/kvm.h
> @@ -646,6 +646,8 @@ struct kvm_ppc_cpu_char {
> #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
> #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
> #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
> +/* FIXME: KVM hasn't exposed these registers yet */
> +#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x00)
>
> /* Transactional Memory checkpointed state:
> * This is all GPRs, all VSX regs and a subset of SPRs
<editorial>
Please split any header updates into a separate patch (a full header
update or, if the changes are not yet included in Linux, a placeholder
patch. Thank you :)
</editorial>
