On 29 December 2011 16:19, Mark Langsdorf <mark.langsd...@calxeda.com> wrote: > Add a cp15 config_base_register that currently defaults to 0. > After the QOM CPU support is added, the value will be properly > set to the periphal base value. > > Signed-off-by: Mark Langsdorf <mark.langsd...@calxeda.com> > Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
I need to revoke this Reviewed-by: because... > @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) > * 0x200 << ($rn & 0xfff), when MMU is off. */ > goto bad_reg; > } > + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { > + switch (crm) { > + case 0: > + /* The config_base_address should hold the value of > + * the peripheral base. ARM should get this from a CPU > + * object property, but that support isn't available in > + * December 2011. Default to 0 for now and board models > + * that care can set it by a private hook */ > + if ((op1 == 4) && (op2 == 0)) { > + return env->cp15.c15_config_base_address; > + } > + } > + goto bad_reg; > + } > return 0; this breaks booting on vexpress, which complains qemu: fatal: Unimplemented cp15 register read (c15, c0, {0, 1}) because we're now barfing on all the other c15 registers which we used to read as zero. The simplest fix is to drop that 'goto bad_reg;'. More complicatedly we could decode the c15 range properly for A9 (as per the TRM). -- PMM