On 01/04/2012 11:50 AM, Peter Maydell wrote: > On 4 January 2012 16:53, Mark Langsdorf <mark.langsd...@calxeda.com> wrote: >> + } else if ((op1 == 0) && (op2 == 0)) { >> + /* power_control should be set to maximum latency. Again, >> + default to 0 and set by private hook */ >> + return env->cp15.c15_power_control; >> + } > > This one's read-write, which means it needs (a) support in set_cp15 > (b) save/load support.
Okay. > You also need to implement the diagnostic register c15,c0,0,1 > otherwise Linux won't boot when it tries to run this code: > http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345 > I suggest that should be implemented as reads-as-written. (Again, will > need save/load > support.) Ditto for the power diagnostic control register c15,c0,0,2, as used > in > this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html I'm handling all the c15 registers listed on p 4-11 of the Cortex-A9 r3p0 TRM. Would you please give me a reference for these other two registers? I'm not seeing them. Thanks. --Mark