On 26/10/22 21:46, Philippe Mathieu-Daudé wrote:
Bernhard posted a series merging both PIIX3/PIIX4 models
in one [1]. Due to Malta-specific board code forced into
the PIIX4 reset values, Bernhard had to include an array
of "register values at reset" as a class property. This
is not wrong, but to model properly the model, we should
simply use the hardware real reset values, not try to
bend the model to please the Malta board.
This series fix this issue by having the Malta bootloader
code setting the board-specific PIIX4 IRQ routing values.
Note patch 2 still misses an equivalent nanoMIPS code.
Regards,
Phil.
[1] https://lore.kernel.org/qemu-devel/20221022150508.26830-1-shen...@gmail.com/
Philippe Mathieu-Daudé (3):
hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition
hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
hw/isa/piix4: Correct IRQRC[A:D] reset values
Based-on: <20221026191821.28167-1-phi...@linaro.org>
https://lore.kernel.org/qemu-devel/20221026191821.28167-1-phi...@linaro.org/
