On 10 January 2012 16:45, Mark Langsdorf <mark.langsd...@calxeda.com> wrote:
> Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,
> and create a configurable property for each defaulting to 96 and 64
> (respectively) so that device modelers can set the value appropriately
> for their SoC. Other ARM processors also set their maximum number of
> used IRQs appropriately.
>
> Set the maximum theoretically number of GIC interrupts to 1020 and
"theoretical"
> update the save/restore code to only use the appropriate number for
> each SoC.
>
> Signed-off-by: Mark Langsdorf <mark.langsd...@calxeda.com>
> @@ -216,6 +216,13 @@ static SysBusDeviceInfo a9mp_priv_info = {
> .qdev.reset = a9mp_priv_reset,
> .qdev.props = (Property[]) {
> DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
> + /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
> + * IRQ lines (with another 32 internal). We default to 64+32, which
> + * is the number provided by the Cortex-A9MP test chip in the
Patch has trailing space at the end of this line (my mailer has eaten
it but it's in the original patch).
> + * Realview PBX-A9 and Versatile Express A9 development boards.
> + * Other boards may differ and should set this property
> appropriately.
> + */
> + DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
> DEFINE_PROP_END_OF_LIST(),
> }
> };
> @@ -221,6 +217,15 @@ static SysBusDeviceInfo mpcore_priv_info = {
> .qdev.size = sizeof(mpcore_priv_state),
> .qdev.props = (Property[]) {
> DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
> + /* The ARM11 MPCORE TRM says the on-chip controller may have
> + * anything from 0 to 224 external interrupt IRQ lines (with another
> + * 32 internal). We default to 32+32, which is the number provided by
> + * the ARM11 MPCore test chip in the Realview Versatile Express
> + * coretile. Other boards may differ and should set this property
> + * appropriately. Some Linux kernels may not boot if the hardware
> + * has more IRQ lines than the kernel expects.
Trailing space again.
> + DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
> DEFINE_PROP_END_OF_LIST(),
> }
> };
> @@ -384,16 +382,34 @@ static int armv7m_nvic_init(SysBusDevice *dev)
> {
> nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
>
> - gic_init(&s->gic);
> + /* 32 internal lines (16 used for system exceptions) plus 64 external
> + * interrupt lines. */
> + gic_init(&s->gic, 96);
s->num_irq, not hardcoded 96.
Also the comment needs rephrasing now:
/* Note that for M profile gic_init() takes the number of external
* interrupt lines only.
*/
> memory_region_add_subregion(get_system_memory(), 0xe000e000,
> &s->gic.iomem);
> s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
> vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
> return 0;
> }
>
> +static SysBusDeviceInfo armv7m_nvic_priv_info = {
> + .init = armv7m_nvic_init,
> + .qdev.name = "armv7m_nvic",
> + .qdev.size = sizeof(nvic_state),
> + .qdev.vmsd = &vmstate_nvic,
> + .qdev.props = (Property[]) {
> + /* The ARM v7m may have anything from 0 to 496 external interrupt
> + * IRQ lines (with another 32 hidden internal exception lines). We
> + * default to 64+32
> + * Other boards may differ and should set this property
> appropriately.
> + */
This comment shouldn't talk about the 32 internal lines, as they are an
implementation detail of arm_gic.c, not architectural (unlike the A
profile GIC internal interrupt lines).
/* The ARM v7m may have anything from 0 to 496 external interrupt
* IRQ lines. We default to 64. Other boards may differ and should
* set this property appropriately.
*/
> + DEFINE_PROP_UINT32("num-irq", nvic_state, num_irq, 64),
> + DEFINE_PROP_END_OF_LIST(),
-- PMM
