On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé <phi...@linaro.org> wrote:
>
> This partly revert commit d48751ed4f ("xilinx-ethlite:
> Simplify byteswapping to/from brams") which states the
> packet data is stored in big-endian.
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
> @@ -102,8 +102,8 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
> D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
> break;
>
> - default:
> - r = tswap32(s->regs[addr]);
> + default: /* Packet data */
> + r = be32_to_cpu(s->regs[addr]);
> break;
> }
> return r;
> @@ -160,8 +160,8 @@ eth_write(void *opaque, hwaddr addr,
> s->regs[addr] = value;
> break;
>
> - default:
> - s->regs[addr] = tswap32(value);
> + default: /* Packet data */
> + s->regs[addr] = cpu_to_be32(value);
> break;
> }
> }
This is a change of behaviour for this device in the
qemu-system-microblazeel petalogix-s3adsp1800 board, because
previously on that system the bytes of the rx buffer would
appear in the registers in little-endian order and now they
will appear in big-endian order.
Edgar, do you know what the real hardware does here ?
thanks
-- PMM
