Peter Maydell wrote: > > "guest binaries don't actually rely that much on the memory model." > > > > I think the reason is those guest binaries are single thread. Memory model > > is > > important in multi-threaded case. BTW, our binary translator now can > > translate > > x86 binary to ARM binary, and ARM has weaker memory model than x86. > > Yes. At the moment this works for QEMU on ARM hosts because in > system mode QEMU itself is single-threaded so the nastier interactions > between multiple guest CPUs don't occur (just about every memory model > defines that memory interactions within a single thread of execution > behave in the obvious manner).
> I also had in mind that guest binaries > tend to make fairly stereotypical use of things like LDREX/STREX > rather than relying on obscure details like their interaction with > plain load/stores. As x86 doesn't use or need barrier instructions, when translating x86 to (say) run on ARM host, multi-threaded code that needs barriers isn't easy to detect, so barriers may be required between every memory access in the generated ARM code. -- Jamie
