> As x86 doesn't use or need barrier instructions, when translating x86 > to (say) run on ARM host, multi-threaded code that needs barriers > isn't easy to detect, so barriers may be required between every memory > access in the generated ARM code.
Sounds awful to me. Regardless current QEMU's support for multi-threaded application, it's possible to emulate a architecture with stronger memory model on a weaker one? Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj