On Thu, Mar 02, 2023 at 01:37:02PM +0000, Jonathan Cameron wrote:
> This register in AER should be both writeable and should
> have a default value with a couple of the errors masked
> including the Uncorrectable Internal Error used by CXL for
> it's error reporting.
>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
> Reviewed-by: Dave Jiang <dave.ji...@intel.com>
> ---
Reviewed-by: Fan Ni <fan...@samsung.com>
> hw/pci/pcie_aer.c | 4 ++++
> include/hw/pci/pcie_regs.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 9a19be44ae..909e027d99 100644
> --- a/hw/pci/pcie_aer.c
> +++ b/hw/pci/pcie_aer.c
> @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver,
> uint16_t offset,
>
> pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
> PCI_ERR_UNC_SUPPORTED);
> + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
> + PCI_ERR_UNC_MASK_DEFAULT);
> + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
> + PCI_ERR_UNC_SUPPORTED);
>
> pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
> PCI_ERR_UNC_SEVERITY_DEFAULT);
> diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
> index 963dc2e170..6ec4785448 100644
> --- a/include/hw/pci/pcie_regs.h
> +++ b/include/hw/pci/pcie_regs.h
> @@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth {
> PCI_ERR_UNC_ATOP_EBLOCKED | \
> PCI_ERR_UNC_TLP_PRF_BLOCKED)
>
> +#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \
> + PCI_ERR_UNC_TLP_PRF_BLOCKED)
> +
> #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \
> PCI_ERR_UNC_SDN | \
> PCI_ERR_UNC_FCP | \
> --
> 2.37.2
>
>
