On Thu, Mar 02, 2023 at 01:37:03PM +0000, Jonathan Cameron wrote:
> PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
> and Status Bits" includes a right hand branch under "All PCI Express devices"
> that allows for messages to be generated or sent onwards without SERR#
> being set as long as the appropriate per error class bit in the PCIe
> Device Control Register is set.
>
> Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
> and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
> Reviewed-by: Dave Jiang <dave.ji...@intel.com>
> ---
Reviewed-by: Fan Ni <fan...@samsung.com>
> hw/pci/pcie_aer.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 909e027d99..103667c368 100644
> --- a/hw/pci/pcie_aer.c
> +++ b/hw/pci/pcie_aer.c
> @@ -192,8 +192,16 @@ static void pcie_aer_update_uncor_status(PCIDevice *dev)
> static bool
> pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
> {
> + uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
> + PCI_EXP_DEVCTL);
> if (!(pcie_aer_msg_is_uncor(msg) &&
> - (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
> + (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
> + !((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
> + (devctl & PCI_EXP_DEVCTL_NFERE)) &&
> + !((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
> + (devctl & PCI_EXP_DEVCTL_CERE)) &&
> + !((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
> + (devctl & PCI_EXP_DEVCTL_FERE))) {
> return false;
> }
>
> --
> 2.37.2
>
>
