On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Create a new "d" RISCVCPUMisaExtConfig property that will update > env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are > replaced with riscv_has_ext(env, RVD). > > Remove the old "d" property and 'ext_d' from RISCVCPUConfig. > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 13 ++++++------- > target/riscv/cpu.h | 1 - > 2 files changed, 6 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 693ff10cab..9bb714d0d8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -812,13 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU > *cpu, Error **errp) > /* Do some ISA extension error checking */ > if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > riscv_has_ext(env, RVA) && > - cpu->cfg.ext_f && cpu->cfg.ext_d && > + cpu->cfg.ext_f && riscv_has_ext(env, RVD) && > cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > cpu->cfg.ext_i = true; > cpu->cfg.ext_m = true; > cpu->cfg.ext_f = true; > - cpu->cfg.ext_d = true; > cpu->cfg.ext_icsr = true; > cpu->cfg.ext_ifencei = true; > > @@ -874,7 +873,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU > *cpu, Error **errp) > return; > } > > - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { > + if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { > error_setg(errp, "D extension requires F extension"); > return; > } > @@ -894,7 +893,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU > *cpu, Error **errp) > cpu->cfg.ext_zve32f = true; > } > > - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { > + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { > error_setg(errp, "Zve64d/V extensions require D extension"); > return; > } > @@ -1104,7 +1103,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) > if (riscv_cpu_cfg(env)->ext_f) { > ext |= RVF; > } > - if (riscv_cpu_cfg(env)->ext_d) { > + if (riscv_has_ext(env, RVD)) { > ext |= RVD; > } > if (riscv_has_ext(env, RVC)) { > @@ -1439,6 +1438,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > .misa_bit = RVA, .enabled = true}, > {.name = "c", .description = "Compressed instructions", > .misa_bit = RVC, .enabled = true}, > + {.name = "d", .description = "Double-precision float point", > + .misa_bit = RVD, .enabled = true}, > }; > > static void riscv_cpu_add_misa_properties(Object *cpu_obj) > @@ -1466,7 +1467,6 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), > DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), > DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), > - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > @@ -1578,7 +1578,6 @@ static void register_cpu_props(Object *obj) > cpu->cfg.ext_e = misa_ext & RVE; > cpu->cfg.ext_m = misa_ext & RVM; > cpu->cfg.ext_f = misa_ext & RVF; > - cpu->cfg.ext_d = misa_ext & RVD; > cpu->cfg.ext_v = misa_ext & RVV; > cpu->cfg.ext_s = misa_ext & RVS; > cpu->cfg.ext_u = misa_ext & RVU; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c6dc24d236..e4cf79e36f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -423,7 +423,6 @@ struct RISCVCPUConfig { > bool ext_g; > bool ext_m; > bool ext_f; > - bool ext_d; > bool ext_s; > bool ext_u; > bool ext_h; > -- > 2.39.2 > >