Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI).
Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn> --- target/riscv/cpu.c | 15 +++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f53400d40f..2156cb380e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -810,13 +810,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i = true; cpu->cfg.ext_m = true; cpu->cfg.ext_icsr = true; cpu->cfg.ext_ifencei = true; @@ -825,13 +824,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) env->misa_ext_mask = env->misa_ext; } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); return; } - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); return; @@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers"); return; @@ -1088,7 +1087,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) { uint32_t ext = 0; - if (riscv_cpu_cfg(env)->ext_i) { + if (riscv_has_ext(env, RVI)) { ext |= RVI; } if (riscv_cpu_cfg(env)->ext_e) { @@ -1442,6 +1441,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVD, .enabled = true}, {.name = "f", .description = "Single-precision float point", .misa_bit = RVF, .enabled = true}, + {.name = "i", .description = "Base integer instruction set", + .misa_bit = RVI, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1464,7 +1465,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), @@ -1575,7 +1575,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext != 0) { - cpu->cfg.ext_i = misa_ext & RVI; cpu->cfg.ext_e = misa_ext & RVE; cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_v = misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ce23b1c431..573bf85ff1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -418,7 +418,6 @@ typedef struct { } RISCVSATPMap; struct RISCVCPUConfig { - bool ext_i; bool ext_e; bool ext_g; bool ext_m; -- 2.39.2