On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > The function is now a no-op for all cpu_init() callers that are setting > a non-zero misa value in set_misa(), since it's no longer used to sync > cpu->cfg props with env->misa_ext bits. Remove it in those cases. > > While we're at it, rename the function to match what it's actually > doing: create user properties to set/remove CPU extensions. Make a note > that it will overwrite env->misa_ext with the defaults set by each user > property. > > Update the MISA bits comment in cpu.h as well. > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 41 ++++++++++------------------------------- > target/riscv/cpu.h | 5 +---- > 2 files changed, 11 insertions(+), 35 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6988ff443a..d8568a024c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -221,7 +221,7 @@ static const char * const riscv_intr_names[] = { > "reserved" > }; > > -static void register_cpu_props(Object *obj); > +static void riscv_cpu_add_user_properties(Object *obj); > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > { > @@ -349,7 +349,6 @@ static void riscv_any_cpu_init(Object *obj) > #endif > > set_priv_version(env, PRIV_VERSION_1_12_0); > - register_cpu_props(obj); > } > > #if defined(TARGET_RISCV64) > @@ -358,7 +357,7 @@ static void rv64_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > - register_cpu_props(obj); > + riscv_cpu_add_user_properties(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > #ifndef CONFIG_USER_ONLY > @@ -370,7 +369,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_10_0); > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); > @@ -383,7 +381,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > #ifndef CONFIG_USER_ONLY > @@ -429,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > - register_cpu_props(obj); > + riscv_cpu_add_user_properties(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > #ifndef CONFIG_USER_ONLY > @@ -442,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV32, 0); > - register_cpu_props(obj); > + riscv_cpu_add_user_properties(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > #ifndef CONFIG_USER_ONLY > @@ -454,7 +451,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_10_0); > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); > @@ -467,7 +463,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > #ifndef CONFIG_USER_ONLY > @@ -481,7 +476,6 @@ static void rv32_ibex_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > #ifndef CONFIG_USER_ONLY > @@ -496,7 +490,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > - register_cpu_props(obj); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > #ifndef CONFIG_USER_ONLY > @@ -514,7 +507,7 @@ static void riscv_host_cpu_init(Object *obj) > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, 0); > #endif > - register_cpu_props(obj); > + riscv_cpu_add_user_properties(obj); > } > #endif > > @@ -1508,30 +1501,16 @@ static Property riscv_cpu_extensions[] = { > }; > > /* > - * Register CPU props based on env.misa_ext. If a non-zero > - * value was set, register only the required cpu->cfg.ext_* > - * properties and leave. env.misa_ext = 0 means that we want > - * all the default properties to be registered. > + * Add CPU properties with user-facing flags. > + * > + * This will overwrite existing env->misa_ext values with the > + * defaults set via riscv_cpu_add_misa_properties(). > */ > -static void register_cpu_props(Object *obj) > +static void riscv_cpu_add_user_properties(Object *obj) > { > - RISCVCPU *cpu = RISCV_CPU(obj); > Property *prop; > DeviceState *dev = DEVICE(obj); > > - /* > - * If misa_ext is not zero, set cfg properties now to > - * allow them to be read during riscv_cpu_realize() > - * later on. > - */ > - if (cpu->env.misa_ext != 0) { > - /* > - * We don't want to set the default riscv_cpu_extensions > - * in this case. > - */ > - return; > - } > - > riscv_cpu_add_misa_properties(obj); > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ce92e8393d..02f26130d5 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -65,10 +65,7 @@ > > #define RV(x) ((target_ulong)1 << (x - 'A')) > > -/* > - * Consider updating register_cpu_props() when adding > - * new MISA bits here. > - */ > +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ > #define RVI RV('I') > #define RVE RV('E') /* E and I are mutually exclusive */ > #define RVM RV('M') > -- > 2.39.2 > >