On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Create a new "m" RISCVCPUMisaExtConfig property that will update > env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are > replaced with riscv_has_ext(env, RVM). > > Remove the old "m" property and 'ext_m' from RISCVCPUConfig. > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 10 +++++----- > target/riscv/cpu.h | 1 - > 2 files changed, 5 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9cf3ab3988..6861446489 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -810,13 +810,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU > *cpu, Error **errp) > CPURISCVState *env = &cpu->env; > > /* Do some ISA extension error checking */ > - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && > + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && > + riscv_has_ext(env, RVM) && > riscv_has_ext(env, RVA) && > riscv_has_ext(env, RVF) && > riscv_has_ext(env, RVD) && > cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > - cpu->cfg.ext_m = true; > cpu->cfg.ext_icsr = true; > cpu->cfg.ext_ifencei = true; > > @@ -1093,7 +1093,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) > if (riscv_has_ext(env, RVE)) { > ext |= RVE; > } > - if (riscv_cpu_cfg(env)->ext_m) { > + if (riscv_has_ext(env, RVM)) { > ext |= RVM; > } > if (riscv_has_ext(env, RVA)) { > @@ -1445,6 +1445,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { > .misa_bit = RVI, .enabled = true}, > {.name = "e", .description = "Base integer instruction set (embedded)", > .misa_bit = RVE, .enabled = false}, > + {.name = "m", .description = "Integer multiplication and division", > + .misa_bit = RVM, .enabled = true}, > }; > > static void riscv_cpu_add_misa_properties(Object *cpu_obj) > @@ -1468,7 +1470,6 @@ static void riscv_cpu_add_misa_properties(Object > *cpu_obj) > static Property riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), > - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > @@ -1576,7 +1577,6 @@ static void register_cpu_props(Object *obj) > * later on. > */ > if (cpu->env.misa_ext != 0) { > - cpu->cfg.ext_m = misa_ext & RVM; > cpu->cfg.ext_v = misa_ext & RVV; > cpu->cfg.ext_s = misa_ext & RVS; > cpu->cfg.ext_u = misa_ext & RVU; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index cc0b9e73ac..7a42c80b7d 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -419,7 +419,6 @@ typedef struct { > > struct RISCVCPUConfig { > bool ext_g; > - bool ext_m; > bool ext_s; > bool ext_u; > bool ext_h; > -- > 2.39.2 > >