On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> Let's remove more code that is open coded in riscv_cpu_realize() and put
> it into a helper. Let's also add an error message instead of just
> asserting out if env->misa_mxl_max != env->misa_mlx.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
> Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 33 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8f0620376c..e8045840bd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -866,6 +866,33 @@ static void
> riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> }
> }
>
> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> + CPUClass *cc = CPU_CLASS(mcc);
> + CPURISCVState *env = &cpu->env;
> +
> + /* Validate that MISA_MXL is set properly. */
> + switch (env->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + case MXL_RV128:
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> + break;
> +#endif
> + case MXL_RV32:
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + if (env->misa_mxl_max != env->misa_mxl) {
> + error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
> + return;
> + }
> +}
> +
> /*
> * Check consistency between chosen extensions while setting
> * cpu->cfg accordingly.
> @@ -1134,7 +1161,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> RISCVCPU *cpu = RISCV_CPU(dev);
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> - CPUClass *cc = CPU_CLASS(mcc);
> Error *local_err = NULL;
>
> cpu_exec_realizefn(cs, &local_err);
> @@ -1143,6 +1169,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + riscv_cpu_validate_misa_mxl(cpu, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> riscv_cpu_validate_priv_spec(cpu, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1171,22 +1203,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> #endif /* CONFIG_USER_ONLY */
>
> - /* Validate that MISA_MXL is set properly. */
> - switch (env->misa_mxl_max) {
> -#ifdef TARGET_RISCV64
> - case MXL_RV64:
> - case MXL_RV128:
> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> - break;
> -#endif
> - case MXL_RV32:
> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - assert(env->misa_mxl_max == env->misa_mxl);
> -
> riscv_cpu_validate_set_extensions(cpu, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> --
> 2.39.2
>
>
