With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh Kanwal <rkan...@rivosinc.com> --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..90460cfe64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1288,6 +1288,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + /* With H-Ext VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ + if (riscv_has_ext(env, RVH)) { + env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); -- 2.25.1