On Thu, May 18, 2023 at 4:21 PM Loïc Lefort <l...@rivosinc.com> wrote: > > Is there a reason to keep RISCV_EXCP_SEMIHOST handling separate from other > exceptions? > Otherwise it could be moved in the switch block just a few lines below.
I agree. I will move it to the switch in the next series. Thanks > > On Thu, May 18, 2023 at 1:39 PM Rajnesh Kanwal <rkan...@rivosinc.com> wrote: >> >> RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local >> interrupt as well. This change adds a check for async flag >> before invoking semihosting logic. >> >> Signed-off-by: Rajnesh Kanwal <rkan...@rivosinc.com> >> --- >> target/riscv/cpu_helper.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index 57d04385f1..c78a2a9514 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) >> target_ulong htval = 0; >> target_ulong mtval2 = 0; >> >> - if (cause == RISCV_EXCP_SEMIHOST) { >> + if (!async && cause == RISCV_EXCP_SEMIHOST) { >> do_common_semihosting(cs); >> env->pc += 4; >> return; >> -- >> 2.25.1 >> >>