Jonathan Cameron <jonathan.came...@huawei.com> writes:
> Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
> provides information related to DRAM devices.
>
> Example injection command in QMP:
>
> { "execute": "cxl-inject-dram-event",
> "arguments": {
> "path": "/machine/peripheral/cxl-mem0",
> "log": "informational",
> "flags": 1,
> "dpa": 1000,
> "descriptor": 3,
> "type": 3,
> "transaction-type": 192,
> "channel": 3,
> "rank": 17,
> "nibble-mask": 37421234,
> "bank-group": 7,
> "bank": 11,
> "row": 2,
> "column": 77,
> "correction-mask": [33, 44, 55,66]
> }}
>
> Reviewed-by: Ira Weiny <ira.we...@intel.com>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
>
> ---
> v7: Additional documentation, plus rename physaddr to dpa reduce
> confusion
> ---
> qapi/cxl.json | 63 ++++++++++++++++++++
> include/hw/cxl/cxl_events.h | 23 +++++++
> hw/mem/cxl_type3.c | 116 ++++++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 13 ++++
> 4 files changed, 215 insertions(+)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 7700e26a0d..ce9adcbc55 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -84,6 +84,69 @@
> '*channel': 'uint8', '*rank': 'uint8',
> '*device': 'uint32', '*component-id': 'str' } }
>
> +##
> +# @cxl-inject-dram-event:
> +#
> +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2)
Period at end of sentence, please.
> +# This event type is reported via one of the event logs specified via
> +# the log parameter.
> +#
> +# @path: CXL type 3 device canonical QOM path
> +#
> +# @log: Event log to add the event to
> +#
> +# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> +# Record Format, Event Record Flags for subfield definitions.
> +#
> +# @dpa: Device Physical Address (relative to @path device). Note lower
> +# bits include some flags. See CXL r3.0 Table 8-44 DRAM Event
> +# Record, Physical Address.
> +#
> +# @descriptor: Memory Event Descriptor with additional memory
> +# event information. See CXL r3.0 Table 8-44 DRAM Event
> +# Record, Memory Event Descriptor for bit definitions.
> +#
> +# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
> +# DRAM Event Record, Memory Event Type for possible values.
> +#
> +# @transaction-type: Type of first transaction that caused the event
> +# to occur. See CXL r3.0 Table 8-44 DRAM Event
> +# Record, Transaction Type for possible values.
> +#
> +# @channel: The channel of the memory event location. A channel is
> +# an interface that can be independently accessed for a
> +# transaction.
> +#
> +# @rank: The rank of the memory event location. A rank is a set of
> +# memory devices on a channel that together execute a
> +# transaction.
> +#
> +# @nibble-mask: Identify one or more nibbles that the error affects
"Identifies", I think.
> +#
> +# @bank-group: Bank group of the memory event location, incorporating
> +# a number of Banks.
> +#
> +# @bank: Bank of the memory event location. A single bank is accessed
> +# per read or write of the memory.
> +#
> +# @row: Row address within the DRAM.
> +#
> +# @column: Column address within the DRAM.
> +#
> +# @correction-mask: Bits within each nibble. Used in order of bits set
> +# in the nibble-mask. Up to 4 nibbles may be covered.
Please format like
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
# Event Record, Physical Address.
#
# @descriptor: Memory Event Descriptor with additional memory event
# information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
# Event Descriptor for bit definitions.
#
# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
# DRAM Event Record, Memory Event Type for possible values.
#
# @transaction-type: Type of first transaction that caused the event
# to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
# Transaction Type for possible values.
#
# @channel: The channel of the memory event location. A channel is an
# interface that can be independently accessed for a transaction.
#
# @rank: The rank of the memory event location. A rank is a set of
# memory devices on a channel that together execute a transaction.
#
# @nibble-mask: Identifies one or more nibbles that the error affects
#
# @bank-group: Bank group of the memory event location, incorporating
# a number of Banks.
#
# @bank: Bank of the memory event location. A single bank is accessed
# per read or write of the memory.
#
# @row: Row address within the DRAM.
#
# @column: Column address within the DRAM.
#
# @correction-mask: Bits within each nibble. Used in order of bits
# set in the nibble-mask. Up to 4 nibbles may be covered.
to blend in with recent commit a937b6aa739 (qapi: Reformat doc comments
to conform to current conventions).
> +#
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-dram-event',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'dpa': 'uint64', 'descriptor': 'uint8',
> + 'type': 'uint8', 'transaction-type': 'uint8',
> + '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> + '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + }}
> +
> ##
> # @cxl-inject-poison:
> #
With these tweaks
Acked-by: Markus Armbruster <arm...@redhat.com>
[...]
