This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 17 +++++++++++++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++++++++++++++++
target/loongarch/insns.decode | 18 ++++++++++++++++++
3 files changed, 52 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index eefd16e3f1..2a2993cb95 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1748,6 +1748,23 @@ INSN_LASX(xvneg_h, xx)
INSN_LASX(xvneg_w, xx)
INSN_LASX(xvneg_d, xx)
+INSN_LASX(xvsadd_b, xxx)
+INSN_LASX(xvsadd_h, xxx)
+INSN_LASX(xvsadd_w, xxx)
+INSN_LASX(xvsadd_d, xxx)
+INSN_LASX(xvsadd_bu, xxx)
+INSN_LASX(xvsadd_hu, xxx)
+INSN_LASX(xvsadd_wu, xxx)
+INSN_LASX(xvsadd_du, xxx)
+INSN_LASX(xvssub_b, xxx)
+INSN_LASX(xvssub_h, xxx)
+INSN_LASX(xvssub_w, xxx)
+INSN_LASX(xvssub_d, xxx)
+INSN_LASX(xvssub_bu, xxx)
+INSN_LASX(xvssub_hu, xxx)
+INSN_LASX(xvssub_wu, xxx)
+INSN_LASX(xvssub_du, xxx)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index cea944c3ba..ec68193686 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -131,6 +131,23 @@ TRANS(xvneg_h, gvec_xx, MO_16, tcg_gen_gvec_neg)
TRANS(xvneg_w, gvec_xx, MO_32, tcg_gen_gvec_neg)
TRANS(xvneg_d, gvec_xx, MO_64, tcg_gen_gvec_neg)
+TRANS(xvsadd_b, gvec_xxx, MO_8, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_h, gvec_xxx, MO_16, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_w, gvec_xxx, MO_32, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_d, gvec_xxx, MO_64, tcg_gen_gvec_ssadd)
+TRANS(xvsadd_bu, gvec_xxx, MO_8, tcg_gen_gvec_usadd)
+TRANS(xvsadd_hu, gvec_xxx, MO_16, tcg_gen_gvec_usadd)
+TRANS(xvsadd_wu, gvec_xxx, MO_32, tcg_gen_gvec_usadd)
+TRANS(xvsadd_du, gvec_xxx, MO_64, tcg_gen_gvec_usadd)
+TRANS(xvssub_b, gvec_xxx, MO_8, tcg_gen_gvec_sssub)
+TRANS(xvssub_h, gvec_xxx, MO_16, tcg_gen_gvec_sssub)
+TRANS(xvssub_w, gvec_xxx, MO_32, tcg_gen_gvec_sssub)
+TRANS(xvssub_d, gvec_xxx, MO_64, tcg_gen_gvec_sssub)
+TRANS(xvssub_bu, gvec_xxx, MO_8, tcg_gen_gvec_ussub)
+TRANS(xvssub_hu, gvec_xxx, MO_16, tcg_gen_gvec_ussub)
+TRANS(xvssub_wu, gvec_xxx, MO_32, tcg_gen_gvec_ussub)
+TRANS(xvssub_du, gvec_xxx, MO_64, tcg_gen_gvec_ussub)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 78452c622c..be706fe0f7 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1340,6 +1340,24 @@ xvneg_h 0111 01101001 11000 01101 ..... .....
@xx
xvneg_w 0111 01101001 11000 01110 ..... ..... @xx
xvneg_d 0111 01101001 11000 01111 ..... ..... @xx
+xvsadd_b 0111 01000100 01100 ..... ..... ..... @xxx
+xvsadd_h 0111 01000100 01101 ..... ..... ..... @xxx
+xvsadd_w 0111 01000100 01110 ..... ..... ..... @xxx
+xvsadd_d 0111 01000100 01111 ..... ..... ..... @xxx
+xvsadd_bu 0111 01000100 10100 ..... ..... ..... @xxx
+xvsadd_hu 0111 01000100 10101 ..... ..... ..... @xxx
+xvsadd_wu 0111 01000100 10110 ..... ..... ..... @xxx
+xvsadd_du 0111 01000100 10111 ..... ..... ..... @xxx
+
+xvssub_b 0111 01000100 10000 ..... ..... ..... @xxx
+xvssub_h 0111 01000100 10001 ..... ..... ..... @xxx
+xvssub_w 0111 01000100 10010 ..... ..... ..... @xxx
+xvssub_d 0111 01000100 10011 ..... ..... ..... @xxx
+xvssub_bu 0111 01000100 11000 ..... ..... ..... @xxx
+xvssub_hu 0111 01000100 11001 ..... ..... ..... @xxx
+xvssub_wu 0111 01000100 11010 ..... ..... ..... @xxx
+xvssub_du 0111 01000100 11011 ..... ..... ..... @xxx
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @xr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @xr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @xr
--
2.39.1
