The previous check was failing with: ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid combination.
Fix the check to correctly match the specification by using minimum SEW rather than the active SEW. >From the specification: "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. In the standard extensions, SEWMIN=8. For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported." >From inspection this new check allows: ELEN=64 1/2, 1/4, 1/8 (encoded as 7, 6, 5 respectfully) ELEN=32 1/2, 1/4 (encoded as 7 and 6 respectfully) Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford <rbradf...@rivosinc.com> --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1e06e7447c..8dfd8fe484 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, xlen - 1 - R_VTYPE_RESERVED_SHIFT); if (lmul & 4) { - /* Fractional LMUL. */ + /* Fractional LMUL - check LMUL >= ELEN/SEW_MIN (8) */ if (lmul == 4 || - cpu->cfg.elen >> (8 - lmul) < sew) { + cpu->cfg.elen >> (8 - lmul) < 8) { vill = true; } } -- 2.41.0