A proposal for an extension of the J1 expansion connector to three rows. The intent is for it to be backwards compatible with all traditional 64-pin expansion cards.
The purpose of the 96-pin expansion connector is: * to increase address and data space for 32-bit CPUs by adding D8-D31 and A20,A21 * improve grounding * to release some pins that were never used in any expansion: RED, GREEN, BLUE, VSYNC and CSYNC * to retain full backwards compatibility The version number of this proposal is currently V0.1 DISCLAIMER: This proposal is based on my experience with 68008, 68000 and 68020 CPUs. Other CPUs may take advantage of different features. If you're aware of changes that would facilitate the widest range of CPUs, please let me know. DISCUSSION: The QL Forum (http://www.qlforum.co.uk/viewtopic.php?f=2&t=729) will be used for a consultation period lasting until February 28th 2014. After that, the resulting expansion will be considered defined. The standard will be under continual review, but any changes will be backwards compatible to ensure interoperability. All future expansions can optionally use the traditional DIN41612 2-row connector, or the expanded 3-row connector. This will be an open standard. If any party intends to make a motherboard or expansion that uses the new standard, they can use it royalty free and without obtaining consent. I, Dave Park, will maintain the standard, and will take requests for designation of available pins by mounting a discussion like this one, then adopting and revising the standard. Any reasonable proposal can be adopted after a 14 day consultation period in a public forum. Video: To my knowledge, the RED, GREEN, BLUE, VSYNC and HSYNC pins were never used on any mass-produced expansion. Because of their purpose, expansion cards neither tied these to ground or connected them in any way. Further, these lines introduce a lot of noise across the board. It is proposed to deprecate these tags, and to make a12 "A19" and b13 "A20" - thereby expanding the address range. If anyone knows of any reasonable objection, or benefit to address lines beyond A21 (4MB), please discuss below. Additional lines: Adding row C allows 32 extra pins. This allows the extension of DATA lines to encompass 32-bit CPUs. It also allows the expansion of the 68008's combined IPL0/2 to two separate lines, IPL0 and IPL2. Two pairs of ground pins are provided in row c. This serves a dual purpose: the primary purpose is to allow improved grounding to expansions. The secondary purpose is that, by the addition of two jumpers, it is possible to prevent accidental wrong insertion of a 2-row card in a 3-row socket in the -BC position. The provisional revised expansion connector is listed at http://www.qlforum.co.uk/viewtopic.php?f=2&t=729 Changes are highlighted in green. Changes that generate ongoing discussion will be changed to yellow, and changes that create controversy will be highlighted in red. If you do not wish to join the QL Forum, discussion here will be reflected in the standard also. -- Dave Park Sandy Electronics, LLC d...@sinclairql.com _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
