In message <4552f0907735844e9204a62bbdd325e732aff...@nkgeml508-mbx.china.huawei.com> Mingui Zhang writes: > Hannes, > > That's the dream of line-card hardware manufactures. If the hardware > is 100% power proportional, then PANET will become useless. > > However, the practice is that only 10%-15% power proportional is > possible, which means a high 85%-90% of baseline power is being wasted > when there is few traffic. > > Thanks, > Mingui
Is this a measured value, and if so, measured on what type of equipment? That seems to me to indicate very high leakage power in an NPU or ASIC if the NPU and ASIC is 50% or more of board power. Did you mean to say that an idle card runs at 85-90% of the power that it would run at with a full packet load? AFAIK only certain types of logic blocks like SRAM have high ratio of leakage to active power. Plain old logic gates have a high active to leakage ratio and for a given logic block you need to know what percentage of the gates tend to be in an active state at any given time. TCAM, when in use, has a very high active power because almost all the gates, except those in disabled banks, go active when doing a TCAM lookup. I'm not an ASIC designer, far from it, but I've reviewed the results of ASIC designers going through this power estimation exercise. If I remember correctly, active power was higher than leakage overall for NPU and other ASIC used in routers and transport. Active power is important enough that chips draw more power and run hotter when testing with small packet loads that with a larger average packet size (the so called Intenet mix or IMIX testing). I remember having a conversation with a chip vendor about the likelyhood of anyone doing a continuous 40 byte packet test at max NEBS temps and whether the intersection of those two requirements was needed. Curtis _______________________________________________ rtgwg mailing list [email protected] https://www.ietf.org/mailman/listinfo/rtgwg
