I will try to figure that out , i am not very known with PCI programming
so that will be a weekend job :-) First look is that they have a
structure like this:
WAITFIFO(4);
OUTREG(PAT_FG_CLR, planemask);
OUTREG(MONO_PAT_0, ~0);
OUTREG(MONO_PAT_1, ~0);
where WAITFIFO is :
#define WAITFIFO(n) if(ps3v->NoPCIRetry) \
while(((INREG(SUBSYS_STAT_REG) >> 8) & 0x1f) < n){}
So the NoPCIRetry option disables/enables the wait , if i understand
correct.
Altough at the moment i have a bit of the problem understanding it.
when NoPCIRetry is true it does the wait for FIFO space, and else the
PCI
chipset does the retry by itself ??
Anybody that could explain that in short ? :-) Or any pointeres to
good PCI docs that explain it ?.
TIA,
Erwin
John Regehr wrote:
>
> > an other question, is there anyway to figure out if it is caused by
> > "lockingup" the PCI-bus , without a logic-analizer or scoop ?
>
> Look in the driver sources and find the code that writes commands to the
> FIFO on the video board. It's probably a macro. Make sure that it
> checks the status of the FIFO before writing to it.
>
> John Regehr
>
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