From: Geoff Winkless <[EMAIL PROTECTED]> > Please understand that I'm not trying to be awkward; I just don't comprehend > the logic.
No prob. I hadn't looked this close on ROM Display contention before so it is interesting to look into and discuss it, also a reminder to get on with a Z80 T-States list for SAM I hope this makes it little less confusing and help you understand the logic a bit more: The ASIC allowes the Z80 to access RAM only once in every 4Ts(RAM) or 8Ts(Display) at the exact same moment. For convenience, lets say only on the 1st of every 4Ts or 8Ts. Now when the Z80 tries to access RAM on the 2nd the ASIC tells the Z80 to wait for 3Ts or 7Ts. Before I used the notation 3+5 to tell the NEXT memory cycle in RAM will be delayed by 5 Wait States. It is more confenient to write it like this. But it can be confusing. To make it less confusing I will use the following formulas to tell how many wait states there will be on a RAM memory cycle. RAM contention: Wait states = 4-(T MOD 4) Display contention: Wait states = 8-(T MOD 8) where T is the number of Tstates passed before the cycle starts. So looking at the LDIR again with Z80 is in 'in sync' (the moment where (T MOD 4)=0 or (T MOD 8) =0) with ASIC. The numbers in [] are the number of Ts passed before the cycle: 1st: LDIR [0] 4,4 (LDIR) >in ROM, no contention [8] 3 (read from RAM) > 8-([8] MOD 8)=0 wait states [11] 5 (store in RAM ,adjust regs) > 8-([11] MOD 8)=5 Wait States [21] 5 (BC<>0 PC-2) > internal, no wait states 2nd LDIR: [26] 4,4 (LDIR) >in ROM, no contention [34] 3 (read from RAM) > 8-([34] MOD 8)=6 wait states [43] 5 (store in RAM ,adjust regs) > 8-([43] MOD 8)=5 Wait States [53] 5 (BC<>0 PC-2) > internal, no wait states [58] The 1st LDIR takes 26T when Z80 is 'in Sync' then the 2nd to 2nd last will take 32T each The last one takes 21T. In case of the call to the ROM LDIR routine the first LDIR will take 31Ts(5Ts to get in sync) and after the last one there will be an extra 7 wait states for fetching the LSB return address for RET ie: [21+(BC-1)*32] 4 RET > in rom, no contention [25+(BC-1)*32] 3 LSB from stack > 8-([25+(BC-1)*32] MOD 8)=7 wait states [35+(BC-1)*32] 3 MSB from stack > 8-([35+(BC-1)*32] MOD 8)=5 wait states Is it less confusing now or did I give you an headache ? I'll save the ASIC I/O part for a later time ;-) For a list what would you prefer or would be less confusing : RET 10 (4,3,3) 12 (4,1+3,1+3) 24 (4+4,5+3,5+3) 1+.. Number of Wait states added. or RET 10 (4,3,3) 12 (4,3+1,3+1) 24 (4+4,3+5,3+5) ..+1 Number of Wait states added. Edwin
