Indeed, the patch you provided works for both CSM in QEMU mode and
QEMU's bios.bin mode.
Testing Results (For this whole time, just for reference):
EDK2 Build Revision: e7d7f02c8e157e936855a091948757f78c7d0298
SeaBIOS Build Revision: df9dd418b3b0e586cb208125094620fc7f90f23d
(SeaBIOS with your patch applied from your last message)
QEMU Build Revision: 621da7789083b80d6f1ff1c0fb499334007b4f51
QEMU command line I used is too long, but if you want it anyways, please
do ask!
In short, I used pc-i440fx-7.1 with a Vista Install CD and Vista
installed QCOW2 Image, and switched between the firmware with the -bios
command-line option.
- Christopher Lentocha <christopherericlento...@gmail.com>
On 2/6/25 6:14 AM, Gerd Hoffmann wrote:
On Wed, Feb 05, 2025 at 10:53:04AM -0500, Christopher Lentocha wrote:
Is it already pushed?
Nope, apparently something went wrong ...
I think I need to add a `if (CONFIG_CSM) {` to it
because I think it wasn't working with the regual bios.bin without CSM
Does a controller reset (see below) work in both cases?
take care,
Gerd
commit 79d50d3c156dfd15ed710d0e2313d113251aeb2e
Author: Gerd Hoffmann <kra...@redhat.com>
Date: Thu Feb 6 12:10:21 2025 +0100
ahci: add controller reset
diff --git a/src/hw/ahci.c b/src/hw/ahci.c
index 4f0f640a1c64..2285d33d4ae2 100644
--- a/src/hw/ahci.c
+++ b/src/hw/ahci.c
@@ -637,7 +637,7 @@ static void
ahci_controller_setup(struct pci_device *pci)
{
struct ahci_port_s *port;
- u32 val, pnr, max;
+ u32 pnr, max;
if (create_bounce_buf() < 0)
return;
@@ -660,8 +660,8 @@ ahci_controller_setup(struct pci_device *pci)
pci_enable_busmaster(pci);
- val = ahci_ctrl_readl(ctrl, HOST_CTL);
- ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
+ ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET);
+ ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN);
ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
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