[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
preames wrote: @BeMg Can you rebase over commit [d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)? https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
preames wrote: I've gone ahead and merged this into main. We have missed the branch creation, so without further action this will not be included in 19.x. We need to ensure the constructor change for compiler-rt lands, and then backport them together if we choose to. https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark zacas as experimental again due to unresolved ABI issue (PR #99898)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/99898 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
preames wrote:
I think this question needs some focused discussion.
My initial stab at this would be something along the following:
* Reorder any super set of extensions before a subset.
* Respect user provided order otherwise.
>From the precedent you point to, we can reasonably treat the ordering an
>implementation defined heuristic. We should document that.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/4] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_supports
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins
(which have a much narrower user interface), and the avoidance of
false generality. This change deliberately only handles group 0
extensions (which happen to be all defined ones today), and avoids
the tblgen changes from that review.
This is still a WIP. It is posted for initial feedback on whether
this makes sense to try to get into 19.x release. Major items left
undone:
* Updating clang tests to exercise this logic.
* Actually running it at all. I did not build compiler-rt, and thus
all my checking was of generated asm/IR.
* Investigate claims from gcc docs that __builtin_cpu_init is called
early in process lifetime with high priority constructor. I did
not find this with some quick searching.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.h | 4 ++
clang/lib/CodeGen/CGBuiltin.cpp | 55 +
clang/lib/CodeGen/CodeGenFunction.h | 3 +
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 4 ++
llvm/lib/TargetParser/RISCVISAInfo.cpp| 61 +++
6 files changed, 133 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 9159162f01d1b..41d836330b38c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -479,3 +479,9 @@ RISCVTargetInfo::checkCallingConvention(CallingConv CC)
const {
return CCCR_OK;
}
}
+
+bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const {
+ // Only allow extensions we have a known bit position for in the
+ // __riscv_feature_bits structure.
+ return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitPosition(Feature);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index d5df6344bedc0..626274b8fc437 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -126,6 +126,10 @@ class RISCVTargetInfo : public TargetInfo {
std::pair hardwareInterferenceSizes() const override {
return std::make_pair(32, 32);
}
+
+ bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
+ bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
+ bool validateCpuSupports(StringRef Feature) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2ad62d6ee0bb2..71c947776adf2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -62,6 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include
#include
@@ -14215,6 +14217,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitRISCVCpuInit() {
+ llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
+ auto *CalleeGV = cast(Func.getCallee());
+ CalleeGV->setDSOLocal(true);
+ CalleeGV->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+ return Builder.CreateCall(Func);
+}
+
Value *CodeGenFunction::EmitX86CpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy,
/*Variadic*/ false);
@@ -14267,6 +14279,43 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(const CallExpr *E) {
+
+ const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef FeatureStr = cast(FeatureExpr)->getString();
+ if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
+return Builder.getFalse();
+
+ // Note: We are making an unchecked assumption that the size of the
+ // feature array is >= 1. This holds for any version of compiler-rt
+ // which defines this interface.
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, 1);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/3] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_supports
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins
(which have a much narrower user interface), and the avoidance of
false generality. This change deliberately only handles group 0
extensions (which happen to be all defined ones today), and avoids
the tblgen changes from that review.
This is still a WIP. It is posted for initial feedback on whether
this makes sense to try to get into 19.x release. Major items left
undone:
* Updating clang tests to exercise this logic.
* Actually running it at all. I did not build compiler-rt, and thus
all my checking was of generated asm/IR.
* Investigate claims from gcc docs that __builtin_cpu_init is called
early in process lifetime with high priority constructor. I did
not find this with some quick searching.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.h | 4 ++
clang/lib/CodeGen/CGBuiltin.cpp | 55 +
clang/lib/CodeGen/CodeGenFunction.h | 3 +
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 4 ++
llvm/lib/TargetParser/RISCVISAInfo.cpp| 61 +++
6 files changed, 133 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 9159162f01d1b..41d836330b38c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -479,3 +479,9 @@ RISCVTargetInfo::checkCallingConvention(CallingConv CC)
const {
return CCCR_OK;
}
}
+
+bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const {
+ // Only allow extensions we have a known bit position for in the
+ // __riscv_feature_bits structure.
+ return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitPosition(Feature);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index d5df6344bedc0..626274b8fc437 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -126,6 +126,10 @@ class RISCVTargetInfo : public TargetInfo {
std::pair hardwareInterferenceSizes() const override {
return std::make_pair(32, 32);
}
+
+ bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
+ bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
+ bool validateCpuSupports(StringRef Feature) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2ad62d6ee0bb2..71c947776adf2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -62,6 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include
#include
@@ -14215,6 +14217,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitRISCVCpuInit() {
+ llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
+ auto *CalleeGV = cast(Func.getCallee());
+ CalleeGV->setDSOLocal(true);
+ CalleeGV->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+ return Builder.CreateCall(Func);
+}
+
Value *CodeGenFunction::EmitX86CpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy,
/*Variadic*/ false);
@@ -14267,6 +14279,43 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(const CallExpr *E) {
+
+ const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef FeatureStr = cast(FeatureExpr)->getString();
+ if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
+return Builder.getFalse();
+
+ // Note: We are making an unchecked assumption that the size of the
+ // feature array is >= 1. This holds for any version of compiler-rt
+ // which defines this interface.
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, 1);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64_t bitpos;
+};
+
+/// Maps extensions with assigned bit positions within group 0 of
+/// __riscv_features_bits to their respective bit position. At the
+/// moment all extensions are within group 0.
+static RISCVExtBit RISCVGroup0BitPositions[] = {
preames wrote:
IMO, adding the additional information to RISCVFeatures.td just complicates
things.
https://github.com/llvm/llvm-project/pull/99700
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/2] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_supports
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins
(which have a much narrower user interface), and the avoidance of
false generality. This change deliberately only handles group 0
extensions (which happen to be all defined ones today), and avoids
the tblgen changes from that review.
This is still a WIP. It is posted for initial feedback on whether
this makes sense to try to get into 19.x release. Major items left
undone:
* Updating clang tests to exercise this logic.
* Actually running it at all. I did not build compiler-rt, and thus
all my checking was of generated asm/IR.
* Investigate claims from gcc docs that __builtin_cpu_init is called
early in process lifetime with high priority constructor. I did
not find this with some quick searching.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.h | 4 ++
clang/lib/CodeGen/CGBuiltin.cpp | 55 +
clang/lib/CodeGen/CodeGenFunction.h | 3 +
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 4 ++
llvm/lib/TargetParser/RISCVISAInfo.cpp| 61 +++
6 files changed, 133 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 9159162f01d1b..41d836330b38c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -479,3 +479,9 @@ RISCVTargetInfo::checkCallingConvention(CallingConv CC)
const {
return CCCR_OK;
}
}
+
+bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const {
+ // Only allow extensions we have a known bit position for in the
+ // __riscv_feature_bits structure.
+ return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitPosition(Feature);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index d5df6344bedc0..626274b8fc437 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -126,6 +126,10 @@ class RISCVTargetInfo : public TargetInfo {
std::pair hardwareInterferenceSizes() const override {
return std::make_pair(32, 32);
}
+
+ bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
+ bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
+ bool validateCpuSupports(StringRef Feature) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2ad62d6ee0bb2..71c947776adf2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -62,6 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include
#include
@@ -14215,6 +14217,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitRISCVCpuInit() {
+ llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
+ auto *CalleeGV = cast(Func.getCallee());
+ CalleeGV->setDSOLocal(true);
+ CalleeGV->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+ return Builder.CreateCall(Func);
+}
+
Value *CodeGenFunction::EmitX86CpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy,
/*Variadic*/ false);
@@ -14267,6 +14279,43 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(const CallExpr *E) {
+
+ const Expr *FeatureExpr = E->getArg(0)->IgnoreParenCasts();
+ StringRef FeatureStr = cast(FeatureExpr)->getString();
+ if (!getContext().getTargetInfo().validateCpuSupports(FeatureStr))
+return Builder.getFalse();
+
+ // Note: We are making an unchecked assumption that the size of the
+ // feature array is >= 1. This holds for any version of compiler-rt
+ // which defines this interface.
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, 1);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
preames wrote: I have posted a cut down version of this which implements __builtin_cpu_supports and __builtin_cpu_init. I posted an early draft to avoid potentially duplicated work. If we're going to get any part of this in for the release branch, we don't have much time. See https://github.com/llvm/llvm-project/pull/99700 https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/99700
This implements the __builtin_cpu_init and __builtin_cpu_supports builtin
routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786. Major
changes are a) a restriction in scope to only the builtins (which have a much
narrower user interface), and the avoidance of false generality. This change
deliberately only handles group 0 extensions (which happen to be all defined
ones today), and avoids the tblgen changes from that review.
This is still a WIP. It is posted for initial feedback on whether this makes
sense to try to get into 19.x release. Major items left undone:
* Updating clang tests to exercise this logic.
* Actually running it at all. I did not build compiler-rt, and thus all my
checking was of generated asm/IR.
* Investigate claims from gcc docs that __builtin_cpu_init is called early in
process lifetime with high priority constructor. I did not find this with some
quick searching.
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_supports
This implements the __builtin_cpu_init and __builtin_cpu_supports
builtin routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.com/llvm/llvm-project/pull/85786.
Major changes are a) a restriction in scope to only the builtins
(which have a much narrower user interface), and the avoidance of
false generality. This change deliberately only handles group 0
extensions (which happen to be all defined ones today), and avoids
the tblgen changes from that review.
This is still a WIP. It is posted for initial feedback on whether
this makes sense to try to get into 19.x release. Major items left
undone:
* Updating clang tests to exercise this logic.
* Actually running it at all. I did not build compiler-rt, and thus
all my checking was of generated asm/IR.
* Investigate claims from gcc docs that __builtin_cpu_init is called
early in process lifetime with high priority constructor. I did
not find this with some quick searching.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.h | 4 ++
clang/lib/CodeGen/CGBuiltin.cpp | 55 +
clang/lib/CodeGen/CodeGenFunction.h | 3 +
llvm/include/llvm/TargetParser/RISCVISAInfo.h | 4 ++
llvm/lib/TargetParser/RISCVISAInfo.cpp| 61 +++
6 files changed, 133 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 9159162f01d1b..41d836330b38c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -479,3 +479,9 @@ RISCVTargetInfo::checkCallingConvention(CallingConv CC)
const {
return CCCR_OK;
}
}
+
+bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const {
+ // Only allow extensions we have a known bit position for in the
+ // __riscv_feature_bits structure.
+ return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitPosition(Feature);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index d5df6344bedc0..626274b8fc437 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -126,6 +126,10 @@ class RISCVTargetInfo : public TargetInfo {
std::pair hardwareInterferenceSizes() const override {
return std::make_pair(32, 32);
}
+
+ bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
+ bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
+ bool validateCpuSupports(StringRef Feature) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2ad62d6ee0bb2..71c947776adf2 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -62,6 +62,8 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include
#include
@@ -14215,6 +14217,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitRISCVCpuInit() {
+ llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
+ auto *CalleeGV = cast(Func.getCallee());
+ CalleeGV->setDSOLocal(true);
+ CalleeGV->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned ) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
preames wrote:
Please ignore my comment here about using weak symbols. After reflecting
further, I realized that having a link time dependence on the compiler support
library is entirely reasonable - so long as that dependence is only present if
the feature is actually used, as is done here.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/preames requested changes to this pull request. At a high level, I think this is a quite a ways from being ready to land. There's both code style issues (mostly false generality), and missing bits of the user interface on the clang side. I do not think this has any real serious chance of being ready to land in 19.x. My suggestion would be that we do one of two things. 1) Acknowledge this is not getting in to 19.x, and switch the the glibc based resolver approach for 20.x. 2) Drastically cut the scope of this. We won't get target_clones or target_variants, but we *could* possibly get builtin_cpu_supports. That has a much smaller user interface scope, and while we would need to add the syntax checking bits there, there's none of the ordering and intersection problems. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
+
+if (Options[Index].Conditions.Features[0].starts_with("default")) {
+ HasDefault = true;
+ DefaultIndex = Index;
+ continue;
+}
+
+Builder.SetInsertPoint(CurBlock);
+
+std::vector TargetAttrFeats =
+getContext()
+.getTargetInfo()
+.parseTargetAttr(Options[Index].Conditions.Features[0])
+.Features;
+
+if (TargetAttrFeats.empty())
+ continue;
+
+// Two conditions need to be checked for the current version:
preames wrote:
This check is both falsely generic and inefficient. We know that the maximum
group ID is going to be 1 for all possible checks. We should check this once
above the loop and be done with it. The optimizer will likely recognize the
redundant code, but why bother emitting it to start with?
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
preames wrote:
There's a semantic problem here unless I'm missing something. Say the user
specifies three choices: default, zba, and zba+zbb (in that order.) Unless I'm
missing something, the third case would be dead here which is almost certainly
not what the user intended. How do other targets handle this case?
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
+ raw_ostream ) const override;
+ void appendAttributeMangling(StringRef AttrStr,
+ raw_ostream ) const override;
};
} // end anonymous namespace
+void RISCVABIInfo::appendAttributeMangling(TargetClonesAttr *Attr,
+ unsigned Index,
+ raw_ostream ) const {
+ appendAttributeMangling(Attr->getFeatureStr(Index), Out);
+}
+
+void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
+ raw_ostream ) const {
+ if (AttrStr == "default") {
+Out << ".default";
+return;
+ }
+
+ Out << '.';
preames wrote:
Using an unnormalized arch string here appears unlikely to be what we want.
This is not what aarch64 does for instance. It also seems questionable to me
to have e.g. "+" in a mangled name.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
preames wrote:
See prior comment about weak symbols and soft dependencies. This might be a
good place for that guard.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
+
+if (Options[Index].Conditions.Features[0].starts_with("default")) {
+ HasDefault = true;
+ DefaultIndex = Index;
+ continue;
+}
+
+Builder.SetInsertPoint(CurBlock);
+
+std::vector TargetAttrFeats =
+getContext()
+.getTargetInfo()
+.parseTargetAttr(Options[Index].Conditions.Features[0])
+.Features;
+
+if (TargetAttrFeats.empty())
+ continue;
+
+// Two conditions need to be checked for the current version:
+//
+// 1. LengthCondition: The maximum group ID of the required extension
+//does not exceed the runtime object's length.
+//__riscv_feature_bits.length > MAX_USED_GROUPID
+//
+// 2. FeaturesCondition: The bitmask of the required extension has been
+//enabled by the runtime object.
+//(__riscv_feature_bits.features[i] & REQUIRED_BITMASK) ==
+//REQUIRED_BITMASK
+//
+// When both conditions are met, return this version of the function.
+// Otherwise, try the next version.
+//
+// if (LengthConditionVersion1 && FeaturesConditionVersion1)
+// return Version1;
+// else if (LengthConditionVersion2 && FeaturesConditionVersion2)
+// return Version2;
+// else if (LengthConditionVersion3 && FeaturesConditionVersion3)
+// return Version3;
+// ...
+// else
+// return DefaultVersion;
+llvm::SmallVector CurrTargetAttrFeats;
+
+for (auto Feat : TargetAttrFeats)
+ CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
preames wrote:
This is silently dropping the + or -. Do we have a syntax error somewhere
which rejects negative features? If not, this would seem to give very
surprising semantics.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned ) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
preames wrote:
This block of repeating code should be factored out as a static helper.
However, you appear to be missing a very important detail. This symbol must be
a weak symbol, and the client code must bail if the weak symbol resolves to
nullptr. Otherwise we have a *hard* dependency on the compiler-rt/libgcc
version as opposed to a soft dependency. We want this to simply select the
default implementation if the libgcc version does not support the new feature.
(I'm a bit unclear on the semantics of a weak global vs a weak function. We
may want to use a check on one of the symbols instead.)
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RISCVExtensionBitmaskTable
+
+namespace {
+struct LessExtName {
+ bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask ,
+ StringRef RHS) {
+return StringRef(LHS.Name) < RHS;
+ }
+ bool
+ operator()(StringRef LHS,
+ const RISCVExtensionBitmaskTable::RISCVExtensionBitmask ) {
+return LHS < StringRef(RHS.Name);
+ }
+};
+} // namespace
+
+static Expected
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef ExtBitmasks =
+ RISCVExtensionBitmaskTable::ExtensionBitmask;
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+return *I;
+
+ return createStringError("Unsupport extension");
+}
+
+llvm::SmallVector getRequireFeatureBitMask(ArrayRef Exts)
{
+ llvm::SmallVector BitMasks(RISCV::RISCVFeatureBitSize);
+
+ for (auto Ext : Exts) {
+Expected ExtBitmask =
+getExtensionBitmask(Ext);
+assert(ExtBitmask && "This extension doesn't has bitmask.");
preames wrote:
The user interface aspect of this should be handled in clang. It's entirely
possible a user tries to name a extension the compiler doesn't know about.
Say, a custom vendor extension. We should probably reject or warn on such
cases, but we definitely shouldn't crash somewhere deep inside of LLVM.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned ) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadFeatureBit = [&](unsigned Index) {
+// Create GEP then load.
+Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
+llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
+ IndexVal};
+Value *Ptr =
+Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+Value *FeaturesBit =
+Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+return FeaturesBit;
+ };
+
+ SmallVector RequireFeatureBits =
preames wrote:
The naming here is quite confusing. This structure is not a list of bits.
It's a single bitmask for which we do a single comparison. See other comments
about false generality.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned ) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadFeatureBit = [&](unsigned Index) {
+// Create GEP then load.
+Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
+llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
+ IndexVal};
+Value *Ptr =
+Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+Value *FeaturesBit =
+Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+return FeaturesBit;
+ };
+
+ SmallVector RequireFeatureBits =
+ llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
+ Value *Result = Builder.getTrue();
+ for (unsigned i = 0; i < RequireFeatureBits.size(); i++) {
+if (!RequireFeatureBits[i])
+ continue;
+MaxGroupIDUsed = i;
+Value *Mask = Builder.getInt64(RequireFeatureBits[i]);
+Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
+Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
+Result = Builder.CreateAnd(Result, Cmp);
+ }
+
+ return Result;
+}
+
+Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
preames wrote:
There's a bunch of false generality here. For a given version of the compiler,
we know the MaxGroupIDUsed statically. Currently, it's always 1. There's no
value in this falsely generic code.
https://github.com/llvm/llvm-project/pull/85786
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add capital letters to T-Head extension names in descriptions. (PR #99070)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/99070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: All of the dependent pieces have landed. For ease of future reference: * https://github.com/llvm/llvm-project/pull/90266 is the attributes emission (off by default). * https://github.com/llvm/llvm-project/pull/97347 is the LLD change. * https://github.com/llvm/llvm-project/pull/87376 is the change to A67 by default The combination of the first and third mean that the emitted attributes now match our ztso lowering as well. Unfortunately, most binaries wont have the attributes at all (due to the LD crash on older versions), but that seems unavoidable at this point. I have re-landed the original change. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 90d79e2 - Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
Author: Philip Reames Date: 2024-07-09T10:45:56-07:00 New Revision: 90d79e258ee9c6935ffeac405b3e9b74542068aa URL: https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa DIFF: https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa.diff LOG: Reapply "[RISCV] Remove experimental from Ztso. (#96465)" This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that, the default WMO lowering has moved to A67 compatible, the ABI attribute emission has landed (off by default), and the LLD change to merge said attributes have landed. Our ztso lowering is believed to also be A67 compatible, and no known issues remain. Original commit message: Ztso 1.0 was ratified in January 2023. Documentation: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll llvm/test/CodeGen/RISCV/atomic-fence.ll llvm/test/CodeGen/RISCV/atomic-load-store.ll llvm/test/CodeGen/RISCV/atomic-rmw.ll llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll llvm/test/CodeGen/RISCV/attributes.ll llvm/test/CodeGen/RISCV/module-elf-flags.ll llvm/test/MC/RISCV/Ztso.s llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/elf-flags.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 36ace1e007c32..49bdb21ac59d6 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -70,6 +70,7 @@ // CHECK-NEXT: zksed1.0 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions) // CHECK-NEXT: zksh 1.0 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions) // CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: ztso 1.0 'Ztso' (Memory Model - Total Store Order) // CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) // CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication) // CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) @@ -170,7 +171,6 @@ // CHECK-NEXT: zicfilp 0.4 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 0.4 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) -// CHECK-NEXT: ztso 0.1 'Ztso' (Memory Model - Total Store Order) // CHECK-NEXT: smmpm1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: ssnpm1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 0f285f7c0033c..018fa25218ea6 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -365,24 +365,30 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s // RV32-ZFHMIN: "-target-feature" "+zfhmin" -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s -// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso' +// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr' // RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s -// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso' +// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr' // RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \ +// RUN: not %clang --target=riscv32-unknown-elf
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
CPU = llvm::sys::getHostCPUName();
+ // If the target cpu is unrecognized, use target features.
+ if (CPU.empty() || CPU.starts_with("generic")) {
+llvm::StringMap HostFeatures;
+if (llvm::sys::getHostCPUFeatures(HostFeatures)) {
+ std::vector Features;
+ for (auto : HostFeatures)
+Features.push_back(
+Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
+ Triple.isRISCV32() ? 32 : 64, Features);
+ if (ParseResult)
+return (*ParseResult)->toString();
preames wrote:
Good catch. Returning std::string for now appears to be the path of least
resistance.
Glancing at the callers, I note that more than half immediately call
parseArchString. We could invert the API here, and return the parsed ISAInfo,
and then convert that back into string form on demand. I didn't see any cases
where we wanted the string form of an invalid architecture combination - that
would be the case which might prevent the API inversion.
https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
https://github.com/preames approved this pull request. LGTM w/minor comments https://github.com/llvm/llvm-project/pull/94352 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver , const
llvm::Triple ,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "native") {
CPU = llvm::sys::getHostCPUName();
+ llvm::StringMap HostFeatures;
+ if (llvm::sys::getHostCPUFeatures(HostFeatures))
+for (auto : HostFeatures)
+ Features.push_back(
+ Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+}
preames wrote:
Do we also need to update riscv::getRISCVArch? There's analogous logic there
for getting features from mcpu native.
https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
+/*pair_count=*/std::size(Query), /*cpu_count=*/0,
+/*cpus=*/0, /*flags=*/0);
+ if (Ret != 0)
+return false;
+
+ uint64_t BaseMask = Query[0].Value;
+ // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
+ if (BaseMask & 1) {
+Features["i"] = true;
+Features["m"] = true;
+Features["a"] = true;
+ }
+
+ uint64_t ExtMask = Query[1].Value;
+ Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
+ Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
+ Features["c"] = ExtMask & (1 << 1); // RISCV_HWPROBE_IMA_C
+ Features["v"] = ExtMask & (1 << 2); // RISCV_HWPROBE_IMA_V
+ Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA
+ Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB
+ Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS
+ Features["zicboz"] = ExtMask & (1 << 6); // RISCV_HWPROBE_EXT_ZICBOZ
+ Features["zbc"] = ExtMask & (1 << 7); // RISCV_HWPROBE_EXT_ZBC
+ Features["zbkb"] = ExtMask & (1 << 8);// RISCV_HWPROBE_EXT_ZBKB
+ Features["zbkc"] = ExtMask & (1 << 9);// RISCV_HWPROBE_EXT_ZBKC
+ Features["zbkx"] = ExtMask & (1 << 10); // RISCV_HWPROBE_EXT_ZBKX
+ Features["zknd"] = ExtMask & (1 << 11); // RISCV_HWPROBE_EXT_ZKND
+ Features["zkne"] = ExtMask & (1 << 12); // RISCV_HWPROBE_EXT_ZKNE
+ Features["zknh"] = ExtMask & (1 << 13); // RISCV_HWPROBE_EXT_ZKNH
+ Features["zksed"] = ExtMask & (1 << 14); // RISCV_HWPROBE_EXT_ZKSED
+ Features["zksh"] = ExtMask & (1 << 15); // RISCV_HWPROBE_EXT_ZKSH
+ Features["zkt"] = ExtMask & (1 << 16);// RISCV_HWPROBE_EXT_ZKT
+ Features["zvbb"] = ExtMask & (1 << 17); // RISCV_HWPROBE_EXT_ZVBB
+ Features["zvbc"] = ExtMask & (1 << 18); // RISCV_HWPROBE_EXT_ZVBC
+ Features["zvkb"] = ExtMask & (1 << 19); // RISCV_HWPROBE_EXT_ZVKB
+ Features["zvkg"] = ExtMask & (1 << 20); // RISCV_HWPROBE_EXT_ZVKG
+ Features["zvkned"] = ExtMask & (1 << 21); // RISCV_HWPROBE_EXT_ZVKNED
+ Features["zvknha"] = ExtMask & (1 << 22); // RISCV_HWPROBE_EXT_ZVKNHA
+ Features["zvknhb"] = ExtMask & (1 << 23); // RISCV_HWPROBE_EXT_ZVKNHB
+ Features["zvksed"] = ExtMask & (1 << 24); // RISCV_HWPROBE_EXT_ZVKSED
+ Features["zvksh"] = ExtMask & (1 << 25); // RISCV_HWPROBE_EXT_ZVKSH
+ Features["zvkt"] = ExtMask & (1 << 26); // RISCV_HWPROBE_EXT_ZVKT
+ Features["zfh"] = ExtMask & (1 << 27);// RISCV_HWPROBE_EXT_ZFH
+ Features["zfhmin"] = ExtMask & (1 << 28); // RISCV_HWPROBE_EXT_ZFHMIN
+ Features["zihintntl"] = ExtMask & (1 << 29); // RISCV_HWPROBE_EXT_ZIHINTNTL
+ Features["zvfh"] = ExtMask & (1 << 30); // RISCV_HWPROBE_EXT_ZVFH
+ Features["zvfhmin"] = ExtMask & (1ULL << 31); // RISCV_HWPROBE_EXT_ZVFHMIN
+ Features["zfa"] = ExtMask & (1ULL << 32); // RISCV_HWPROBE_EXT_ZFA
+ // TODO: set ztso when it is no longer experimental.
+ // Features["ztso"] = ExtMask & (1ULL << 33);// RISCV_HWPROBE_EXT_ZTSO
preames wrote:
I agree that leaving this as a TODO is the right thing to do right now.
https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
preames wrote:
Consider this a purely stylistic comment.
We should probably be using either the vDSO symbol or the glibc shim. In
either case, we'd have a weak symbol which could possibly be nullptr, and need
to return early.
In this use case, the difference likely doesn't matter, but if we reuse this
code, the lack of caching provided by vDSO could be problematic.
https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap ) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap ) {
+ RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+ {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+ int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
+/*pair_count=*/std::size(Query), /*cpu_count=*/0,
+/*cpus=*/0, /*flags=*/0);
+ if (Ret != 0)
+return false;
+
+ uint64_t BaseMask = Query[0].Value;
+ // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
+ if (BaseMask & 1) {
+Features["i"] = true;
+Features["m"] = true;
+Features["a"] = true;
+ }
+
+ uint64_t ExtMask = Query[1].Value;
preames wrote:
I think this is likely to be fine in practice.
>From https://docs.kernel.org/arch/riscv/hwprobe.html, I see "If a key is
>unknown to the kernel, its key field will be cleared to -1, and its value set
>to 0. " If I'm reading that properly, if RISCV_HWPROBE_KEY_IMA_EXT_0 isn't a
>valid key, it is the kernel's responsible for clearing all bits to zero, so
>this code should work.
https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94352 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: Once https://github.com/llvm/llvm-project/pull/90266 lands with the attributes off by default, I think we should move forward with relanding this. We do need one change though - our TSO lowering unconditionally uses the A6S ABI variant - right? - so we need to adjust the attribute emission to generate A6S when compiling for TSO. This is pretty minor honestly, but we should do it. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote:
Chatted with @patrick-rivos on the status of TSO. The following is my summary:
* psABI changes have landed which change the default for WMO to what we used to
call the "A6/A7 compatibility table". The TSO change which landed to psABI
defines a mapping which is compatible with this table, but also cross
compatible with WMO A6 and WMO A7 independently.
* Patrick's change (https://reviews.llvm.org/D155517) changed LLVM to emitting
code which is believed to match the psABI for TSO. Note that this was done
before the psABI changes were accepted.
* Our WMO lowering is still the A6 variant. We have not moved to the A6/A7
compat mapping which is now mandated by psABI. (We probably should, just to
match gcc.)
* The psABI change included two set of ELF flags for managing TSO and the A6/A7
compat question. I know I implemented the former, but neither of us knew the
status of the compat flags.
* As a reminder, gcc originally implemented a buggy variant of the A6 table for
WMO. The first correct version was gcc 13 which went straight to the new psABI
mapping ("A6/A7 compat"). None of the available options give us cross
compatibility with binaries compiled with an old gcc.
Takeaway here is that we probably are fine to move ztso out of experimental
once someone reports back on the status of the elf flags for the a6/a7 compat
thing.
https://github.com/llvm/llvm-project/pull/96465
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] f985a88 - Revert "[RISCV] Remove experimental from Ztso. (#96465)"
Author: Philip Reames
Date: 2024-06-24T08:32:28-07:00
New Revision: f985a8826bfa4ca3d23e654185de35e30ea6dc79
URL:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79
DIFF:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79.diff
LOG: Revert "[RISCV] Remove experimental from Ztso. (#96465)"
This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See
discussion on review thread.
Added:
Modified:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/GlobalISel/atomic-fence.ll
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-fence.ll
llvm/test/CodeGen/RISCV/atomic-load-store.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/module-elf-flags.ll
llvm/test/MC/RISCV/Ztso.s
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/elf-flags.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c3c471c4bc396..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -365,30 +365,24 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG
%s
-// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS
%s
-// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izalasr'
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version
number
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7
-menable-experimental-extensions -### %s \
+// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS
%s
-// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental
extension 'zalasr' (this compiler supports 0.1)
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental
extension 'ztso' (this compiler supports 0.1)
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1
-menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
-// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso1p0 -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZTSO %s
-// RV32-ZTSO: "-target-feature" "+ztso"
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 46a61e3c0afc7..d7935af532dfa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1650,13 +1650,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
-// RUN: %clang --target=riscv32-unknown-linux-gnu \
-// RUN: -march=rv32iztso1p0 -E -dM %s \
+// RUN: %clang --target=riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32iztso0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu \
-//
[clang] [llvm] [RISCV] Remove experimental from Ztso. (PR #96465)
preames wrote: > I think @preames told me he was keeping this experimental for a reason. Yes, revert pending. The concern here is that there are multiple possible ABIs here, and at the point I implemented this, the ABI chosen in my initial set of patches was compatible with the then current WMO ABI, but is *incompatible* with the revised ABI for load acquire/store release. I know there has been some work on this since, but the prominent warning comment has not been removed, and there is not discussion in this review about status. I will note that simply deleting a comment from the docs *which directly explain why something is still experimental* without discussing exactly that issue in the review thread is, IMO, poor behavior on all parties involved. https://github.com/llvm/llvm-project/pull/96465 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)
preames wrote: Given the concern about breaking configurations w/no-integrated-as and older binutils, can someone summarize here which versions of binutils are known to work/not work after this change? This will likely become the key search result for such breakage, and having it well documented for users seems critical. https://github.com/llvm/llvm-project/pull/95070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", FeatureStdExtC], [TuneNoDefaultUnroll]>; +def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", + SyntacoreSCR3RV32Model, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtC], + [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; + +def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", preames wrote: This part should really be a standalone change. Please separate the addition of the new processor as it's own PR. https://github.com/llvm/llvm-project/pull/95427 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
preames wrote: > Will this core have active support on the LLVM side? I can't speak for the vendor, but I'll say that I'm interested in having this supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and having in tree support seems worthwhile. I've ordered one of these myself, and plan on using it for ongoing RISC-V vector development. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, preames wrote: > The supported extensions are listed in 2.1.2 of this > [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), > including zicond. I @sunshaoce We should adjust the patch description to reference this document. If you have anything you think is supported which is not on the documented list, please highlight it so that @zqb-all can clarify docs. @zqb-all Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, +FeatureStdExtZmmul, +FeatureStdExtZvfh, +FeatureStdExtZvfhmin, +FeatureStdExtZvl32b, +FeatureStdExtZvl64b, +FeatureStdExtZvl128b, +FeatureStdExtZvl256b])>; preames wrote: Zvl256 implies Zvl32 through Zvl128, so those don't need to be explicitly repeated. Per the docs, the actual execution width is 128 bit so we could add [TuneDLenFactor2] to the tuning list. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, preames wrote: Looking at e.g. zicond, I don't see anything in the docs which claim support for this extension. ruapu appears to work via running an instruction and checking for faults - this could be a dangerous thing to rely on if the CPU e.g. incorrectly implements some extension, or doesn't implement the reserved opcodes the way the tool expects. I suggest that we cut down this list to include *only* those things which are specified. We can expand that list later based on changes to documentation and/or communication with vendor. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/preames requested changes to this pull request. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [IR] Avoid creating icmp/fcmp constant expressions (PR #92885)
@@ -8,7 +8,8 @@ // CHECK: entry: // CHECK-NEXT: %retval = alloca i32 // CHECK-NEXT: store i32 0, ptr %retval -// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32 +// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a +// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 preames wrote: Oh, ignore me. I didn't realize this was specific testing unsimplified IR. https://github.com/llvm/llvm-project/pull/92885 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [IR] Avoid creating icmp/fcmp constant expressions (PR #92885)
@@ -8,7 +8,8 @@ // CHECK: entry: // CHECK-NEXT: %retval = alloca i32 // CHECK-NEXT: store i32 0, ptr %retval -// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32 +// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a +// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 preames wrote: This looks to be a missing constant fold somewhere. The compare should be folded to true, not a constantexpr. https://github.com/llvm/llvm-project/pull/92885 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Don't enable -mrelax-all for -O0 on RISC-V (PR #88538)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88538 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #88954)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88954 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
preames wrote:
Please rename NewArch to ArchStorage. Specifically, we end up with a StringRef
bound to this storage, and having it go out of scope before that StringRef
would be a use-after-free.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
preames wrote:
This may not be fully evaluated at compile time. I'd go back to the static
arrays personally.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+{"rva20s64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+{"rva22u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+{"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_"
+ "ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+{"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+{"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_"
+ "shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+{"rvb23u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+{"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
preames wrote:
The formatting on this is very odd - please file each line to 76 characters for
the long sequences of extensions.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+// A mapping from profile name to march string with all mandatory
+// extensions.
+static const std::map SupportedProfiles = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+{"rva20s64",
+ "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+{"rva22u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+{"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_"
+ "ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+{"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+{"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_"
+ "shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+{"rvb23u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+{"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_"
+ "ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_"
+ "zawrs_"
+ "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_"
+ "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
+{"rvm23u32",
+ "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_"
+ "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"},
+};
+
+auto FoundProfile = llvm::find_if(
+SupportedProfiles,
+[Arch](const std::pair ) {
+ return Arch.starts_with(Profile.first);
+});
+
+if (FoundProfile == SupportedProfiles.end())
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->second;
+StringRef ArchWithoutProfile = Arch.substr(FoundProfile->first.size());
+if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+return createStringError(
+errc::invalid_argument,
+"additional extensions must be after separator '_'");
+ NewArch += ArchWithoutProfile.str();
+}
+Arch = NewArch;
preames wrote:
One idea to simplify this code - build the std::string NewArch, and then make a
recursive call to this routine and return the result. This would avoid all the
lifetime issues involved with the fallthrough.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
preames wrote:
You don't need this variable, please sink it into the if-clause below.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
https://github.com/preames commented: After this was discussed at the sync-up call today, I believe we're in agreement on direction here. This is close to being ready and is just pending some code cleanup. https://github.com/llvm/llvm-project/pull/76357 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
preames wrote:
Very minor, but I believe you can use std::pair here instead.
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 13ccaf9 - Revert "Reapply "[analyzer] Accept C library functions from the `std` namespace""
Author: Philip Reames
Date: 2024-03-13T10:19:42-07:00
New Revision: 13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
URL:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c
DIFF:
https://github.com/llvm/llvm-project/commit/13ccaf9b9d4400bb128b35ff4ac733e4afc3ad1c.diff
LOG: Revert "Reapply "[analyzer] Accept C library functions from the `std`
namespace""
This reverts commit e48d5a838f69e0a8e0ae95a8aed1a8809f45465a.
Fails to build on x86-64 w/gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)
with the following message:
../llvm-project/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp:41:28:
error: declaration of ‘std::unique_ptr
IsCLibraryFunctionTest::ASTUnit’ changes meaning of ‘ASTUnit’ [-fpermissive]
41 | std::unique_ptr ASTUnit;
|^~~
In file included from
../llvm-project/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp:4:
../llvm-project/clang/include/clang/Frontend/ASTUnit.h:89:7: note: ‘ASTUnit’
declared here as ‘class clang::ASTUnit’
89 | class ASTUnit {
| ^~~
Added:
Modified:
clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
clang/unittests/StaticAnalyzer/CMakeLists.txt
llvm/utils/gn/secondary/clang/unittests/StaticAnalyzer/BUILD.gn
Removed:
clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
diff --git
a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
index b4e1636130ca7c..3432d2648633c2 100644
--- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
+++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
@@ -41,8 +41,12 @@ class CallDescription {
/// - We also accept calls where the number of arguments or parameters is
///greater than the specified value.
/// For the exact heuristics, see CheckerContext::isCLibraryFunction().
-/// (This mode only matches functions that are declared either directly
-/// within a TU or in the namespace `std`.)
+/// Note that functions whose declaration context is not a TU (e.g.
+/// methods, functions in namespaces) are not accepted as C library
+/// functions.
+/// FIXME: If I understand it correctly, this discards calls where C++ code
+/// refers a C library function through the namespace `std::` via headers
+/// like .
CLibrary,
/// Matches "simple" functions that are not methods. (Static methods are
diff --git a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
index 1a9bff529e9bb1..d6d4cec9dd3d4d 100644
--- a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
+++ b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
@@ -87,11 +87,9 @@ bool CheckerContext::isCLibraryFunction(const FunctionDecl
*FD,
if (!II)
return false;
- // C library functions are either declared directly within a TU (the common
- // case) or they are accessed through the namespace `std` (when they are used
- // in C++ via headers like ).
- const DeclContext *DC = FD->getDeclContext()->getRedeclContext();
- if (!(DC->isTranslationUnit() || DC->isStdNamespace()))
+ // Look through 'extern "C"' and anything similar invented in the future.
+ // If this function is not in TU directly, it is not a C library function.
+ if (!FD->getDeclContext()->getRedeclContext()->isTranslationUnit())
return false;
// If this function is not externally visible, it is not a C library
function.
diff --git a/clang/unittests/StaticAnalyzer/CMakeLists.txt
b/clang/unittests/StaticAnalyzer/CMakeLists.txt
index db56e77331b821..775f0f8486b8f9 100644
--- a/clang/unittests/StaticAnalyzer/CMakeLists.txt
+++ b/clang/unittests/StaticAnalyzer/CMakeLists.txt
@@ -11,7 +11,6 @@ add_clang_unittest(StaticAnalysisTests
CallEventTest.cpp
ConflictingEvalCallsTest.cpp
FalsePositiveRefutationBRVisitorTest.cpp
- IsCLibraryFunctionTest.cpp
NoStateChangeFuncVisitorTest.cpp
ParamRegionTest.cpp
RangeSetTest.cpp
diff --git a/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
b/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
deleted file mode 100644
index 31ff13f428da36..00
--- a/clang/unittests/StaticAnalyzer/IsCLibraryFunctionTest.cpp
+++ /dev/null
@@ -1,84 +0,0 @@
-#include "clang/ASTMatchers/ASTMatchFinder.h"
-#include "clang/ASTMatchers/ASTMatchers.h"
-#include "clang/Analysis/AnalysisDeclContext.h"
-#include "clang/Frontend/ASTUnit.h"
-#include "clang/StaticAnalyzer/Core/PathSensitive/CheckerContext.h"
-#include "clang/Tooling/Tooling.h"
-#include "gtest/gtest.h"
-
-#include
-
-using namespace clang;
-using namespace ento;
-using namespace ast_matchers;
-
-class IsCLibraryFunctionTest : public
[clang] [RISCV] Add canonical ISA string as Module metadata in IR. (PR #80760)
preames wrote: I agree with @asb's framing above. Assuming this doesn't commit us to something which is hard to forward version for some reason, I support addressing this in a target specific manner for the moment. https://github.com/llvm/llvm-project/pull/80760 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)
@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef
VL) {
return CommonAlignment;
}
+/// Check if \p Order represents reverse order.
+static bool isReverseOrder(ArrayRef Order) {
+ unsigned Sz = Order.size();
+ return !Order.empty() && all_of(enumerate(Order), [&](const auto ) {
+return Pair.value() == Sz || Sz - Pair.index() - 1 == Pair.value();
+ });
+}
+
+/// Checks if the provided list of pointers \p Pointers represents the strided
+/// pointers for type ElemTy. If they are not, std::nullopt is returned.
+/// Otherwise, if \p Inst is not specified, just initialized optional value is
+/// returned to show that the pointers represent strided pointers. If \p Inst
+/// specified, the runtime stride is materialized before the given \p Inst.
+/// \returns std::nullopt if the pointers are not pointers with the runtime
+/// stride, nullptr or actual stride value, otherwise.
+static std::optional
+calculateRtStride(ArrayRef PointerOps, Type *ElemTy,
+ const DataLayout , ScalarEvolution ,
+ SmallVectorImpl ,
+ Instruction *Inst = nullptr) {
+ SmallVector SCEVs;
preames wrote:
An alternate approach which might be simpler and yet cover many of the
interesting test cases might be:
* Loop over the pointers, check that getPointerBase matches.
* Loop again doing removePointerBase
* This gives a list of offsets from base, bail if any non-constant
* Sort the list of constant offsets
* Check if strided w/shuffle?
If you don't want a shuffle afterwards, you can check the delta without sorting.
This won't cover non-constant strides, but I'm not sure we really care about
those in practice.
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[openmp] [clang-tools-extra] [libcxx] [lld] [flang] [clang] [llvm] [lldb] [mlir] [libc] [SLP]Add support for strided loads. (PR #80310)
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.size() - 1)
+ if (static_cast(*Diff) == Sz - 1)
return LoadsState::Vectorize;
// Simple check if not a strided access - clear order.
- IsPossibleStrided = *Diff % (VL.size() - 1) == 0;
+ bool IsPossibleStrided = *Diff % (Sz - 1) == 0;
+ // Try to generate strided load node if:
+ // 1. Target with strided load support is detected.
+ // 2. The number of loads is greater than MinProfitableStridedLoads,
+ // or the potential stride <= MaxProfitableLoadStride and the
+ // potential stride is power-of-2 (to avoid perf regressions for the very
+ // small number of loads) and max distance > number of loads, or
potential
+ // stride is -1.
+ // 3. The loads are ordered, or number of unordered loads <=
+ // MaxProfitableUnorderedLoads, or loads are in reversed order.
+ // (this check is to avoid extra costs for very expensive shuffles).
+ if (IsPossibleStrided && (((Sz > MinProfitableStridedLoads ||
+ (static_cast(std::abs(*Diff)) <=
+ MaxProfitableLoadStride * Sz &&
+ isPowerOf2_32(std::abs(*Diff &&
+ static_cast(std::abs(*Diff)) > Sz)
||
+*Diff == -(static_cast(Sz) - 1))) {
+int Stride = *Diff / static_cast(Sz - 1);
preames wrote:
How is the diff-in-bytes divided by the number of elements the stride? Did you
maybe mean to use element size here?
It's also possible you have two Sz variables with different meaning. I did not
check for this.
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [flang] [mlir] [openmp] [llvm] [clang] [clang-tools-extra] [lldb] [lld] [libc] [SLP]Add support for strided loads. (PR #80310)
https://github.com/preames commented: These comments are trying to be helpful in pointing out bits which might be simplified or split off, but my track record with SLP reviews is not great. Feel free to ignore any or all of these. https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [libcxx] [lldb] [lld] [mlir] [clang-tools-extra] [libc] [openmp] [llvm] [clang] [SLP]Add support for strided loads. (PR #80310)
@@ -30,7 +30,7 @@ define void @test() {
; CHECK-SLP-THRESHOLD: bb:
; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison,
ptr [[COND_IN_V]], i32 0
; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr>
[[TMP0]], <4 x ptr> poison, <4 x i32> zeroinitializer
-; CHECK-SLP-THRESHOLD-NEXT:[[TMP2:%.*]] = getelementptr i64, <4 x ptr>
[[TMP1]], <4 x i64>
+; CHECK-SLP-THRESHOLD-NEXT:[[TMP2:%.*]] = getelementptr i64, <4 x ptr>
[[TMP1]], <4 x i64>
preames wrote:
Shouldn't this be a strided load with a stride of -4*8?
If what you're aiming for is test stability, can you use a index which doesn't
look anything like a strided load?
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libc] [lld] [llvm] [lldb] [libcxx] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)
@@ -17,7 +17,7 @@ define i16 @test() {
; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16>
@llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison)
; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0
; CHECK-NEXT:[[TMP6:%.*]] = extractelement <2 x i16> [[TMP4]], i32 1
-; CHECK-NEXT:[[CMP_I178:%.*]] = icmp ult i16 [[TMP6]], [[TMP5]]
+; CHECK-NEXT:[[CMP_I178:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]]
; CHECK-NEXT:br label [[WHILE_BODY_I]]
;
entry:
preames wrote:
Unless this is specifically testing something about offsets from null, can you
update this test to pass in a pointer argument and index off that?
(Separate change, no review needed.)
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [libc] [mlir] [libcxx] [lldb] [lld] [clang] [openmp] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)
@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr
[[P:%.*]], i64 0, i64 0
; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr
[[S:%.*]], i64 0
-; CHECK-NEXT:[[ARRAYIDX4:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 4
-; CHECK-NEXT:[[ARRAYIDX11:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 8
-; CHECK-NEXT:[[ARRAYIDX18:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 12
-; CHECK-NEXT:[[ARRAYIDX25:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 16
-; CHECK-NEXT:[[ARRAYIDX32:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 20
-; CHECK-NEXT:[[ARRAYIDX39:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 24
-; CHECK-NEXT:[[ARRAYIDX46:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 28
; CHECK-NEXT:[[ARRAYIDX48:%.*]] = getelementptr inbounds [48 x float], ptr
[[P]], i64 0, i64 23
-; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr
[[ARRAYIDX]], i32 0
-; CHECK-NEXT:[[TMP1:%.*]] = insertelement <8 x ptr> [[TMP0]], ptr
[[ARRAYIDX4]], i32 1
-; CHECK-NEXT:[[TMP2:%.*]] = insertelement <8 x ptr> [[TMP1]], ptr
[[ARRAYIDX11]], i32 2
-; CHECK-NEXT:[[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr
[[ARRAYIDX18]], i32 3
-; CHECK-NEXT:[[TMP4:%.*]] = insertelement <8 x ptr> [[TMP3]], ptr
[[ARRAYIDX25]], i32 4
-; CHECK-NEXT:[[TMP5:%.*]] = insertelement <8 x ptr> [[TMP4]], ptr
[[ARRAYIDX32]], i32 5
-; CHECK-NEXT:[[TMP6:%.*]] = insertelement <8 x ptr> [[TMP5]], ptr
[[ARRAYIDX39]], i32 6
-; CHECK-NEXT:[[TMP7:%.*]] = insertelement <8 x ptr> [[TMP6]], ptr
[[ARRAYIDX46]], i32 7
-; CHECK-NEXT:[[TMP8:%.*]] = call <8 x float>
@llvm.masked.gather.v8f32.v8p0(<8 x ptr> [[TMP7]], i32 4, <8 x i1> , <8 x float> poison)
-; CHECK-NEXT:[[TMP9:%.*]] = load <8 x float>, ptr [[ARRAYIDX48]], align 4
-; CHECK-NEXT:[[TMP10:%.*]] = shufflevector <8 x float> [[TMP9]], <8 x
float> poison, <8 x i32>
-; CHECK-NEXT:[[TMP11:%.*]] = fsub fast <8 x float> [[TMP10]], [[TMP8]]
-; CHECK-NEXT:store <8 x float> [[TMP11]], ptr [[ARRAYIDX2]], align 4
+; CHECK-NEXT:[[TMP0:%.*]] = call <8 x float>
@llvm.experimental.vp.strided.load.v8f32.p0.i64(ptr align 4 [[ARRAYIDX]], i64
16, <8 x i1> , i32 8)
+; CHECK-NEXT:[[TMP1:%.*]] = load <8 x float>, ptr [[ARRAYIDX48]], align 4
+; CHECK-NEXT:[[TMP2:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x
float> poison, <8 x i32>
preames wrote:
Can't this reverse become a negative strided load?
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [openmp] [mlir] [libc] [lldb] [lld] [clang-tools-extra] [llvm] [libcxx] [SLP]Add support for strided loads. (PR #80310)
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef
VL, const Value *VL0,
std::optional Diff =
getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE);
// Check that the sorted loads are consecutive.
- if (static_cast(*Diff) == VL.size() - 1)
+ if (static_cast(*Diff) == Sz - 1)
return LoadsState::Vectorize;
// Simple check if not a strided access - clear order.
- IsPossibleStrided = *Diff % (VL.size() - 1) == 0;
+ bool IsPossibleStrided = *Diff % (Sz - 1) == 0;
+ // Try to generate strided load node if:
+ // 1. Target with strided load support is detected.
+ // 2. The number of loads is greater than MinProfitableStridedLoads,
+ // or the potential stride <= MaxProfitableLoadStride and the
+ // potential stride is power-of-2 (to avoid perf regressions for the very
+ // small number of loads) and max distance > number of loads, or
potential
+ // stride is -1.
+ // 3. The loads are ordered, or number of unordered loads <=
+ // MaxProfitableUnorderedLoads, or loads are in reversed order.
+ // (this check is to avoid extra costs for very expensive shuffles).
+ if (IsPossibleStrided && (((Sz > MinProfitableStridedLoads ||
+ (static_cast(std::abs(*Diff)) <=
+ MaxProfitableLoadStride * Sz &&
+ isPowerOf2_32(std::abs(*Diff &&
+ static_cast(std::abs(*Diff)) > Sz)
||
+*Diff == -(static_cast(Sz) - 1))) {
+int Stride = *Diff / static_cast(Sz - 1);
+if (*Diff == Stride * static_cast(Sz - 1)) {
+ if (TTI.isTypeLegal(VecTy) &&
preames wrote:
The isTypeLegal check here should be redundant.
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[mlir] [clang] [libc] [lldb] [lld] [openmp] [flang] [libcxx] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)
@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) {
; CHECK-NEXT: entry:
; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr
[[ADDR:%.*]], i32 0
; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr>
poison, <8 x i32> zeroinitializer
-; CHECK-NEXT:[[TMP2:%.*]] = getelementptr i32, <8 x ptr> [[TMP1]], <8 x
i32>
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr i32, <8 x ptr> [[TMP1]], <8 x
i32>
preames wrote:
Same as last.
https://github.com/llvm/llvm-project/pull/80310
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)
preames wrote: FYI - https://github.com/llvm/llvm-project/pull/80360 adds testing infrastructure to exercise the TTI hooks. https://github.com/llvm/llvm-project/pull/80310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [llvm] [clang-tools-extra] [lld] [clang] [libc] [libcxx] [lldb] [flang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ Index % NumElems == 0)) {
+ std::pair SubLT =
+ getTypeLegalizationCost(SubTp);
+ return Index == 0
+ ? TTI::TCC_Free
+ : SubLT.first * getRISCVInstructionCost(RISCV::VMV_V_V,
+ SubLT.second,
+ CostKind);
+}
+ }
+ break;
+case TTI::SK_InsertSubvector:
+ if (auto *FSubTy = dyn_cast(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
preames wrote:
Same basic style comments as above.
https://github.com/llvm/llvm-project/pull/80164
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [libcxx] [compiler-rt] [lldb] [llvm] [flang] [lld] [libc] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
preames wrote:
I think this check would be more clearly expressed as an and of the following
clauses
a) ST->getRealMaxVLen() == ST->getRealMinVLen()
b) NumElems * ElementSizeInBits == VLEN
c) Index % NumElems == 0
Note that this only supports m1 full extracts. But starting there and
extending it to m2, and m4 later seems entirely reasonable.
https://github.com/llvm/llvm-project/pull/80164
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[lldb] [compiler-rt] [clang-tools-extra] [llvm] [flang] [clang] [libcxx] [libc] [lld] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,50 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp)) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ Index % NumElems == 0)) {
+ std::pair SubLT =
+ getTypeLegalizationCost(SubTp);
+ return Index == 0
+ ? TTI::TCC_Free
+ : SubLT.first * getRISCVInstructionCost(RISCV::VMV_V_V,
preames wrote:
For a full VREG case, you never need the VMV_V_V. You only need the VMV_V_V if
NumElems < VLMAX.
Extending this to sub-register extract with exact VLEN known would be
reasonable, but let's do that in a separate patch.
https://github.com/llvm/llvm-project/pull/80164
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: I honestly neither understand this, nor particular care. I'm okay with any reasonable wording you want to use here - up to and including the previous identical wording for the two with the minor typo fix. If we find better wording later, we can just update it then. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
preames wrote: > It has been approved to be pursued as a fast track extension > (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698). > It has not yet been approved by the chairs. Works for me. I've edited the PR description to include this information so that it ends up in the submit message. I'm about to land this change on @mehnadnerd behalf since he doesn't have commit access. This was requested out of band. https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: The difference between the two appears to be which counter must be writeable. So maybe something like, "hcounter bits writeable for all non-zero hpmcounter bits" vs "scounter bits writeable for all non-zero hpmcounter bits"? This is the case where having an actual spec for this would be really useful. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; preames wrote: This description looks wrong. Document says "Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable." Maybe: "Support writeable enables for any supproted counter (with exception of zero registers)" Also, typo: "supproted" should be "supported" https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
https://github.com/preames approved this pull request. LGTM w/comments addressed. https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
preames wrote: I think we need some kind of official documentation to merge this. I went looking to see if I could find mention of this extension in e.g. ARC notes, and didn't find it. @mehnadnerd can you provide some kind of link or reference to some RVI source indicating the status of this proposal? It doesn't need to be near ratified, I'm just worried about the precedent we'd set by accepting an experimental extension with the only reference being an individual person's github. https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/79911
>From 3344e42d05875269b680b9626cd6cd093e88d81e Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/2] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
.../test/Preprocessor/riscv-target-features.c | 9 +++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td | 65
llvm/test/CodeGen/RISCV/attributes.ll | 4 +
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zalasr-invalid.s | 40 ++
llvm/test/MC/RISCV/rv32zalasr-valid.s | 78 +++
llvm/test/MC/RISCV/rv64zalasr-invalid.s | 28 +++
llvm/test/MC/RISCV/rv64zalasr-valid.s | 31
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
13 files changed, 271 insertions(+)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
create mode 100644 llvm/test/MC/RISCV/rv32zalasr-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalasr-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalasr-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalasr-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2361c83a5a610..35d112bcd070f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -144,6 +144,7 @@
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1333,6 +1334,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5caf2fee197f2..a957a8dfba95b 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -232,6 +232,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification
`_.
+``experimental-zalasr``
+ LLVM implements the `0.0.5 draft specification
`_.
+
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `1.0.0-rc2 specification
`_.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 0ae1fc01e4ffc..8f31b0f40d5c9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -197,6 +197,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zaamo", {0, 2}},
{"zabha", {1, 0}},
{"zacas", {1, 0}},
+{"zalasr", {0, 1}},
{"zalrsc", {0, 2}},
{"zcmop", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6b7bf4886c263..6f87eae101f04 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -192,6 +192,13 @@ def HasStdExtZacas :
Predicate<"Subtarget->hasStdExtZacas()">,
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
+def FeatureStdExtZalasr
+: SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
+ "'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
+def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZalasr),
+ "'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
+
def FeatureStdExtZalrsc
: SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true",
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)
https://github.com/preames approved this pull request. LGTM as well. https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
preames wrote: Not actively working on this. Anyone interested is welcome to pick up the patch. https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [driver] Respect the mode the driver is in for autocomplete (PR #74770)
https://github.com/preames closed https://github.com/llvm/llvm-project/pull/74770 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][doc] Add blank line before lists (PR #77573)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77573 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
@@ -96,6 +96,8 @@ on support follow. ``Svnapot`` Assembly Support ``Svpbmt`` Supported ``V``Supported + ``Za128rs`` Supported preames wrote: I think these may warrant an explanatory note after the table. See what we do for e.g. zicntr. Something which says these are defined by the profile specification seems like a useful breadcrumb. https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [Flang] Support -mrvv-vector-bits flag (PR #77588)
https://github.com/preames approved this pull request. LGTM We should explore options for merging the option processing code for options supported by both clang and flang, but that's explicitly future work. https://github.com/llvm/llvm-project/pull/77588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 0b7dda3 - Revert "[flang][nfc] Refactor linker invocation logic (#75534)"
Author: Philip Reames
Date: 2023-12-15T11:08:09-08:00
New Revision: 0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896
URL:
https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896
DIFF:
https://github.com/llvm/llvm-project/commit/0b7dda3d4cbe6a4180fd80f91e9f29e474c1d896.diff
LOG: Revert "[flang][nfc] Refactor linker invocation logic (#75534)"
This reverts commit 71bbfabd08d90a3007f6034e420daa66c41027db. Breaks
check-flang on x86_64 host.
Added:
Modified:
clang/lib/Driver/ToolChains/CommonArgs.cpp
flang/test/Driver/linker-flags.f90
Removed:
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 6de41642a734a7..3d1df58190ce05 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1116,87 +1116,73 @@ bool tools::addOpenMPRuntime(ArgStringList ,
const ToolChain ,
return true;
}
-/// Determines if --whole-archive is active in the list of arguments.
-static bool isWholeArchivePresent(const ArgList ) {
- bool WholeArchiveActive = false;
- for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA)) {
-if (Arg) {
- for (StringRef ArgValue : Arg->getValues()) {
-if (ArgValue == "--whole-archive")
- WholeArchiveActive = true;
-if (ArgValue == "--no-whole-archive")
- WholeArchiveActive = false;
- }
-}
- }
-
- return WholeArchiveActive;
-}
-
-/// Add Fortran runtime libs for MSVC
-static void addFortranRuntimeLibsMSVC(const ArgList ,
- llvm::opt::ArgStringList ) {
- unsigned RTOptionID = options::OPT__SLASH_MT;
- if (auto *rtl = Args.getLastArg(options::OPT_fms_runtime_lib_EQ)) {
-RTOptionID = llvm::StringSwitch(rtl->getValue())
- .Case("static", options::OPT__SLASH_MT)
- .Case("static_dbg", options::OPT__SLASH_MTd)
- .Case("dll", options::OPT__SLASH_MD)
- .Case("dll_dbg", options::OPT__SLASH_MDd)
- .Default(options::OPT__SLASH_MT);
- }
- switch (RTOptionID) {
- case options::OPT__SLASH_MT:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static.lib");
-break;
- case options::OPT__SLASH_MTd:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static_dbg.lib");
-break;
- case options::OPT__SLASH_MD:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic.lib");
-break;
- case options::OPT__SLASH_MDd:
-CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic_dbg.lib");
-break;
- }
-}
-
-/// Add Fortran runtime libs
void tools::addFortranRuntimeLibs(const ToolChain , const ArgList ,
llvm::opt::ArgStringList ) {
- // 1. Link FortranRuntime and FortranDecimal
- // These are handled earlier on Windows by telling the frontend driver to
- // add the correct libraries to link against as dependents in the object
- // file.
- if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
-CmdArgs.push_back("-lFortranRuntime");
-CmdArgs.push_back("-lFortranDecimal");
- }
+ // These are handled earlier on Windows by telling the frontend driver to add
+ // the correct libraries to link against as dependents in the object file.
- // 2. Link FortranMain
- // If -fno-fortran-main has been passed, skip linking Fortran_main.a
- if (Args.hasArg(options::OPT_no_fortran_main))
-return;
+ // if -fno-fortran-main has been passed, skip linking Fortran_main.a
+ bool LinkFortranMain = !Args.hasArg(options::OPT_no_fortran_main);
+ if (!TC.getTriple().isKnownWindowsMSVCEnvironment()) {
+if (LinkFortranMain) {
+ // The --whole-archive option needs to be part of the link line to
+ // make sure that the main() function from Fortran_main.a is pulled
+ // in by the linker. Determine if --whole-archive is active when
+ // flang will try to link Fortran_main.a. If it is, don't add the
+ // --whole-archive flag to the link line. If it's not, add a proper
+ // --whole-archive/--no-whole-archive bracket to the link line.
+ bool WholeArchiveActive = false;
+ for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA)) {
+if (Arg) {
+ for (StringRef ArgValue : Arg->getValues()) {
+if (ArgValue == "--whole-archive")
+ WholeArchiveActive = true;
+if (ArgValue == "--no-whole-archive")
+ WholeArchiveActive = false;
+ }
+}
+ }
- // 2.1. MSVC
- if (TC.getTriple().isKnownWindowsMSVCEnvironment()) {
-addFortranRuntimeLibsMSVC(Args, CmdArgs);
-return;
- }
+ // TODO: Find an equivalent of `--whole-archive` for Darwin.
+ if (!WholeArchiveActive && !TC.getTriple().isMacOSX()) {
+CmdArgs.push_back("--whole-archive");
+CmdArgs.push_back("-lFortran_main");
+
[llvm] [clang] [clang-tools-extra] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -228,87 +228,86 @@ define void @widen_broadcast_unaligned(ptr %p0, i32 %v) {
}
define i128 @load_i128(ptr %ptr) {
-; CHECK-O0-LABEL: load_i128:
-; CHECK-O0: # %bb.0:
-; CHECK-O0-NEXT:pushq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O0-NEXT:.cfi_offset %rbx, -16
-; CHECK-O0-NEXT:xorl %eax, %eax
-; CHECK-O0-NEXT:movl %eax, %ebx
-; CHECK-O0-NEXT:movq %rbx, %rax
-; CHECK-O0-NEXT:movq %rbx, %rdx
-; CHECK-O0-NEXT:movq %rbx, %rcx
-; CHECK-O0-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O0-NEXT:popq %rbx
-; CHECK-O0-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O0-NEXT:retq
-;
-; CHECK-O3-LABEL: load_i128:
-; CHECK-O3: # %bb.0:
-; CHECK-O3-NEXT:pushq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 16
-; CHECK-O3-NEXT:.cfi_offset %rbx, -16
-; CHECK-O3-NEXT:xorl %eax, %eax
-; CHECK-O3-NEXT:xorl %edx, %edx
-; CHECK-O3-NEXT:xorl %ecx, %ecx
-; CHECK-O3-NEXT:xorl %ebx, %ebx
-; CHECK-O3-NEXT:lock cmpxchg16b (%rdi)
-; CHECK-O3-NEXT:popq %rbx
-; CHECK-O3-NEXT:.cfi_def_cfa_offset 8
-; CHECK-O3-NEXT:retq
+; CHECK-O0-CUR-LABEL: load_i128:
preames wrote:
Your tests need updated, these check prefixes no longer exist.
https://github.com/llvm/llvm-project/pull/74275
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang-tools-extra] [clang] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -30095,12 +30102,16 @@ TargetLoweringBase::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
Type *MemType = SI->getValueOperand()->getType();
- bool NoImplicitFloatOps =
- SI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
- if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
- !Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
- (Subtarget.hasSSE1() || Subtarget.hasX87()))
-return AtomicExpansionKind::None;
+ if (!SI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
+ !Subtarget.useSoftFloat()) {
+if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
+(Subtarget.hasSSE1() || Subtarget.hasX87()))
preames wrote:
Do we need to check the alignment here?
https://github.com/llvm/llvm-project/pull/74275
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -30115,12 +30126,16 @@
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
// can use movq to do the load. If we have X87 we can load into an 80-bit
// X87 register and store it to a stack temporary.
preames wrote:
Can you move the comment down to the case it applies to (inside the outer if).
Currently, it binds to both cases which is misleading.
https://github.com/llvm/llvm-project/pull/74275
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op,
SelectionDAG ,
if (!IsSeqCst && IsTypeLegal)
return Op;
- if (VT == MVT::i64 && !IsTypeLegal) {
+ if (!IsTypeLegal && !Subtarget.useSoftFloat() &&
+ !DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat)) {
+SDValue Chain;
+// For illegal i128 atomic_store, when AVX is enabled, we can simply emit a
+// vector store.
+if (VT == MVT::i128) {
+ if (Subtarget.is64Bit() && Subtarget.hasAVX()) {
preames wrote:
Looks like you can collapse one level of if clause here.
https://github.com/llvm/llvm-project/pull/74275
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] [llvm] [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (PR #74275)
@@ -31259,14 +31274,23 @@ static SDValue LowerATOMIC_STORE(SDValue Op,
SelectionDAG ,
if (!IsSeqCst && IsTypeLegal)
return Op;
- if (VT == MVT::i64 && !IsTypeLegal) {
+ if (!IsTypeLegal && !Subtarget.useSoftFloat() &&
+ !DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat)) {
+SDValue Chain;
+// For illegal i128 atomic_store, when AVX is enabled, we can simply emit a
+// vector store.
+if (VT == MVT::i128) {
+ if (Subtarget.is64Bit() && Subtarget.hasAVX()) {
+SDValue VecVal = DAG.getBitcast(MVT::v2i64, Node->getVal());
+Chain = DAG.getStore(Node->getChain(), dl, VecVal, Node->getBasePtr(),
+ Node->getMemOperand());
+ }
+}
+
// For illegal i64 atomic_stores, we can try to use MOVQ or MOVLPS if SSE
// is enabled.
-bool NoImplicitFloatOps =
-DAG.getMachineFunction().getFunction().hasFnAttribute(
-Attribute::NoImplicitFloat);
-if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
- SDValue Chain;
+if (VT == MVT::i64) {
if (Subtarget.hasSSE1()) {
preames wrote:
Same here.
https://github.com/llvm/llvm-project/pull/74275
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Reduce the size of the index used for RVV intrinsics. NFC (PR #74906)
preames wrote: > > LGTM - though maybe use uint32_t? > > Looking at this code, the whole Intrinsics map vs OverloadIntrinsic map > > structure loops to have heavy redundancy and could be greatly simplified. > > Maybe a follow up? > > Did you have a specific idea in mind? Maybe we could use a single map and use > the size of the vector being more than 1 to detect overloaded? > > I'm skeptical that the `8` is the correct inline space for the SmallVector in > OverloadedIntrinsicMap. That's basically where I was going. We track every name to index mapping twice, and we really only need to do so once. Maybe the cost of a SmallVector is high enough to be worth two structures, but then why not have a signal value in the primary map and a much smaller index keyed overload structure? https://github.com/llvm/llvm-project/pull/74906 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
