[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D70401#4204511 , @recallmenot wrote:

> Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
> I tried replacing my distros llvm and clang with a patched version of this 
> like this:
>
>   git clone https://aur.archlinux.org/llvm-git.git
>   cd llvm-git
>   mkdir src
>   cd src
>   git clone https://github.com/llvm/llvm-project.git
>   cd llvm-project
>   arc patch D70401
>   cd ../..
>   mv llvm-config.h src/
>   makepkg -es
>   sudo pacman -Rd --nodeps clang llvm
>   makepkg -eid
>
> but that bricked my xfce-wayland-manjaro DE (one screen black)
> And in config.toml if I put
>
>   [build]
>   target = "riscv32i-unknown-none-elf"
>   rustflags = [
>   "-C", "target-feature=+e,+c"
>   ]
>
> then build with cargo build
> LLVM still complains it doesn't implement CodeGen for RV32E yet
> What am I doing wrong?
> Ended up reverting to repository llvm and clang, desktop now works again but 
> CodeGen is obviously missing.

I don't see any obvious problem here.
I am not familiar with rust. Is `riscv32i-unknown-none-elf` a valid target for 
`rustc`, it should be something like `riscv32-unknown-elf` in LLVM I think. And 
is `target-feature=+e,+c` the right way to specify features?
Can you please provide the whole command/arguments passed to LLVM?


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Edmund Raile via Phabricator via cfe-commits]

recallmenot added a comment.

Hi, I'm working on CH32V003 for rust and it uses RV32EC core.
I tried replacing my distros llvm and clang with a patched version of this like 
this:

  git clone https://aur.archlinux.org/llvm-git.git
  cd llvm-git
  mkdir src
  cd src
  git clone https://github.com/llvm/llvm-project.git
  cd llvm-project
  arc patch D70401
  cd ../..
  mv llvm-config.h src/
  makepkg -es
  sudo pacman -Rd --nodeps clang llvm
  makepkg -eid

but that bricked my xfce-wayland-manjaro DE (one screen black)
And in config.toml if I put

  [build]
  target = "riscv32i-unknown-none-elf"
  rustflags = [
"-C", "target-feature=+e,+c"
  ]

then build with cargo build
LLVM still complains it doesn't implement CodeGen for RV32E yet
What am I doing wrong?
Ended up reverting to repository llvm and clang, desktop now works again but 
CodeGen is obviously missing.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D70401#3948829 , @StephenFan wrote:

> In D70401#3873874 , @pcwang-thead 
> wrote:
>
>> In D70401#3873347 , @luojia wrote:
>>
>>> Hello! Any further updates to this patch? It seems like all the inline 
>>> comments have been resolved.
>>
>> We have done some works in this patch to make it compatible with GCC, it can 
>> be combined with GNU toolchain now.
>>
>> But as what have been discussed[1, 2], we may proceed with this patch when 
>> RV32E/ilp32e is ratified.
>>
>> 1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
>> 2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257
>
> RV32E/ilp32e has been 
> ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan 
> to proceed with this patch? :)

I will follow the proceeding of spec and finish this patch, but I don't think 
they have been ratified.
There are some changes about RV32E/RV64E 
, but I think they are 
still **proposal**.
And, there are still some issues we need to fix in the psabi:

- Add the LP64E ABI, to support RV64E 

- ilp32e issue 


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D70401#3873874 , @pcwang-thead 
wrote:

> In D70401#3873347 , @luojia wrote:
>
>> Hello! Any further updates to this patch? It seems like all the inline 
>> comments have been resolved.
>
> We have done some works in this patch to make it compatible with GCC, it can 
> be combined with GNU toolchain now.
>
> But as what have been discussed[1, 2], we may proceed with this patch when 
> RV32E/ilp32e is ratified.
>
> 1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
> 2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

RV32E/ilp32e has been 
ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan to 
proceed with this patch? :)


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead marked an inline comment as done.
pcwang-thead added a comment.

In D70401#3873347 , @luojia wrote:

> Hello! Any further updates to this patch? It seems like all the inline 
> comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be 
combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when 
RV32E/ilp32e is ratified.

1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Luo Jia via Phabricator via cfe-commits]

luojia added a comment.

Hello! Any further updates to this patch? It seems like all the inline comments 
have been resolved.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead marked an inline comment as done.
pcwang-thead added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411
 // implemented such that the stack will always be 16 byte aligned.
 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
 RVFI->setLibCallStackSize(LibCallFrameSize);

zixuan-wu wrote:
> I think this 16 should be adjusted as above logic for rv32e
Thanks. :-)


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411
 // implemented such that the stack will always be 16 byte aligned.
 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
 RVFI->setLibCallStackSize(LibCallFrameSize);

I think this 16 should be adjusted as above logic for rv32e


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:106
+for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
+  markSuperRegs(Reserved, Reg);
+

I am wondering whether we need construct another new RegisterClass for RV32E 
instead of GPR, for example eGPR, so that the num and other info such as 
weight, etc of RegisterClass can adjust. Then the reserved logic is not 
necessary.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.
Herald added a subscriber: StephenFan.

In D70401#3391561 , @khchen wrote:

> I found 
> https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c
>  result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
> Did you have same issue?

I got the same issue, but it may be not this patch's problem.
Here is the reduced case:

  #include 
  
  unsigned long long getL() { return 0xafafafafc5c5b8a3ull; }
  int main(int argc, char **argv) {
unsigned long long UL = getL(); /* 0xafafafafc5c5b8a3 */
unsigned int ui = (unsigned int)UL; /* 0xc5c5b8a3 =  3318069411 */
printf("ui = %u (0x%x)\t\tUL-ui = %lld (0x%llx)\n", ui, ui, UL - ui, UL - 
ui);
  }

GCC output is:

  ui = 3318069411 (0xc5c5b8a3)UL-ui = -5787213829993660416 
(0xafafafaf)

LLVM output is:

  ui = 3318069411 (0xc5c5b8a3)UL-ui = 0 (0xafafafaf)

The problem is the way to pass arguments to `printf`.
GCC asm:

li  a4,-1347440640
addisp,sp,-24
addia4,a4,-81
sw  a4,8(sp)
lw  a5,8(sp)
li  a2,-976896000
addia2,a2,-1885
lui a0,%hi(.LC1)
sw  a5,0(sp)
li  a3,0
li  a5,0
mv  a1,a2
addia0,a0,%lo(.LC1)
sw  ra,20(sp)
sw  a3,4(sp)
callprintf

LLVM asm:

addisp, sp, -16
sw  ra, 12(sp)  # 4-byte Folded Spill
sw  s0, 8(sp)   # 4-byte Folded Spill
addis0, sp, 16
andisp, sp, -8
lui a0, 719611
addia5, a0, -81
sw  a5, 4(sp)
lui a0, %hi(.L.str)
addia0, a0, %lo(.L.str)
lui a1, 810076
addia1, a1, -1885
sw  zero, 0(sp)
mv  a2, a1
mv  a4, zero
callprintf

Both GCC and LLVM pass format string and two `ui` by `a0, a1, a2`, the 
difference is how they pass rest variadic arguments.
`UL-ui` is with 2*XLEN size, so it will be spilt to two part (low and high 
32-bits). Low part is 0x, high part is 0xafafafaf.
For GCC:

  First UL-ui  : low -> a3, high -> a4
  Second UL-ui : low -> a5, high -> stack.0

For LLVM:

  First UL-ui  : low -> a4, high -> a5
  Second UL-ui : low -> stack.0, high -> stack.1

Because we use GLIBC compiled by GCC  while linking with LLVM's output, so in 
`printf`'s view:

  a3 -> undefined, so it is zero.
  a4 -> low part, 0x
  a5 -> high part, 0xafafafaf
  stack.0 -> low part, 0x
  stack.1 -> not used

It get `0x` and `0xafafafaf` for two `UL-ui` (seen as 
the output).

In the ABI specification, it says (Integer Calling Convention 
):

  In the base integer calling convention, variadic arguments are passed in the 
same manner as named arguments, with one exception. Variadic arguments with 
2×XLEN-bit alignment and size at most 2×XLEN bits are passed in an aligned 
register pair (i.e., the first register in the pair is even-numbered), or on 
the stack by value if none is available. After a variadic argument has been 
passed on the stack, all future arguments will also be passed on the stack 
(i.e. the last argument register may be left unused due to the aligned register 
pair rule).

And this is what LLVM do for ILP32E currently.

I saw the same issue on Github(Inconsistent variadic argument passing behavior 
between ilp32 and ilp32e for long long/double 
), so shall LLVM be 
compatible with GCC's behavior?
@kito-cheng @khchen


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D70401#3395340 , @kito-cheng wrote:

> Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, 
> so here is note from my site:
>
> RISC-V psABI doc still say "we don't  guarantee the stability of `ILP32E`", 
> the reason is RV32E still not a ratified extension, but as psABI chair, what 
> I can say is we intend to do NOT change as possible.
>
> As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so 
> I support ilp32e should be supported on LLVM upstream.

Thanks! I will spend some time to make this patch compatible with GCC 
implementation, please feel free to give some comments and suggestions!


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so 
here is note from my site:

RISC-V psABI doc still say "we don't  guarantee the stability of `ILP32E`", the 
reason is RV32E still not a ratified extension, but as psABI chair, what I can 
say is we intend to do NOT change as possible.

As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so I 
support ilp32e should be supported on LLVM upstream.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> If I understand correctly, E can't be combined with D in current 
> specification since E must use ILP32E calling convention.

Calling convention and extensions are separated, calling convention are specify 
the how argument passing and the register convention, so ILP32E *can* use with 
`-march=rv32efd`, but it can't pass or return floating point type in FPR.

Just like we can `ILP32` for `-march=rv32ifd` and `LP64` with `-march=rv64ifd`, 
you may confused about the opposite combination like `ILP32D` with 
`-march=rv32i` and `LP64D` with `-march=rv64i` is not work, that's because it 
require pass or return floating point type in FPR, but FPR isn't existing in 
such ISA config.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.
Herald added a subscriber: s.

In D70401#3384758 , @pcwang-thead 
wrote:

> In D70401#3250049 , @khchen wrote:
>
>> 1. please add a check here 
>> 
>>  and a clang cc1 test for it.
>> 2. Have you try to run llvm-test-suite with rv32e config on qemu?
>
>
>
> 1. Thanks, I may do it later. And here is a question: the comment 
> 
>  says `It is illegal to specify 'e' extensions with 'f' and 'd'`.
>
> While ilp32e 
> 
>  says:
>
>> The ILP32E calling convention is not compatible with ISAs that have 
>> registers that require load and store alignments of more than 32 bits. In 
>> particular, this calling convention must not be used with the D ISA 
>> extension.
>
> And, the RV32E 
>  chapter 
> in RISCV ISA manual says:
>
>> RV32E can be combined with all current standard extensions.
>
> If I understand correctly, E can't be combined with D in current 
> specification since E must use ILP32E calling convention.

IMO, at least clang need to follows the gcc's implementation.
I guess gcc implementation follow riscv-elf-psabi-doc, @kito-cheng could you 
please confirm that?

> 2. I have run llvm-test-suite with rv32e on qemu, and found no major fault 
> for current implementation. Some tests are disabled because they can't run on 
> bare mental (sees Disabled llvm-test-suite cases 
> ).
>
> There are some failed tests due to floating-point precision, but I saw the 
> same result when run with  rv32imc on bare mental. I haven't taken the time 
> to find out the reason, but I guess it may be soft-float issues.

Thanks for testing!! I also tested your patch locally, 
Could you please make sure all gcc and clang results are the same in your 
failed tests?

I found 
https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c
 result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
Did you have same issue?

my build option:

  $/path/to/rv32e-gcc/bin/riscv32-unknown-elf-gcc -march=rv32e -mabi=ilp32e 
2003-05-26-Shorts.c
  $./bin/clang --target=riscv32 -march=rv32e -mabi=ilp32e 
--gcc-toolchain=/path/to/rv32e-gcc/ 2003-05-26-Shorts.c 

clang output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = 0 (0xafafafaf)

  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = -2060025877491592863 
(0xe3695161)   


  i = -976897885 (0xc5c5b8a3) L-i = 0 (0xafafafb0)  

   i* i = -1912031287 (0x8e08b7c9)L/ i = 6996953267980741613 
(0x611a2bed0001)   


  us= 47267 (0xb8a3)  UL-us = -4195947477825748992 
(0xc5c5afafafaf) 
  us*us = 2234169289 (0x852ab7c9)   UL/us = 1452874783539635691 
(0x1429a5ebf397)


   s= -18269 (0xb8a3) L-s = -4195666002849038335 
(0xc5c6afafafaf)   
   s* s = 333756361 (0x13e4b7c9)  L/ s = -7718140893307295808 
(0x94e3a7c1201b)  


  ub= 163 (0xa3)  UL-ub = -4195745167686238208 
(0xc5c5b800afafafaf) 
  ub*ub = 26569 (0x67c9)  UL/ub = 2350833624863004346 
(0x209fd6ba0113eca9)  


   b= -93 (0xffa3)L-b = -4195744068174610431 
(0xc5c5b900afafafaf)   
   b* b = 8649 (0x21c9)   L/b = -1938405340110362979 
(0xe519669d00dd1421)   

gcc output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = -5787213829993660416 
(0xafafafaf)
  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = 3815330145 (0xe3695161)
  
  i = -976897885 (0xc5c5b8a3) L-i = -5787213825698693120 
(0xafafafb0)
   i* i = -1912031287 (0x8e08b7c9)L/ i = 5924072429 (0x1611a2bed)
  
  us= 47267 (0xb8a3)  UL-us = -5787213826675638272 
(0xafafafafc5c5)
  us*us = 2234169289 (0x852ab7c9)   UL/us = 267830203885035 (0xf3971429a5eb)
  
   s= -18269 (0xb8a3) L-s = -5787213826675572736 
(0xafafafafc5c6)
   s* s = 333756361 (0x13e4b7c9)  L/ s = 316777810864064 (0x1201b94e3a7c0)
  
  ub= 163 (0xa3)  UL-ub = -5787213826675591168 

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead commandeered this revision.
pcwang-thead edited reviewers, added: zixuan-wu; removed: pcwang-thead.
pcwang-thead added a comment.
Herald added a subscriber: arichardson.
Herald added a project: All.

In D70401#3250049 , @khchen wrote:

> 1. please add a check here 
> 
>  and a clang cc1 test for it.
> 2. Have you try to run llvm-test-suite with rv32e config on qemu?



1. Thanks, I may do it later. And here is a question: the comment 

 says `It is illegal to specify 'e' extensions with 'f' and 'd'`.

While ilp32e 

 says:

> The ILP32E calling convention is not compatible with ISAs that have registers 
> that require load and store alignments of more than 32 bits. In particular, 
> this calling convention must not be used with the D ISA extension.

And, the RV32E 
 chapter 
in RISCV ISA manual says:

> RV32E can be combined with all current standard extensions.

If I understand correctly, E can't be combined with D in current specification 
since E must use ILP32E calling convention.

2. I have run llvm-test-suite with rv32e on qemu, and found no major fault for 
current implementation. Some tests are disabled because they can't run on bare 
mental (sees Disabled llvm-test-suite cases ).

There are some failed tests due to floating-point precision, but I saw the same 
result when run with  rv32gc on bare mental. I haven't taken the time to find 
out the reason, but I guess it may be soft-float issues.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D70401#3325419 , @zixuan-wu wrote:

> It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there 
> are no workable environment such as runtime and kernel for ilp32e in GNU 
> series tools.
> And we can not run llvm-test-suite in baremental environment(NOT linux but 
> elf triple). So I have a question about how to test llvm in elf triple and 
> environment? Is there any test case llvm community normally uses and accepts?

I believe you can try QEMU, I tried it before.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/JE0aG-Mr0u4/m/tfFoITv7AgAJ
For llvm-test-suite, you could disable some non-baremental tests manually.
I found some issues in my local rv32e implementation by running llvm-test-suite 
before, it's why I think it's good to have a test.

Maybe the other reviewers have different opinions about this.
@luismarques @jrtc27 @asb @kito-cheng What do you think?


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu added a comment.

Sorry for the wrong action of commandeer, @pcwang-thead will still be the 
author.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu added a comment.

It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are 
no workable environment such as runtime and kernel for ilp32e in GNU series 
tools.
And we can not run llvm-test-suite in baremental environment(NOT linux but elf 
triple). So I have a question about how to test llvm in elf triple and 
environment? Is there any test case llvm community normally uses and accepts?


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu commandeered this revision.
zixuan-wu added a reviewer: pcwang-thead.
zixuan-wu added a comment.

In D70401#3250049 , @khchen wrote:

> 2. Have you try to run llvm-test-suite with rv32e config on qemu?

It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are 
no workable environment such as runtime and kernel for ilp32e in GNU series 
tools.
And we can not run llvm-test-suite in baremental environment(NOT linux but elf 
triple). So I have a question about how to test llvm in elf triple and 
environment? Is there any test case llvm community normally uses and accepts?


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: llvm/lib/Support/TargetParser.cpp:339
+if (ISAInfo.hasExtension("d"))
+  return "ilp32d";
 return "ilp32";

khchen wrote:
> why do we need to change the order?
IMO, when `e` is combined with `d`, `e` should have higher priority so that the 
default ABI will be `ilp32e` and then this error will be reported.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

1. please add a check here 

 and a clang cc1 test for it.
2. Have you try to run llvm-test-suite with rv32e config on qemu?




Comment at: llvm/lib/Support/TargetParser.cpp:339
+if (ISAInfo.hasExtension("d"))
+  return "ilp32d";
 return "ilp32";

why do we need to change the order?


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.
Herald added subscribers: alextsao1999, eopXD.

Gentle ping.

We are testing this patch and I'd like to get some nice advice.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

ping.


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