[coreboot] Could coreboot work on my laptop?
Hi, First of all, congratulations for your work! I wish you a great success with coreboot, it really is an interesting and useful project. I have a laptop with the following material. Do you think I can install Coreboot? Motherboard: Manufacturer: Intel Corporation Product Name: SANTA ROSA CRB chipsets: Manufacturer: Intel Corporation Product Name: Crestline ICH8M Chipset processor: Intel Core 2 Duo The lspci -tvnn command gives me the following: -[:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-01.0-[:01]00.0 nVidia Corporation GeForce 8600M GS [10de:0425] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[:02-03]00.0 Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter [168c:001c] +-1c.2-[:04-05]00.0 Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] +-1c.3-[:06-07]-- +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[:08]-- +-1f.0 Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] +-1f.2 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA IDE Controller [8086:2828] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] I don't know what I/O chip is on the mainboard, and superiotool -dV fails to find anything, and the result of flashrom -V is attached in a file. And thanks for your hard work! Lionel flashrom_results Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4250 - in trunk/coreboot-v2: ...
s...@coreboot.org wrote: Log: Run dos2unix on all files: Thanks! Please watch out for line endings when committing. Thanks! //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4248 - in trunk/coreboot-v2/src/ma inboard: rca/rm4100 thomson/ip1000
On Sat, 02 May 2009 13:46:25 +0200, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: Hi Joe, there is a small problem with your commit. Both files has their line endings (newlines) changed from LF (Unix style) to CR+LF (DOS style). On 02.05.2009 02:50, s...@coreboot.org wrote: Author: linux_junkie Date: 2009-05-02 02:50:58 +0200 (Sat, 02 May 2009) New Revision: 4248 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/gpio.c trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c Log: Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something. Signed-off-by: Joseph Smith j...@settoplinux.org Acked-by: Joseph Smith j...@settoplinux.org Almost all files in our tree have LF line terminators. Exceptions are: CR+LF: src/southbridge/intel/i82801ca/i82801ca_pci.c src/northbridge/intel/i82830/vga.c src/cpu/intel/model_f4x/microcode_MBDF410D.h src/mainboard/thomson/ip1000/gpio.c src/mainboard/dell/s1850/irq_tables.c src/mainboard/rca/rm4100/gpio.c Mix of CR+LF and LF: src/mainboard/msi/ms9185/Options.lb src/mainboard/msi/ms9282/Options.lb src/mainboard/asus/m2v-mx_se/Options.lb I'll have to admit, sometimes when it is slow at work I do use wordpad/notepad to edit/create files. Unfortunately when I am at work I am stuck in windows world... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4250 - in trunk/coreboot-v2: ...
On Sat, 2 May 2009 15:26:50 +0200, Peter Stuge pe...@stuge.se wrote: s...@coreboot.org wrote: Log: Run dos2unix on all files: Thanks! Please watch out for line endings when committing. Thanks! Thanks Peter, I will store that command in my memory bank :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
This patch lets you assign PIRQs in mainboard Config.lb or use the default
ones listed in i82801xx_lpc.c.
Once and if everyone converts to the better way of assign PIRQs in
mainboard Config.lb the option of using the defaults can be removed. The
patch enables a margin of time to do so.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.orgIndex: src/southbridge/intel/i82801xx/i82801xx_lpc.c
===
--- src/southbridge/intel/i82801xx/i82801xx_lpc.c (revision 4250)
+++ src/southbridge/intel/i82801xx/i82801xx_lpc.c (working copy)
@@ -36,6 +36,8 @@
#define NMI_OFF 0
+typedef struct southbridge_intel_i82801xx_config config_t;
+
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - = Reserved
* 0x01 - 0001 = Reserved
@@ -66,7 +68,11 @@
#define PIRQG 0x0A
#define PIRQH 0x0B
-/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your mainboards Config.lb.
+*/
void i82801xx_enable_apic(struct device *dev)
{
@@ -114,18 +120,59 @@
static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
{
- /* Route PIRQA - PIRQD. */
- pci_write_config8(dev, PIRQA_ROUT, PIRQA);
- pci_write_config8(dev, PIRQB_ROUT, PIRQB);
- pci_write_config8(dev, PIRQC_ROUT, PIRQC);
- pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ /* Get the chip configuration */
+ config_t *config = dev-chip_info;
+ if (config-pirqa_routing) {
+ pci_write_config8(dev, PIRQA_ROUT, config-pirqa_routing);
+ } else {
+ pci_write_config8(dev, PIRQA_ROUT, PIRQA);
+ }
+
+ if (config-pirqb_routing) {
+ pci_write_config8(dev, PIRQB_ROUT, config-pirqb_routing);
+ } else {
+ pci_write_config8(dev, PIRQB_ROUT, PIRQB);
+ }
+
+ if (config-pirqc_routing) {
+ pci_write_config8(dev, PIRQC_ROUT, config-pirqc_routing);
+ } else {
+ pci_write_config8(dev, PIRQC_ROUT, PIRQC);
+ }
+
+ if (config-pirqd_routing) {
+ pci_write_config8(dev, PIRQD_ROUT, config-pirqd_routing);
+ } else {
+ pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ }
+
/* Route PIRQE - PIRQH (for ICH2-ICH9). */
if (ich_model = 0x2440) {
- pci_write_config8(dev, PIRQE_ROUT, PIRQE);
- pci_write_config8(dev, PIRQF_ROUT, PIRQF);
- pci_write_config8(dev, PIRQG_ROUT, PIRQG);
- pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+
+ if (config-pirqe_routing) {
+ pci_write_config8(dev, PIRQE_ROUT, config-pirqe_routing);
+ } else {
+ pci_write_config8(dev, PIRQE_ROUT, PIRQE);
+ }
+
+ if (config-pirqf_routing) {
+ pci_write_config8(dev, PIRQF_ROUT, config-pirqf_routing);
+ } else {
+ pci_write_config8(dev, PIRQF_ROUT, PIRQF);
+ }
+
+ if (config-pirqg_routing) {
+ pci_write_config8(dev, PIRQG_ROUT, config-pirqg_routing);
+ } else {
+ pci_write_config8(dev, PIRQG_ROUT, PIRQG);
+ }
+
+ if (config-pirqh_routing) {
+ pci_write_config8(dev, PIRQH_ROUT, config-pirqh_routing);
+ } else {
+ pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+ }
}
}
Index: src/southbridge/intel/i82801xx/chip.h
===
--- src/southbridge/intel/i82801xx/chip.h (revision 4250)
+++ src/southbridge/intel/i82801xx/chip.h (working copy)
@@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
On Sat, 02 May 2009 11:15:32 -0400, Joseph Smith j...@settoplinux.org
wrote:
This patch lets you assign PIRQs in mainboard Config.lb or use the
default
ones listed in i82801xx_lpc.c.
Once and if everyone converts to the better way of assign PIRQs in
mainboard Config.lb the option of using the defaults can be removed. The
patch enables a margin of time to do so.
oh, thanks Stefan for the idea, tested, and
Signed-off-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.orgIndex: src/southbridge/intel/i82801xx/i82801xx_lpc.c
===
--- src/southbridge/intel/i82801xx/i82801xx_lpc.c (revision 4250)
+++ src/southbridge/intel/i82801xx/i82801xx_lpc.c (working copy)
@@ -36,6 +36,8 @@
#define NMI_OFF 0
+typedef struct southbridge_intel_i82801xx_config config_t;
+
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - = Reserved
* 0x01 - 0001 = Reserved
@@ -66,7 +68,11 @@
#define PIRQG 0x0A
#define PIRQH 0x0B
-/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your mainboards Config.lb.
+*/
void i82801xx_enable_apic(struct device *dev)
{
@@ -114,18 +120,59 @@
static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
{
- /* Route PIRQA - PIRQD. */
- pci_write_config8(dev, PIRQA_ROUT, PIRQA);
- pci_write_config8(dev, PIRQB_ROUT, PIRQB);
- pci_write_config8(dev, PIRQC_ROUT, PIRQC);
- pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ /* Get the chip configuration */
+ config_t *config = dev-chip_info;
+ if (config-pirqa_routing) {
+ pci_write_config8(dev, PIRQA_ROUT, config-pirqa_routing);
+ } else {
+ pci_write_config8(dev, PIRQA_ROUT, PIRQA);
+ }
+
+ if (config-pirqb_routing) {
+ pci_write_config8(dev, PIRQB_ROUT, config-pirqb_routing);
+ } else {
+ pci_write_config8(dev, PIRQB_ROUT, PIRQB);
+ }
+
+ if (config-pirqc_routing) {
+ pci_write_config8(dev, PIRQC_ROUT, config-pirqc_routing);
+ } else {
+ pci_write_config8(dev, PIRQC_ROUT, PIRQC);
+ }
+
+ if (config-pirqd_routing) {
+ pci_write_config8(dev, PIRQD_ROUT, config-pirqd_routing);
+ } else {
+ pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ }
+
/* Route PIRQE - PIRQH (for ICH2-ICH9). */
if (ich_model = 0x2440) {
- pci_write_config8(dev, PIRQE_ROUT, PIRQE);
- pci_write_config8(dev, PIRQF_ROUT, PIRQF);
- pci_write_config8(dev, PIRQG_ROUT, PIRQG);
- pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+
+ if (config-pirqe_routing) {
+ pci_write_config8(dev, PIRQE_ROUT, config-pirqe_routing);
+ } else {
+ pci_write_config8(dev, PIRQE_ROUT, PIRQE);
+ }
+
+ if (config-pirqf_routing) {
+ pci_write_config8(dev, PIRQF_ROUT, config-pirqf_routing);
+ } else {
+ pci_write_config8(dev, PIRQF_ROUT, PIRQF);
+ }
+
+ if (config-pirqg_routing) {
+ pci_write_config8(dev, PIRQG_ROUT, config-pirqg_routing);
+ } else {
+ pci_write_config8(dev, PIRQG_ROUT, PIRQG);
+ }
+
+ if (config-pirqh_routing) {
+ pci_write_config8(dev, PIRQH_ROUT, config-pirqh_routing);
+ } else {
+ pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+ }
}
}
Index: src/southbridge/intel/i82801xx/chip.h
===
--- src/southbridge/intel/i82801xx/chip.h (revision 4250)
+++ src/southbridge/intel/i82801xx/chip.h (working copy)
@@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
--
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Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
Very nice. Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
It does look like an SMP machine in which both CPUs are trying to run as the BSP. Possible? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4251 - trunk/coreboot-v2/src/southbridge/intel/i82801xx
Author: linux_junkie
Date: 2009-05-02 23:30:57 +0200 (Sat, 02 May 2009)
New Revision: 4251
Modified:
trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
Log:
Assign PIRQs in mainboard Config.lb or use the default ones listed in
i82801xx_lpc.c.
Signed-off-by: Joseph Smith j...@settoplinux.org
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h
===
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02
12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02
21:30:57 UTC (rev 4251)
@@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config {
+ /**
+* Interrupt Routing configuration
+* If bit7 is 1, the interrupt is disabled.
+*/
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
===
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-05-02 12:42:30 UTC (rev 4250)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c
2009-05-02 21:30:57 UTC (rev 4251)
@@ -36,6 +36,8 @@
#define NMI_OFF 0
+typedef struct southbridge_intel_i82801xx_config config_t;
+
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - = Reserved
* 0x01 - 0001 = Reserved
@@ -66,7 +68,11 @@
#define PIRQG 0x0A
#define PIRQH 0x0B
-/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */
+/*
+ * Use 0x0ef8 for a bitmap to cover all these IRQ's.
+ * Use the defined IRQ values above or set mainboard
+ * specific IRQ values in your mainboards Config.lb.
+*/
void i82801xx_enable_apic(struct device *dev)
{
@@ -114,18 +120,59 @@
static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
{
- /* Route PIRQA - PIRQD. */
- pci_write_config8(dev, PIRQA_ROUT, PIRQA);
- pci_write_config8(dev, PIRQB_ROUT, PIRQB);
- pci_write_config8(dev, PIRQC_ROUT, PIRQC);
- pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ /* Get the chip configuration */
+ config_t *config = dev-chip_info;
+ if (config-pirqa_routing) {
+ pci_write_config8(dev, PIRQA_ROUT, config-pirqa_routing);
+ } else {
+ pci_write_config8(dev, PIRQA_ROUT, PIRQA);
+ }
+
+ if (config-pirqb_routing) {
+ pci_write_config8(dev, PIRQB_ROUT, config-pirqb_routing);
+ } else {
+ pci_write_config8(dev, PIRQB_ROUT, PIRQB);
+ }
+
+ if (config-pirqc_routing) {
+ pci_write_config8(dev, PIRQC_ROUT, config-pirqc_routing);
+ } else {
+ pci_write_config8(dev, PIRQC_ROUT, PIRQC);
+ }
+
+ if (config-pirqd_routing) {
+ pci_write_config8(dev, PIRQD_ROUT, config-pirqd_routing);
+ } else {
+ pci_write_config8(dev, PIRQD_ROUT, PIRQD);
+ }
+
/* Route PIRQE - PIRQH (for ICH2-ICH9). */
if (ich_model = 0x2440) {
- pci_write_config8(dev, PIRQE_ROUT, PIRQE);
- pci_write_config8(dev, PIRQF_ROUT, PIRQF);
- pci_write_config8(dev, PIRQG_ROUT, PIRQG);
- pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+
+ if (config-pirqe_routing) {
+ pci_write_config8(dev, PIRQE_ROUT,
config-pirqe_routing);
+ } else {
+ pci_write_config8(dev, PIRQE_ROUT, PIRQE);
+ }
+
+ if (config-pirqf_routing) {
+ pci_write_config8(dev, PIRQF_ROUT,
config-pirqf_routing);
+ } else {
+ pci_write_config8(dev, PIRQF_ROUT, PIRQF);
+ }
+
+ if (config-pirqg_routing) {
+ pci_write_config8(dev, PIRQG_ROUT,
config-pirqg_routing);
+ } else {
+ pci_write_config8(dev, PIRQG_ROUT, PIRQG);
+ }
+
+ if (config-pirqh_routing) {
+ pci_write_config8(dev, PIRQH_ROUT,
config-pirqh_routing);
+ } else {
+ pci_write_config8(dev, PIRQH_ROUT, PIRQH);
+ }
}
}
--
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Re: [coreboot] [PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
On Sat, 2 May 2009 13:39:53 -0700, ron minnich rminn...@gmail.com wrote: Very nice. Acked-by: Ronald G. Minnich rminn...@gmail.com Thanks r4251 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] fix the XIP size and fallback computations for M2V-MX SE
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello,
It seems I'm quite tired to formulate the description of the patch accurately I
hope it is understandable somehow.
Following patch fixes the XIP computation issue. I removed the normal image
because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)
This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.
Third reason is that now it makes 384KB for additional ROMs and payload - plenty
of space for CBFS fun ;)
Now it uses generic _ROMBASE etc computation which is nice too.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAkn8wQgACgkQ3J9wPJqZRNUftgCfXjuQUkJwksgI4VU81mdJ78Kh
PyMAoMMWXjUKmq5YVQhsWZ6iFMEdgTSu
=mtSc
-END PGP SIGNATURE-
Index: src/mainboard/asus/m2v-mx_se/Config.lb
===
--- src/mainboard/asus/m2v-mx_se/Config.lb (revision 4250)
+++ src/mainboard/asus/m2v-mx_se/Config.lb (working copy)
@@ -20,24 +20,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
+include /config/nofailovercalculation128.lb
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0x - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-##WARNING enable caching of whole ROM during CAR
-##for 512KB flash
-default XIP_ROM_SIZE = 0x8
-default XIP_ROM_BASE = 0x + 1 - XIP_ROM_SIZE
-
arch i386 end
driver mainboard.o
Index: src/mainboard/asus/m2v-mx_se/Options.lb
===
--- src/mainboard/asus/m2v-mx_se/Options.lb (revision 4250)
+++ src/mainboard/asus/m2v-mx_se/Options.lb (working copy)
@@ -96,8 +96,6 @@
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_USE_PRINTK_IN_CAR
-default ROM_SIZE = 512 * 1024
-default FALLBACK_SIZE = 256 * 1024
default HAVE_FALLBACK_BOOT = 1
default HAVE_HARD_RESET = 1
default HAVE_PIRQ_TABLE = 0
@@ -153,7 +151,6 @@
default MAINBOARD_PART_NUMBER = M2V-MX SE
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
-default ROM_IMAGE_SIZE = 64 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
Index: src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===
--- src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (revision 4250)
+++ src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (working copy)
@@ -162,64 +162,10 @@
}
-#if USE_FALLBACK_IMAGE == 1
-
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- /* unsigned last_boot_normal_x = last_boot_normal(); */
- /* FIXME */
- unsigned last_boot_normal_x = 1;
-
- sio_init();
- it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
- it8712f_kill_watchdog();
- uart_init();
- console_init();
- enable_rom_decode();
-
- print_info(now booting... fallback\r\n);
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_x)
- goto normal_image;
- else
- goto fallback_image;
- }
-
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
-
- /* Is this a deliberate reset by the BIOS? */
- if (bios_reset_detected() last_boot_normal_x) {
- goto normal_image;
- }
- /* This is the primary CPU, how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
-
-normal_image:
- /* print_info(JMP normal image\r\n); */
-
- __asm__ __volatile__(jmp __normal_image:
- :a (bist), b (cpu_init_detectedx));
-
-fallback_image:
- ;
-}
-#endif
-
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
-#endif
real_main(bist, cpu_init_detectedx);
}
Index: targets/asus/m2v-mx_se/Config.lb
===
--- targets/asus/m2v-mx_se/Config.lb (revision 4249)
+++ targets/asus/m2v-mx_se/Config.lb (working copy)
@@ -20,19 +20,35 @@
target asus_m2v-mx_se
mainboard asus/m2v-mx_se
-romimage
Re: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote: It does look like an SMP machine in which both CPUs are trying to run as the BSP. Possible? It's definitely an SMP machine, two dual-core CPUs. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] LinuxTag 2009 in Berlin, June 24-27
On 01.05.2009 13:26, Joseph Smith wrote: (Or my top hat flash for these boards if that works out.) What is this? http://www.coreboot.org/Top_Hat_Flash I hope to build something similar for M2A-VM boards. The pinout and my multimeter measurements certainly look favourable. Ah yes. A generic top hat flash PCB with two or three jumpers would probably handle almost every soldered LPC/FWH chip out there. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege w...@gnu.org wrote: On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote: It does look like an SMP machine in which both CPUs are trying to run as the BSP. Possible? It's definitely an SMP machine, two dual-core CPUs. So can you see what changed in the k8 north/cpu support since the last time it worked? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] r4233/4234 broke h8dme (serial corruption + hang)
On Sat, May 02, 2009 at 04:38:12PM -0700, ron minnich wrote:
On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege w...@gnu.org wrote:
On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wrote:
It does look like an SMP machine in which both CPUs are trying to run
as the BSP.
Possible?
It's definitely an SMP machine, two dual-core CPUs.
So can you see what changed in the k8 north/cpu support since the last
time it worked?
Sure. The last time it worked is r4232, I had to bisect to find the commit
causing the problem. r4233/4234 are one changeset.
src/northbridge/amd is unchanged by this changeset.
The diff for src/cpu/amd is attached.
Thanks,
Ward.
--
Ward Vandewege w...@fsf.org
Free Software Foundation - Senior Systems Administrator
Index: car/copy_and_run.c
===
--- car/copy_and_run.c (revision 4232)
+++ car/copy_and_run.c (revision 4234)
@@ -2,119 +2,36 @@
moved from nrv2v.c and some lines from crt0.S
2006/05/02 - stepan: move nrv2b to an extra file.
*/
-static inline void print_debug_cp_run(const char *strval, uint32_t val)
-{
-#if CONFIG_USE_PRINTK_IN_CAR
-printk_debug(%s%08x\r\n, strval, val);
-#else
-print_debug(strval); print_debug_hex32(val); print_debug(\r\n);
-#endif
-}
-#if CONFIG_COMPRESS
-#define ENDIAN 0
-#define BITSIZE 32
-#include lib/nrv2b.c
-#endif
+void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
+extern u8 _liseg, _iseg, _eiseg;
static void copy_and_run(void)
{
uint8_t *src, *dst;
-unsigned long ilen, olen;
+unsigned long ilen;
+ src = _liseg;
+ dst = _iseg;
+ ilen = _eiseg - dst;
-#if !CONFIG_COMPRESS
- print_debug(Copying coreboot to RAM.\r\n);
- __asm__ volatile (
- leal _liseg, %0\n\t
- leal _iseg, %1\n\t
- leal _eiseg, %2\n\t
- subl %1, %2\n\t
- : =a (src), =b (dst), =c (olen)
- );
- memcpy(dst, src, olen);
-#else
- print_debug(Uncompressing coreboot to RAM.\r\n);
-
-__asm__ volatile (
- leal _liseg, %0\n\t
- leal _iseg, %1\n\t
-: =a (src) , =b (dst)
-);
-
- print_debug_cp_run(src=,(uint32_t)src);
- print_debug_cp_run(dst=,(uint32_t)dst);
-
-// dump_mem(src, src+0x100);
-
- olen = unrv2b(src, dst, ilen);
- print_debug_cp_run(coreboot_ram.nrv2b length = , ilen);
-
-#endif
-// dump_mem(dst, dst+0x100);
-
- print_debug_cp_run(coreboot_ram.bin length = , olen);
-
- print_debug(Jumping to coreboot.\r\n);
-
-__asm__ volatile (
-xorl %ebp, %ebp\n\t /* cpu_reset for hardwaremain dummy */
- cli\n\t
- leal_iseg, %edi\n\t
- jmp *%edi\n\t
- );
-
+ copy_and_run_core(src, dst, ilen, 0);
}
#if CONFIG_AP_CODE_IN_CAR == 1
+extern u8 _liseg_apc, _iseg_apc, _eiseg_apc;
+
static void copy_and_run_ap_code_in_car(unsigned ret_addr)
{
uint8_t *src, *dst;
-unsigned long ilen, olen;
+unsigned long ilen;
-//print_debug(Copying coreboot AP code to CAR.\r\n);
+ src = _liseg_apc;
+ dst = _iseg_apc;
+ ilen = _eiseg_apc - dst;
-#if !CONFIG_COMPRESS
-__asm__ volatile (
-leal _liseg_apc, %0\n\t
-leal _iseg_apc, %1\n\t
-leal _eiseg_apc, %2\n\t
-subl %1, %2\n\t
-: =a (src), =b (dst), =c (olen)
-);
-memcpy(dst, src, olen);
-#else
-
-__asm__ volatile (
-leal _liseg_apc, %0\n\t
-leal _iseg_apc, %1\n\t
-: =a (src) , =b (dst)
-);
-
-//print_debug_cp_run(src=,(uint32_t)src);
-//print_debug_cp_run(dst=,(uint32_t)dst);
-
-// dump_mem(src, src+0x100);
-
-olen = unrv2b(src, dst, ilen);
-//print_debug_cp_run(coreboot_apc.nrv2b length = , ilen);
-
-#endif
-// dump_mem(dst, dst+0x100);
-
-//print_debug_cp_run(coreboot_apc.bin length = , olen);
-
-//print_debug(Jumping to coreboot AP code in CAR.\r\n);
-
-__asm__ volatile (
-movl %0, %%ebp\n\t /* cpu_reset for hardwaremain dummy */
-cli\n\t
-leal_iseg_apc, %%edi\n\t
-jmp *%%edi\n\t
- :: a(ret_addr)
-);
-
+ copy_and_run_core(src, dst, ilen, ret_addr);
}
#endif
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
