Re: Instruction scheduling question

[Steve Ellcey]

On Sat, 2013-06-15 at 00:06 +0200, Eric Botcazou wrote:
> > The part of the scheduling change that I am interested in is the change in
> > where the addiu instruction occurs and the related changes from the positive
> > offsets to the negative offsets.  Can anyone tell me where the code that
> > decides to do that is?  Extra bonus points for any answer not including the
> > word 'reload'.
> 
> Very likely in sched-deps.c:find_modifiable_mems and related functions.

That looks like the right place.  It seems to be triggered by the
DONT_BREAK_DEPENDENCIES flag in the haifa scheduler.  As an experiment,
I added DONT_BREAK_DEPENDENCIES to the scheduling flags and it no longer
did that transformation.

Thanks.

Steve Ellcey
sell...@mips.com

Re: Instruction scheduling question

[Eric Botcazou]

> The part of the scheduling change that I am interested in is the change in
> where the addiu instruction occurs and the related changes from the positive
> offsets to the negative offsets.  Can anyone tell me where the code that
> decides to do that is?  Extra bonus points for any answer not including the
> word 'reload'.

Very likely in sched-deps.c:find_modifiable_mems and related functions.

-- 
Eric Botcazou

Instruction scheduling question

[Steve Ellcey]

I have an instruction scheduling question I was hoping someone could help me
with.  Specifically, I am trying to figure out where and how GCC is deciding
to move the add of a constant to a register above the use of that register and
then changing the register usage by change the offsets associated with it.

For example, I am compiling the following memcpy code for MIPS:

void *memcpy_word_ptr(int * __restrict d, int * __restrict s, unsigned int n )
{
  int i;
  for(i=0; i