RE: [PATCH, rs6000] Fix PR83789: __builtin_altivec_lvx fails for powerpc for altivec-4.c
Hi, Just to update from my side, this patch fixes the issues I had reported in PR83789 and there are no new regression in my testing. Best Regards, Kaushik M. Phatak -Original Message- From: Segher Boessenkool [mailto:seg...@kernel.crashing.org] Sent: Tuesday, March 13, 2018 12:25 AM To: Peter Bergner Cc: GCC Patches ; Kaushik Phatak ; Bill Schmidt Subject: Re: [PATCH, rs6000] Fix PR83789: __builtin_altivec_lvx fails for powerpc for altivec-4.c Hi! On Sun, Mar 11, 2018 at 10:23:02AM -0500, Peter Bergner wrote: > PR83789 shows a problem in the builtin expansion code not calling the There is no hurry I think? And some changes are needed, so I'll leave it to you. The patch is fine with those trivialities fixed. Okay for trunk. Thanks! Enjoy your vacation! Segher
RE: [PATCH PR83789] Fix for Altivec builtin failure
Hi, Thanks for your quick reply. >> I think you should use altivec_lvx_v4si_2op_si instead? I will look into this. I had used v4si_internal as this was generated in older versions (> And the same needs to be done for v8hi, v16qi, v4sf, maybe more? I did observe some other testcase failures for 32-bit, I will look at these instructions as well. Best Regards, Kaushik M. Phatak
[PATCH PR83789] Fix for Altivec builtin failure
Hi, Please find below a patch to fix PR83789. The altivec builtin '__builtin_altivec_lvx' fails for the 32-bit powerpc-linux target. This is observed in gcc-7 onwards and does not affect powerpc64-linux target. This is regression tested for powerpc-linux. Please let me know if this patch is OK. Regards, Kaushik M Phatak 2018-02-01 Kaushik Phatak PR target/83789 * config/rs6000/rs6000.c (altivec_expand_builtin): Provide support for 32-bit target for altivec builtin. Index: gcc/config/rs6000/rs6000.c === --- gcc/config/rs6000/rs6000.c (revision 256400) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -15799,8 +15799,10 @@ exp, target, false); case ALTIVEC_BUILTIN_LVX: case ALTIVEC_BUILTIN_LVX_V4SI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op, - exp, target, false); + return altivec_expand_lv_builtin (((TARGET_64BIT) +? CODE_FOR_altivec_lvx_v4si_2op +: CODE_FOR_altivec_lvx_v4si_internal), + exp, target, false); case ALTIVEC_BUILTIN_LVX_V8HI: return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op, exp, target, false);
RE: [PATCH : RL78] Disable interrupts during hardware multiplication routines
Hi Nick, I have modified and updated this patch as per your comments. Apologies, as it has taken me awhile for me to get back to this. https://gcc.gnu.org/ml/gcc-patches/2016-01/msg00702.html >> +/* Structure for G13 MDUC registers. */ struct mduc_reg_type { >> + unsigned int address; >> + enum machine_mode mode; >> + bool is_volatile; >> +struct mduc_reg_type mduc_regs[NUM_OF_MDUC_REGS] = >> + {{0xf00e8, QImode, true}, > If the is_volatile field is true for all members of this array, why bother > having it at all ? I have got rid of the unnecessary volatile field here. >> +check_mduc_usage () >Add a void type to the declaration. Done. > You should have a blank line between the end of the variable > declarations and the start of the code. Done. >> > + if (get_attr_is_g13_muldiv_insn (insn) == IS_G13_MULDIV_INSN_YES) > I am not sure - but it might be safer to check INSN_P(insn) first Added an INSN_P check here. >> > +if (mduc_regs[i].mode == QImode) >> +{ > Indentation. Hopefully this is fixed. Some issue in editor when moving from tabs to spaces. >> + emit_insn (gen_movqi (gen_rtx_REG (HImode, AX_REG), mem_mduc)); >> +} >In the else case you are using gen_movqi to move an HImode value... >Also you could simplify the above code like this: Fixed this, also used a simpler logic as suggested. >> > +fs = fs + NUM_OF_MDUC_REGS * 2; >> if (fs > 254 * 3) > No - this is wrong. "fs" is the amount of extra space needed in the Sorry, I think I misread this. I have added code at top or prologue which will update cfun->machine->framesize. >> +#define NUM_OF_MDUC_REGS 6 > Why define this here ? It is only ever used in rl78,c and it can be > computed automatically by applying the ARRAY_SIZE macro I have removed this marco and used ARRAY_SIZE to compute the size instead. >> +msave-mduc-in-interrupts >> +Target Mask(SAVE_MDUC_REGISTERS) >> +Stores the MDUC registers in interrupt handlers for G13 target. >> >> +mno-save-mduc-in-interrupts >> +Target RejectNegative Mask(NO_SAVE_MDUC_REGISTERS) >> +Does not save the MDUC registers in interrupt handlers for G13 target. >This looks wrong. Surely you only need the msave-mduc-in-interrupts >definition. That will automatically allow -mno-save-mduc-in-interrupts, >since it does not have the RejectNegative attribute. Also these is no >need to have two separate target mask bits. Just SAVE_MDUC_REGISTERS >will do. Well, the earlier idea was to save the MDUC registers by default for G13 targets. Hence the '-mno-' was introduced, but I can go with your suggestion if it reduces any confusion. >> +++ gcc/doc/invoke.texi(working copy) > You should also add the name of the new option to the Machine Dependent Added the new option to the list. >> +@item -msave-mduc-in-interrupts >Still not quite right. The last sentence should be: > The MDUC registers will only be saved Update the last line of the manual as per your suggestion. >> My review comment is still outstanding. - from Mike Stump The current RL78 ABI does not contain specific information about these registers from the G13 variant of the RL78 target. We can try and request Renesas to add information about the same along with the option required for this. Nick, do you have any thoughts on this? (assuming this version of patch is closer to acceptance) The patch is regression tested for "-msim -mg13 -msave-mduc-in-interrupts". Best Regards, Kaushik gcc/ChangeLog 2016-05-04 Kaushik Phatak * config/rl78/rl78.c (rl78_expand_prologue): Save the MDUC related registers in all interrupt handlers if necessary. (rl78_option_override): Add warning. (MUST_SAVE_MDUC_REGISTERS): New macro. (rl78_expand_epilogue): Restore the MDUC registers if necessary. * config/rl78/rl78.c (check_mduc_usage): New function. * config/rl78/rl78.c (mduc_regs): New structure to hold MDUC register data. * config/rl78/rl78.md (is_g13_muldiv_insn): New attribute. * config/rl78/rl78.md (mulsi3_g13): Add is_g13_muldiv_insn attribute. * config/rl78/rl78.md (udivmodsi4_g13): Add is_g13_muldiv_insn attribute. * config/rl78/rl78.md (mulhi3_g13): Add is_g13_muldiv_insn attribute. * config/rl78/rl78.opt (msave-mduc-in-interrupts): New option. * doc/invoke.texi (RL78 Options): Add -msave-mduc-in-interrupts. Index: gcc/config/rl78/rl78.c === --- gcc/config/rl78/rl78.c (revision 235865) +++ gcc/config/rl78/rl78.c (working copy) @@ -76,6 +76,21 @@ "sp", "ap", "psw", "es", "cs" }; +/* Structure for G13 MDUC registers. */ +struc
[PATCH: RL78] Optimize libgcc routines using clrw and clrb
Hi, Please find below a patch that optimizes libgcc routines for the RL78 target. This is similar to my earlier patch submitted here, https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00415.html The patch optimizes the loading of immediate value in the case of 0x00, by using the clrw or clrb instruction. The patch replaces movw/mov instruction with the smaller clrw/clrb instruction. The clrw and clrb generates only 1 byte of opcode as compared to 3 or 2 bytes for movw and mov. Kindly review this patch and let me know what you think. This is regression tested for rl78 -msim. Best Regards, Kaushik p.s. Kindly ignore any disclaimers at end of this e-mail as they are auto-inserted. Apologies for the same. 2016-04-06 Kaushik Phatak * config/rl78/bit-count.S: Use clrw/clrb where possible. * config/rl78/cmpsi2.S: Likewise. * config/rl78/divmodhi.S Likewise. * config/rl78/divmodsi.S Likewise. * config/rl78/fpbit-sf.S Likewise. * config/rl78/fpmath-sf.S Likewise. * config/rl78/mulsi3.S Likewise. Index: libgcc/config/rl78/bit-count.S === --- libgcc/config/rl78/bit-count.S (revision 3174) +++ libgcc/config/rl78/bit-count.S (working copy) @@ -139,7 +139,7 @@ xor1cy, a.5 xor1cy, a.6 xor1cy, a.7 - movwax, #0 + clrwax bnc $1f incwax 1: @@ -190,7 +190,7 @@ movwax, sp addwax, #4 movwhl, ax - mov a, #0 + clrba 1: xch a, b mov a, [hl] @@ -207,7 +207,7 @@ bnz $1b mov x, a - mov a, #0 + clrba movwr8, ax ret END_FUNC ___popcountqi_internal Index: libgcc/config/rl78/cmpsi2.S === --- libgcc/config/rl78/cmpsi2.S (revision 3174) +++ libgcc/config/rl78/cmpsi2.S (working copy) @@ -162,8 +162,8 @@ ;; They differ. Subtract *S2 from *S1 and return as the result. mov x, a - mov a, #0 - mov r9, #0 + clrba + clrbr9 subwax, r8 1: movwr8, ax Index: libgcc/config/rl78/divmodhi.S === --- libgcc/config/rl78/divmodhi.S (revision 3174) +++ libgcc/config/rl78/divmodhi.S (working copy) @@ -576,7 +576,7 @@ .macro NEG_AX movwhl, ax - movwax, #0 + clrwax subwax, [hl] movw[hl], ax .endm Index: libgcc/config/rl78/divmodsi.S === --- libgcc/config/rl78/divmodsi.S (revision 3174) +++ libgcc/config/rl78/divmodsi.S (working copy) @@ -952,10 +952,10 @@ .macro NEG_AX movwhl, ax - movwax, #0 + clrwax subwax, [hl] movw[hl], ax - movwax, #0 + clrwax sknc decwax subwax, [hl+2] Index: libgcc/config/rl78/fpbit-sf.S === --- libgcc/config/rl78/fpbit-sf.S (revision 3174) +++ libgcc/config/rl78/fpbit-sf.S (working copy) @@ -117,7 +117,7 @@ call$!__int_iszero bnz $2f ;; At this point, both args are zero. - mov a, #0 + clrba ret 2: @@ -151,7 +151,7 @@ bc $ybig_cmpsf ; branch if X < Y bnz $xbig_cmpsf ; branch if X > Y - mov a, #0 + clrba ret xbig_cmpsf:; |X| > |Y| so return A = 1 if pos, 0xff if neg @@ -285,7 +285,7 @@ movwr10, #0x7fff ret ;; -inf -2: mov r8, #0 +2: clrbr8 mov r10, #0x8000 ret @@ -302,10 +302,10 @@ clr1a.7 call$!__int_fixunssfsi - movwax, #0 + clrwax subwax, r8 movwr8, ax - movwax, #0 + clrwax sknc decwax subwax, r10 @@ -410,7 +410,7 @@ set1a.7 ;; Clear B:C:R12:R13 - movwbc, #0 + clrwbc movwr12, #0 ;; Shift bits from the mantissa (A:X:R10) into (B:C:R12:R13), @@ -482,10 +482,10 @@ ;; If negative convert to positive ... movwhl, ax - movwax, #0 + clrwax subwax, bc movwbc, ax - movwax, #0 + clrwax sknc decwax subwax, hl @@ -533,7 +533,7 @@ bnz $1f movwax, bc cmpwax, #0 - movwax, #0 + clrwax bnz $1f ;; Return 0.0 Index: libgcc/config/rl78/fpmath-sf.S === --- libgcc/config/rl78/fp
RE: [PING PATCH: RL78] Optimize libgcc routines using clrw and clrb
Hi Nick, Please let me know if you have had a chance to look at the following patch, https://gcc.gnu.org/ml/gcc-patches/2016-02/msg00415.html Best Regards, Kaushik -Original Message- From: Kaushik Phatak Sent: Friday, February 05, 2016 6:26 PM To: 'gcc-patches@gcc.gnu.org' Cc: nick clifton (ni...@redhat.com) Subject: [PATCH: RL78] Optimize libgcc routines using clrw and clrb Hi, Please find below a simple patch which optimizes the loading of immediate value by using the clrw or clrb instruction in case a 0x00 is being loaded into the register. The patch replaces movw/mov instruction with the smaller clrw/clrb instruction. The clrw and clrb generates only 1 byte of opcode as compared to 3 or 2 bytes for movw and mov. There is a total of about 94 bytes code size improvement with this patch in these libgcc routines.
[PATCH: RL78] Optimize libgcc routines using clrw and clrb
Hi, Please find below a simple patch which optimizes the loading of immediate value by using the clrw or clrb instruction in case a 0x00 is being loaded into the register. The patch replaces movw/mov instruction with the smaller clrw/clrb instruction. The clrw and clrb generates only 1 byte of opcode as compared to 3 or 2 bytes for movw and mov. There is a total of about 94 bytes code size improvement with this patch in these libgcc routines. The following routines have improved code size, ___mulsi3 : 2 bytes ___divsi3 : 20 bytes ___modsi3 : 20 bytes ___divhi3 : 10 bytes ___modhi3 : 10 bytes ___parityqi_internal : 2 bytes __int_cmpsf : 2 bytes ___fixsfsi : 5 bytes ___fixunssfsi : 2 bytes ___floatsisf : 6 bytes _int_unpack_sf : 1 bytes ___addsf3 : 5 bytes __rl78_int_pack_a_r8 : 2 bytes ___mulsf3 : 2 bytes ___divsf3 : 3 bytes __gcc_bcmp : 2 bytes I have also attached a draft version of a similar patch (rl78_libgcc_optimize_draft.patch), which goes further and removes movw immediate to other saddr registers and replaces them with 2 instructions, i.e. START_FUNC ___modhi3 ;; r8 = 4[sp] % 6[sp] - movwde, #0 + clrwax + movwde,ax mov a, [sp+5] This patch improves code size by 1 byte for each such substitution, however does add an extra clock cycle. We may consider this patch in case we are purely looking for code size improvement, assuming the libraries are built with -Os. This shows a total of 134 bytes improvement in code size. Patch1: rl78_libgcc_optimize_clrw.patch - 94 bytes improvement in code size. Patch2: rl78_libgcc_optimize_draft.patch - 134 bytes improvement in code size. Kindly review this patch and let me know what you think. This is regression tested for rl78 -msim. Best Regards, Kaushik p.s. Kindly ignore any disclaimers at end of this e-mail as they are auto-inserted. Apologies for the same. 2016-02-05 Kaushik Phatak * config/rl78/bit-count.S: Use clrw/clrb where possible. * config/rl78/cmpsi2.S: Likewise. * config/rl78/divmodhi.S Likewise. * config/rl78/divmodsi.S Likewise. * config/rl78/fpbit-sf.S Likewise. * config/rl78/fpmath-sf.S Likewise. * config/rl78/mulsi3.S Likewise. Index: libgcc/config/rl78/bit-count.S === --- libgcc/config/rl78/bit-count.S (revision 3174) +++ libgcc/config/rl78/bit-count.S (working copy) @@ -139,7 +139,7 @@ xor1cy, a.5 xor1cy, a.6 xor1cy, a.7 - movwax, #0 + clrwax bnc $1f incwax 1: @@ -190,7 +190,7 @@ movwax, sp addwax, #4 movwhl, ax - mov a, #0 + clrba 1: xch a, b mov a, [hl] @@ -207,7 +207,7 @@ bnz $1b mov x, a - mov a, #0 + clrba movwr8, ax ret END_FUNC ___popcountqi_internal Index: libgcc/config/rl78/cmpsi2.S === --- libgcc/config/rl78/cmpsi2.S (revision 3174) +++ libgcc/config/rl78/cmpsi2.S (working copy) @@ -162,8 +162,8 @@ ;; They differ. Subtract *S2 from *S1 and return as the result. mov x, a - mov a, #0 - mov r9, #0 + clrba + clrbr9 subwax, r8 1: movwr8, ax Index: libgcc/config/rl78/divmodhi.S === --- libgcc/config/rl78/divmodhi.S (revision 3174) +++ libgcc/config/rl78/divmodhi.S (working copy) @@ -576,7 +576,7 @@ .macro NEG_AX movwhl, ax - movwax, #0 + clrwax subwax, [hl] movw[hl], ax .endm Index: libgcc/config/rl78/divmodsi.S === --- libgcc/config/rl78/divmodsi.S (revision 3174) +++ libgcc/config/rl78/divmodsi.S (working copy) @@ -952,10 +952,10 @@ .macro NEG_AX movwhl, ax - movwax, #0 + clrwax subwax, [hl] movw[hl], ax - movwax, #0 + clrwax sknc decwax subwax, [hl+2] Index: libgcc/config/rl78/fpbit-sf.S === --- libgcc/config/rl78/fpbit-sf.S (revision 3174) +++ libgcc/config/rl78/fpbit-sf.S (working copy) @@ -117,7 +117,7 @@ call$!__int_iszero bnz $2f ;; At this point, both args are zero. - mov a, #0 + clrba ret 2: @@ -151,7 +151,7 @@ bc $ybig_cmpsf ; branch if X < Y bnz $xbig_cmpsf ; branch if X > Y - mov a, #0 + clrba ret xbig_cmpsf:; |X| &g
RE: [PATCH : RL78] Disable interrupts during hardware multiplication routines
Hi DJ, Please find attached an updated patch which tries to address the points raised by you in my earlier attempt, https://gcc.gnu.org/ml/gcc-patches/2015-08/msg01729.html 1. Added an option for -msave.. and -mno-save.. The default will be to save the MDUC registers for the g13 target in the ISR. 2. As an optimization, it will check for usage of mul and divmod routines before saving/restoring. 3. I have eliminated the special insns used earlier and directly generating movhi/movqi for the mem reference, also setting them as volatile. 4. Updated and fixed the issue in invoke.texi. This has been regression tested for -mg13 -msim. The only glitch I observed was the list file printed out the address of the MDUC registers in decimal and not in HEX, for example, mov a, !983272 is displayed instead of, mov a, !0xF00E8 However, the objectdump generates these addresses correctly in hex along with their register name references (, etc.) Please let me know if this updated patch is OK. Best Regards, Kaushik gcc/ChangeLog 2015-12-07 Kaushik Phatak * config/rl78/rl78.c (rl78_expand_prologue): Save the MDUC related registers in all interrupt handlers if necessary. (rl78_option_override): Add warning. (MUST_SAVE_MDUC_REGISTER): New macro. (rl78_expand_epilogue): Restore the MDUC registers if necessary. * config/rl78/rl78.c (check_mduc_usage): New function. * config/rl78/rl78.opt (msave-mduc-in-interrupts): New option. (mno-save-mduc-in-interrupts): New option. * doc/invoke.texi (@item -msave-mduc-in-interrupts): New item. (@item -mno-save-mduc-in-interrupts): New item Index: gcc/config/rl78/rl78.c === --- gcc/config/rl78/rl78.c (revision 2871) +++ gcc/config/rl78/rl78.c (working copy) @@ -342,6 +342,10 @@ #undef TARGET_OPTION_OVERRIDE #define TARGET_OPTION_OVERRIDE rl78_option_override +#define MUST_SAVE_MDUC_REGISTER \ + (!TARGET_NO_SAVE_MDUC_REGISTER\ + && (is_interrupt_func (NULL_TREE)) && RL78_MUL_G13) + static void rl78_option_override (void) { @@ -366,6 +370,9 @@ /* Address spaces are currently only supported by C. */ error ("-mes0 can only be used with C"); + if (TARGET_SAVE_MDUC_REGISTER && !(TARGET_G13 || RL78_MUL_G13)) +warning (0, "mduc registers only saved for G13 target"); + switch (rl78_cpu_type) { case CPU_UNINIT: @@ -1307,6 +1314,27 @@ return (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE); } +/* Check if the block uses mul/div insns. */ +int +check_mduc_usage () +{ + rtx insn; + basic_block bb; + FOR_EACH_BB_FN (bb, cfun) + { +FOR_BB_INSNS (bb, insn) +{ + if (recog_memoized (insn) == CODE_FOR_udivmodsi4_g13 + || recog_memoized (insn) == CODE_FOR_mulhi3_g13 + || recog_memoized (insn) == CODE_FOR_mulsi3_g13) +{ + return 1; +} +} + } + return 0; +} + /* Expand the function prologue (from the prologue pattern). */ void rl78_expand_prologue (void) @@ -1318,7 +1346,7 @@ if (rl78_is_naked_func ()) return; - + /* Always re-compute the frame info - the register usage may have changed. */ rl78_compute_frame_info (); @@ -1371,6 +1399,46 @@ F (emit_insn (gen_push (ax))); } + /* Save MDUC register inside interrupt routine. */ + if (MUST_SAVE_MDUC_REGISTER && (!crtl->is_leaf || check_mduc_usage ())) +{ + rtx mem_mduc; + + mem_mduc = gen_rtx_MEM (QImode, GEN_INT (0xf00e8)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movqi (gen_rtx_REG (QImode, A_REG), mem_mduc)); + emit_insn (gen_push (gen_rtx_REG (HImode, AX_REG))); + + mem_mduc = gen_rtx_MEM (HImode, GEN_INT (0x0)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movhi (gen_rtx_REG (HImode, AX_REG), mem_mduc)); + emit_insn (gen_push (gen_rtx_REG (HImode, AX_REG))); + + mem_mduc = gen_rtx_MEM (HImode, GEN_INT (0x2)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movhi (gen_rtx_REG (HImode, AX_REG), mem_mduc)); + emit_insn (gen_push (gen_rtx_REG (HImode, AX_REG))); + + mem_mduc = gen_rtx_MEM (HImode, GEN_INT (0x4)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movhi (gen_rtx_REG (HImode, AX_REG), mem_mduc)); + emit_insn (gen_push (gen_rtx_REG (HImode, AX_REG))); + + mem_mduc = gen_rtx_MEM (HImode, GEN_INT (0x6)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movhi (gen_rtx_REG (HImode, AX_REG), mem_mduc)); + emit_insn (gen_push (gen_rtx_REG (HImode, AX_REG))); + + mem_mduc = gen_rtx_MEM (HImode, GEN_INT (0xf00e0)); + MEM_VOLATILE_P (mem_mduc) = 1; + emit_insn (gen_movhi (gen
RE: [PATCH : RL78] Disable interrupts during hardware multiplication routines
Hi DJ, Thanks for your feedback comments. Sorry it took me a while to get back on this. >> Have you compared the latency of the multiply instructions to the overhead of >> saving those registers in the interrupt handler? >> What about the case where performance is priority, and the developer knows >> that >> the interrupt handlers don't use the multiply registers? >> Also, your code doesn't properly handle the case where the interrupts are >> alread >> disabled when those functions are called. It would re-enable interrupts >> before >> the main code was prepared for it. Yes, I agree the patch does not handle the case where interrupts are disabled. Also, the code performance would suffer when the 'di/ei' instructions are placed inline with the multiplication code. I have worked out an updated patch, which would save the MDUC specific registers in the interrupt routine when the option '-msave-mduc-in-interrupts' is passed. This gets active only for the G13 targets. This patch will save and restore the MDUC specific registers: mduc,mdal/h,mdbl/h and mdcl/h This option does add about 56 bytes of code to the interrupt service routine due to the saves/restores via push/pop. Kindly review this patch and let me know if it would be useful for the RL78 port (either in current state or with modifications) The other option/solution would be for the end user to disable/enable interrupts during the mul/div routines in project as per their requirement. This has been regression tested for ""-mg13 -msim -msave-mduc-in-interrupts" Best Regards, Kaushik gcc/ChangeLog 2015-08-27 Kaushik Phatak * config/rl78/rl78-real.md (movqi_from_mduc,movhi_from_mdal, movhi_from_mdah,movhi_from_mdbl,movhi_from_mdbh,movhi_from_mdcl, movhi_from_mdch,movqi_to_mduc,movhi_to_mdal,movhi_to_mdah, movhi_to_mdbl,movhi_to_mdbh,movhi_to_mdcl,movhi_to_mdch): New patterns. * config/rl78/rl78.c (rl78_expand_prologue): Save the MDUC related register in all interrupt handlers if necessary. (rl78_option_override): Add warning. (MUST_SAVE_MDUC_REGISTER): New macro. (rl78_expand_epilogue): Restore the MDUC registers if necessary. * config/rl78/rl78.opt (msave-mduc-in-interrupts): New option. * doc/invoke.texi (@item -msave-mduc-in-interrupts): New item. Index: gcc/config/rl78/rl78-real.md === --- gcc/config/rl78/rl78-real.md(revision 227024) +++ gcc/config/rl78/rl78-real.md(working copy) @@ -37,6 +37,55 @@ ;;-- Moving +(define_insn "movqi_from_mduc" + [(set (match_operand:QI 0 "register_operand" "=a") + (unspec_volatile:QI [(match_operand:QI 1 "" "")] UNS_BUILTIN_MDUC))] + "" + "mov\t%0, !0xf00e8" +) + +(define_insn "movhi_from_mdal" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand:HI 1 "" "")] UNS_BUILTIN_MDAL))] + "" + "movw\t%0, !0x0" +) + +(define_insn "movhi_from_mdah" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand:HI 1 "" "")] UNS_BUILTIN_MDAH))] + "" + "movw\t%0, !0x2" +) + +(define_insn "movhi_from_mdbl" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand 1)] UNS_BUILTIN_MDBL))] + "" + "movw\t%0, !0x4" +) + +(define_insn "movhi_from_mdbh" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand 1)] UNS_BUILTIN_MDBH))] + "" + "movw\t%0, !0x6" +) + +(define_insn "movhi_from_mdcl" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand 1)] UNS_BUILTIN_MDCL))] + "" + "movw\t%0, !0xf00e0" +) + +(define_insn "movhi_from_mdch" + [(set (match_operand:HI 0 "register_operand" "=A") + (unspec_volatile:HI [(match_operand 1)] UNS_BUILTIN_MDCH))] + "" + "movw\t%0, !0xf00e2" +) + (define_insn "movqi_to_es" [(set (reg:QI ES_REG) (match_operand:QI 0 "register_operand" "a"))] @@ -51,6 +100,62 @@ "mov\t%0, es" ) +(define_insn "movqi_to_mduc" + [(set (reg:QI 0 ) + (unspec_volatile:QI [(match_operand:QI 0)] UNS_BUILTIN_MDUC)) +(match_operand:QI 1 "register_operand" "A")] + "" + "mo
[PATCH: RL78] libgcc fixes for divmodsi, divmodhi and divmodqi
Hi, The following patch fixes issues in the div/mod emulation routines for the RL78 target. Hunk in divmodsi.S: This hunk adds a branch to 'main_loop_done_himode' instead of a direct 'ret'. The 'ret' from here was causing the hardware to crash as the registers were not being restored from stack before return. This happened for long data division by 0. Note: A 'br $!' is used as a only using 'br $' gives error, relocation truncated to fit: R_RL78_DIR8S_PCREL at link time in testcase. This hunk also fixes an issue related to return register. r10,r11 was returned for div instruction instead of r8,r9 register. Hunk in divmodhi.S: Fixes issue related to return register. r10 was returned for div instruction instead of r8 register. Hunk in divmodqi.S: Returns a 0x00 instead of 0xff to keep results consistent with other data types. The hunks in divmodhi and divmodqi are not critical, however the one in divmodsi is critical as the processor runs away to undefined space and crashes. This is regression tested for RL78 -msim. Please let me know if it is OK to commit. Best Regards, Kaushik Changelog: 2015-08-21 Kaushik Phatak * config/rl78/divmodqi.S: Return 0x00 by default for div by 0. * config/rl78/divmodsi.S: Update return register to r8. * config/rl78/divmodhi.S: Update return register to r8,r9. Branch to main_loop_done_himode to pop registers before return. Index: libgcc/config/rl78/divmodhi.S === --- libgcc/config/rl78/divmodhi.S (revision 227024) +++ libgcc/config/rl78/divmodhi.S (working copy) @@ -454,7 +454,11 @@ movwax, den cmpwax, #0 bnz $den_not_zero\which + .if \need_result + movwquot, #0 + .else movwnum, #0 + .endif ret den_not_zero\which: Index: libgcc/config/rl78/divmodqi.S === --- libgcc/config/rl78/divmodqi.S (revision 227024) +++ libgcc/config/rl78/divmodqi.S (working copy) @@ -63,7 +63,7 @@ ret den_is_zero\which: - mov r8, #0xff + mov r8, #0x00 ret ;; These routines leave DE alone - the signed functions use DE Index: libgcc/config/rl78/divmodsi.S === --- libgcc/config/rl78/divmodsi.S (revision 227024) +++ libgcc/config/rl78/divmodsi.S (working copy) @@ -688,9 +688,14 @@ or a, denB3; not x cmpwax, #0 bnz $den_not_zero\which + .if \need_result + movwquotL, #0 + movwquotH, #0 + .else movwnumL, #0 movwnumH, #0 - ret + .endif + br $!main_loop_done_himode\which den_not_zero\which: .if \need_result rl78_divmod.patch Description: rl78_divmod.patch
[PATCH : RL78] Disable interrupts during hardware multiplication routines
Hi, Please find attached a patch which disables interrupts during inline hardware multiplication routines. These routines use up several control registers which are not saved/restored in interrupt routines. This causes corruption of result in case multiplication/division registers are used in main code as well as interrupts. This patch has been regression tested with simulator as well as hardware. Please review the same and let me know if OK to commit? Best Regards, Kaushik Phatak 2015-06-05 Kaushik Phatak * config/rl78/rl78.md (mulhi3_g13): Disable interrupts in routine. (mulsi3_g14): Likewise. (mulsi3_g13): Likewise. (udivmodsi4_g13): Likewise. Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 224145) +++ gcc/config/rl78/rl78.md (working copy) @@ -372,6 +372,7 @@ ] "RL78_MUL_G13" "; G13 mulhi macro %0 = %1 * %2 + di mov a, #0x00 mov !0xf00e8, a ; MDUC movwax, %h1 @@ -381,6 +382,7 @@ nop ; mdb = mdal * mdah movwax, 0x6 ; MDBL movw%h0, ax + ei ; end of mulhi macro" [(set_attr "valloc" "macax")] ) @@ -397,6 +399,7 @@ ] "RL78_MUL_G14" "; G14 mulsi macro %0 = %1 * %2 + di movwax, %h1 movwbc, %h2 MULHU ; bcax = bc * ax @@ -411,6 +414,7 @@ MACHU ; MACR += bc * ax movwax, 0x0 movw%H0, ax + ei ; end of mulsi macro" [(set_attr "valloc" "macax")] ) @@ -429,6 +433,7 @@ ] "RL78_MUL_G13" "; G13 mulsi macro %0 = %1 * %2 + di mov a, #0x00 mov !0xf00e8, a ; MDUC movwax, %h1 @@ -461,6 +466,7 @@ nop ; Additional nop for MAC movwax, !0xf00e0; MDCL movw%H0, ax + ei ; end of mulsi macro" [(set_attr "valloc" "macax")] ) @@ -629,6 +635,7 @@ { if (find_reg_note (insn, REG_UNUSED, operands[3])) return "; G13 udivsi macro %0 = %1 / %2 \n\ + di \n\ mov a, #0xC0; Set DIVMODE=1 and MACMODE=1 \n\ mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\ movwax, %H1 \n\ @@ -647,9 +654,11 @@ movw%h0, ax \n\ movwax, 0x2 \n\ movw%H0, ax \n\ + ei \n\ ; end of udivsi macro"; else if (find_reg_note (insn, REG_UNUSED, operands[0])) return "; G13 umodsi macro %3 = %1 %% %2 \n\ + di \n\ mov a, #0xC0; Set DIVMODE=1 and MACMODE=1 \n\ mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\ movwax, %H1 \n\ @@ -668,9 +677,11 @@ movw%h3, ax \n\ movwax, !0xf00e2\n\ movw%H3, ax \n\ + ei \n\ ; end of umodsi macro"; else return "; G13 udivmodsi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\ + di \n\ mov a, #0xC0; Set DIVMODE=1 and MACMODE=1 \n\ mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\ movwax, %H1 \n\ @@ -693,6 +704,7 @@ movw%h3, ax \n\ movwax, !0xf00e2\n\ movw%H3, ax \n\ + ei \n\ ; end of udivmodsi macro"; } [(set_attr "valloc" "macax")] /* End of Patch */ Best Regards, Kaushik Phatak rl78_mul_div.diff Description: rl78_mul_div.diff
RE: [Patch: RL78] Add support for 64-bit doubles
Hi DJ, >> I assume this should be "doubles" not "double" though... I had made this change as suggested, however we had some issue while integrating the tools with our eclipse plug-ins. The RX toolchain has a similar patch where the option is "doubles" while the folder name is "double". Would it be ok to revert this line from "64-bit-doubles" to "64-bit-double" as this? +MULTILIB_DIRNAMES = g10 64-bit-double https://gcc.gnu.org/ml/gcc-patches/2014-05/msg02350.html Best Regards, Kaushik
RE: [Patch: RL78] Add support for 64-bit doubles
Hi DJ, > This is OK. Thanks! Do you need someone to commit it for you? Thanks, I can commit these changes. >> +MULTILIB_DIRNAMES = g10 64-bit-double > I assume this should be "doubles" not "double" though... Yes, will make that change and commit it. Best Regards, Kaushik
RE: [Patch: RL78] Add support for 64-bit doubles
Hi DJ, Please find below an updated patch which also adds the texi part. My earlier patch which addressed your comments is below, https://gcc.gnu.org/ml/gcc-patches/2014-05/msg01076.html The newlib and binutils part of this patch have been reviewed and committed: https://sourceware.org/ml/newlib/2014/msg00151.html https://sourceware.org/ml/binutils/2014-05/msg00140.html Let me know if below patch is ok to commit (also attached). Thanks, Kaushik 2014-05-26 Kaushik Phatak * config/rl78/rl78.h (TARGET_CPU_CPP_BUILTINS): Define __RL78_64BIT_DOUBLES__ or __RL78_32BIT_DOUBLES__. (ASM_SPEC): Pass -m64bit-doubles or -m32bit-doubles on to the assembler. (DOUBLE_TYPE_SIZE): Use 64 bit if TARGET_64BIT_DOUBLES is true. * gcc/config/rl78/rl78.opt (m64bit-doubles): New option. (m32bit-doubles) Likewise. * gcc/config/rl78/t-rl78: Add 64-bit-double multilib. * doc/invoke.texi: Document -m32bit-doubles and -m64bit-doubles option for RL78. Index: gcc/config/rl78/rl78.h === --- gcc/config/rl78/rl78.h (revision 210920) +++ gcc/config/rl78/rl78.h (working copy) @@ -23,18 +23,22 @@ #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78) #define RL78_MUL_G13 (rl78_mul_type == MUL_G13) -#define TARGET_CPU_CPP_BUILTINS() \ - do\ -{ \ - builtin_define ("__RL78__"); \ - builtin_assert ("cpu=RL78"); \ - if (RL78_MUL_RL78) \ - builtin_define ("__RL78_MUL_RL78__"); \ - if (RL78_MUL_G13)\ - builtin_define ("__RL78_MUL_G13__");\ - if (TARGET_G10) \ - builtin_define ("__RL78_G10__");\ -} \ +#define TARGET_CPU_CPP_BUILTINS() \ + do\ +{ \ + builtin_define ("__RL78__"); \ + builtin_assert ("cpu=RL78"); \ + if (RL78_MUL_RL78) \ + builtin_define ("__RL78_MUL_RL78__"); \ + if (RL78_MUL_G13)\ + builtin_define ("__RL78_MUL_G13__");\ + if (TARGET_G10) \ + builtin_define ("__RL78_G10__");\ + if (TARGET_64BIT_DOUBLES)\ +builtin_define ("__RL78_64BIT_DOUBLES__"); \ + else \ +builtin_define ("__RL78_32BIT_DOUBLES__"); \ +} \ while (0) #undef STARTFILE_SPEC @@ -47,6 +51,8 @@ #define ASM_SPEC "\ %{mrelax:-relax} \ %{mg10} \ +%{m64bit-doubles:-m64bit-doubles} \ +%{!m64bit-doubles:-m32bit-doubles} \ " #undef LINK_SPEC @@ -95,7 +101,7 @@ #define LONG_LONG_TYPE_SIZE64 #define FLOAT_TYPE_SIZE32 -#define DOUBLE_TYPE_SIZE 32 /*64*/ +#define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32) #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/ #define LIBGCC2_HAS_DF_MODE1 Index: gcc/config/rl78/rl78.opt === --- gcc/config/rl78/rl78.opt(revision 210920) +++ gcc/config/rl78/rl78.opt(working copy) @@ -30,6 +30,14 @@ Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_NONE) Select hardware or software multiplication support. +m64bit-doubles +Target RejectNegative Mask(64BIT_DOUBLES) Report +Store doubles in 64 bits. + +m32bit-doubles +Target RejectNegative InverseMask(64BIT_DOUBLES) Report +Stores doubles in 32 bits. This is the default + Enum Name(rl78_mul_types) Type(enum rl78_mul_types) Index: gcc/config/rl78/t-rl78 === --- gcc/config/rl78/t-rl78 (revision 210920) +++ gcc/config/rl78/t-rl78 (working copy) @@ -23,5 +23,5 @@ # Enable multilibs: -MULTILIB_OPTIONS= mg10 -MULTILIB_DIRNAMES = g10 +MULTILIB_OPTIONS= mg10 m64bit-doubles +MULTILIB_DIRNAMES = g10 64-bit-double Index: gcc/doc/invoke.texi === --- gcc/doc/invoke.texi (revision 210920) +++ gcc/doc/invoke.texi (working copy) @@ -873,7 +873,7 @@ See RS/6000 and PowerPC Options. @emph{RL78 Options} -@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78} +@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=rl78 -m64bit-doubles -m32bit-doubles} @emph{RS/6000 and PowerPC Options} @gccoptlist{-mcpu
RE: [Patch: RL78] Add support for 64-bit doubles
Hi DJ, >> "long double" should always be 64 bits, which means that libgcc must >> always have DFmode helpers. Please find below a modified patch which sets the long double to 64 bits. This will use default settings for DFmode and libgcc long double types. I have also posted the binutils part of my patch, https://sourceware.org/ml/binutils/2014-05/msg00117.html I have also posted the newlib part of thei patch, https://sourceware.org/ml/newlib/2014/msg00150.html I have also attached the following patch, to avoid issue with whitespaces being dropped. Let me know if the below version is OK to commit. Thanks, Kaushik 2014-05-14 Kaushik Phatak * config/rl78/rl78.h (TARGET_CPU_CPP_BUILTINS): Define __RL78_64BIT_DOUBLES__ or __RL78_32BIT_DOUBLES__. (ASM_SPEC): Pass -m64bit-doubles or -m32bit-doubles on to the assembler. (DOUBLE_TYPE_SIZE): Use 64 bit if TARGET_64BIT_DOUBLES is true. * gcc/config/rl78/rl78.opt (m64bit-doubles): New option. (m32bit-doubles) Likewise. * gcc/config/rl78/t-rl78: Add 64-bit-double multilib. Index: gcc/config/rl78/rl78.h === --- gcc/config/rl78/rl78.h (revision 210319) +++ gcc/config/rl78/rl78.h (working copy) @@ -23,18 +23,22 @@ #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78) #define RL78_MUL_G13 (rl78_mul_type == MUL_G13) -#define TARGET_CPU_CPP_BUILTINS() \ - do\ -{ \ - builtin_define ("__RL78__"); \ - builtin_assert ("cpu=RL78"); \ - if (RL78_MUL_RL78) \ - builtin_define ("__RL78_MUL_RL78__"); \ - if (RL78_MUL_G13)\ - builtin_define ("__RL78_MUL_G13__");\ - if (TARGET_G10) \ - builtin_define ("__RL78_G10__");\ -} \ +#define TARGET_CPU_CPP_BUILTINS() \ + do\ +{ \ + builtin_define ("__RL78__"); \ + builtin_assert ("cpu=RL78"); \ + if (RL78_MUL_RL78) \ + builtin_define ("__RL78_MUL_RL78__"); \ + if (RL78_MUL_G13)\ + builtin_define ("__RL78_MUL_G13__");\ + if (TARGET_G10) \ + builtin_define ("__RL78_G10__");\ + if (TARGET_64BIT_DOUBLES)\ +builtin_define ("__RL78_64BIT_DOUBLES__"); \ + else \ +builtin_define ("__RL78_32BIT_DOUBLES__"); \ +} \ while (0) #undef STARTFILE_SPEC @@ -47,6 +51,8 @@ #define ASM_SPEC "\ %{mrelax:-relax} \ %{mg10} \ +%{m64bit-doubles:-m64bit-doubles} \ +%{!m64bit-doubles:-m32bit-doubles} \ " #undef LINK_SPEC @@ -95,7 +101,7 @@ #define LONG_LONG_TYPE_SIZE64 #define FLOAT_TYPE_SIZE32 -#define DOUBLE_TYPE_SIZE 32 /*64*/ +#define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32) #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/ #define LIBGCC2_HAS_DF_MODE1 Index: gcc/config/rl78/rl78.opt === --- gcc/config/rl78/rl78.opt(revision 210319) +++ gcc/config/rl78/rl78.opt(working copy) @@ -30,6 +30,14 @@ Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_NONE) Select hardware or software multiplication support. +m64bit-doubles +Target RejectNegative Mask(64BIT_DOUBLES) Report +Store doubles in 64 bits. + +m32bit-doubles +Target RejectNegative InverseMask(64BIT_DOUBLES) Report +Stores doubles in 32 bits. This is the default + Enum Name(rl78_mul_types) Type(enum rl78_mul_types) Index: gcc/config/rl78/t-rl78 === --- gcc/config/rl78/t-rl78 (revision 210319) +++ gcc/config/rl78/t-rl78 (working copy) @@ -23,5 +23,5 @@ # Enable multilibs: -MULTILIB_OPTIONS= mg10 -MULTILIB_DIRNAMES = g10 +MULTILIB_OPTIONS= mg10 m64bit-doubles +MULTILIB_DIRNAMES = g10 64-bit-double rl78_64bit .diff Description: rl78_64bit .diff
RE: [Patch: RL78] Add support for 64-bit doubles
Hi DJ, Thanks for your review earlier. >> It looks OK, it's just the timing is bad. Please remind us after GCC is >> back in stage1. I am reposting this patch with GCC in stage 1. >> I would also like to see an explicit initialization for the variable to >> guarantee that the >> default is 32-bit-doubles, or some other notation that guarantees the >> default. Does the macro ' TARGET_64BIT_DOUBLES ' not guarantee this? 'sizeof' returns length as 4 for doubles for default options and 8 for -m64bit-doubles. Is there any other way to do this explicitly? >> Also, please note in the reminder that you've tested both options and don't >> see any differences in the testsuite results >> between them that reflect bugs in DFmode double support. Just because >> you've enabled the type doesn't mean it >> will work properly. We have regression tested this for -m32bit-doubles, -m64bit-doubles and default -msim options and results look OK. Few additional failures for 64 bit types which were linker errors due to ROM overflow. These were verified manually by adjusting the linker script. Please let me know if any modifications are required. Below patch is identical to one submitted earlier. Regards, Kaushik 2014-05-12 Kaushik Phatak * config/rl78/rl78.h (TARGET_CPU_CPP_BUILTINS): Define __RL78_64BIT_DOUBLES__ or __RL78_32BIT_DOUBLES__. (ASM_SPEC): Pass -m64bit-doubles or -m32bit-doubles on to the assembler. (DOUBLE_TYPE_SIZE): Use 64 bit if TARGET_64BIT_DOUBLES is true. (LIBGCC2_HAS_DF_MODE): Define based on __RL78_32BIT_DOUBLES__. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Use 64 bit is __RL78_64BIT_DOUBLES__ is defined. * gcc/config/rl78/rl78.opt (m64bit-doubles): New option. (m32bit-doubles) Likewise. * gcc/config/rl78/t-rl78: Add 64-bit-double multilib. Index: gcc/config/rl78/rl78.h === --- gcc/config/rl78/rl78.h (revision 210319) +++ gcc/config/rl78/rl78.h (working copy) @@ -23,18 +23,22 @@ #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78) #define RL78_MUL_G13 (rl78_mul_type == MUL_G13) -#define TARGET_CPU_CPP_BUILTINS() \ - do\ -{ \ - builtin_define ("__RL78__"); \ - builtin_assert ("cpu=RL78"); \ - if (RL78_MUL_RL78) \ - builtin_define ("__RL78_MUL_RL78__"); \ - if (RL78_MUL_G13)\ - builtin_define ("__RL78_MUL_G13__");\ - if (TARGET_G10) \ - builtin_define ("__RL78_G10__");\ -} \ +#define TARGET_CPU_CPP_BUILTINS() \ + do\ +{ \ + builtin_define ("__RL78__"); \ + builtin_assert ("cpu=RL78"); \ + if (RL78_MUL_RL78) \ + builtin_define ("__RL78_MUL_RL78__"); \ + if (RL78_MUL_G13)\ + builtin_define ("__RL78_MUL_G13__");\ + if (TARGET_G10) \ + builtin_define ("__RL78_G10__");\ + if (TARGET_64BIT_DOUBLES)\ +builtin_define ("__RL78_64BIT_DOUBLES__"); \ + else \ +builtin_define ("__RL78_32BIT_DOUBLES__"); \ +} \ while (0) #undef STARTFILE_SPEC @@ -47,6 +51,8 @@ #define ASM_SPEC "\ %{mrelax:-relax} \ %{mg10} \ +%{m64bit-doubles:-m64bit-doubles} \ +%{!m64bit-doubles:-m32bit-doubles} \ " #undef LINK_SPEC @@ -95,11 +101,16 @@ #define LONG_LONG_TYPE_SIZE64 #define FLOAT_TYPE_SIZE32 -#define DOUBLE_TYPE_SIZE 32 /*64*/ +#define DOUBLE_TYPE_SIZE(TARGET_64BIT_DOUBLES ? 64 : 32) #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/ -#define LIBGCC2_HAS_DF_MODE1 +#ifdef __RL78_32BIT_DOUBLES__ +#define LIBGCC2_HAS_DF_MODE 0 +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32 +#else +#define LIBGCC2_HAS_DF_MODE 1 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 +#endif #define DEFAULT_SIGNED_CHAR0 Index: gcc/config/rl78/rl78.opt === --- gcc/config/rl78/rl78.opt(revision 210319) +++ gcc/config/rl78/rl78.opt(working copy) @@ -30,6 +30,14 @@ Target RejectNeg
[Patch: RL78] Add support for 64-bit doubles
Hi, Please find below a patch which adds support for 64-bit doubles to the RL78 target. This is largely based on the rx target port and uses similar option and multilibs. I will be posting the binutils and newlib part of this patch shortly. Kindly review the same and let me know if OK to commit. Thanks & Best Regards, Kaushik 2013-03-06 Kaushik Phatak * config/rl78/rl78.h (TARGET_CPU_CPP_BUILTINS): Define __RL78_64BIT_DOUBLES__ or __RL78_32BIT_DOUBLES__. (ASM_SPEC): Pass -m64bit-doubles or -m32bit-doubles on to the assembler. (DOUBLE_TYPE_SIZE): Use 64 bit if TARGET_64BIT_DOUBLES is true. (LIBGCC2_HAS_DF_MODE): Define based on __RL78_32BIT_DOUBLES__. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Use 64 bit is __RL78_64BIT_DOUBLES__ is defined. * gcc/config/rl78/rl78.opt (m64bit-doubles): New option. (m32bit-doubles) Likewise. * gcc/config/rl78/t-rl78: Add 64-bit-double multilib. Index: gcc/config/rl78/rl78.h === --- gcc/config/rl78/rl78.h (revision 208379) +++ gcc/config/rl78/rl78.h (working copy) @@ -23,18 +23,22 @@ #define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78) #define RL78_MUL_G13 (rl78_mul_type == MUL_G13) -#define TARGET_CPU_CPP_BUILTINS() \ - do\ -{ \ - builtin_define ("__RL78__"); \ - builtin_assert ("cpu=RL78"); \ - if (RL78_MUL_RL78) \ - builtin_define ("__RL78_MUL_RL78__"); \ - if (RL78_MUL_G13)\ - builtin_define ("__RL78_MUL_G13__");\ - if (TARGET_G10) \ - builtin_define ("__RL78_G10__");\ -} \ +#define TARGET_CPU_CPP_BUILTINS() \ + do\ +{ \ + builtin_define ("__RL78__"); \ + builtin_assert ("cpu=RL78"); \ + if (RL78_MUL_RL78) \ + builtin_define ("__RL78_MUL_RL78__"); \ + if (RL78_MUL_G13)\ + builtin_define ("__RL78_MUL_G13__");\ + if (TARGET_G10) \ + builtin_define ("__RL78_G10__");\ + if (TARGET_64BIT_DOUBLES)\ +builtin_define ("__RL78_64BIT_DOUBLES__"); \ + else \ +builtin_define ("__RL78_32BIT_DOUBLES__"); \ +} \ while (0) #undef STARTFILE_SPEC @@ -47,6 +51,8 @@ #define ASM_SPEC "\ %{mrelax:-relax} \ %{mg10} \ +%{m64bit-doubles:-m64bit-doubles} \ +%{!m64bit-doubles:-m32bit-doubles} \ " #undef LINK_SPEC @@ -95,11 +101,16 @@ #define LONG_LONG_TYPE_SIZE64 #define FLOAT_TYPE_SIZE32 -#define DOUBLE_TYPE_SIZE 32 /*64*/ +#define DOUBLE_TYPE_SIZE(TARGET_64BIT_DOUBLES ? 64 : 32) #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/ -#define LIBGCC2_HAS_DF_MODE1 +#ifdef __RL78_32BIT_DOUBLES__ +#define LIBGCC2_HAS_DF_MODE 0 +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32 +#else +#define LIBGCC2_HAS_DF_MODE 1 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 +#endif #define DEFAULT_SIGNED_CHAR0 Index: gcc/config/rl78/rl78.opt === --- gcc/config/rl78/rl78.opt(revision 208379) +++ gcc/config/rl78/rl78.opt(working copy) @@ -30,6 +30,14 @@ Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_NONE) Select hardware or software multiplication support. +m64bit-doubles +Target RejectNegative Mask(64BIT_DOUBLES) Report +Store doubles in 64 bits. + +m32bit-doubles +Target RejectNegative InverseMask(64BIT_DOUBLES) Report +Stores doubles in 32 bits. This is the default + Enum Name(rl78_mul_types) Type(enum rl78_mul_types) Index: gcc/config/rl78/t-rl78 === --- gcc/config/rl78/t-rl78 (revision 208379) +++ gcc/config/rl78/t-rl78 (working copy) @@ -23,5 +23,5 @@ # Enable multilibs: -MULTILIB_OPTIONS= mg10 -MULTILIB_DIRNAMES = g10 +MULTILIB_OPTIONS= mg10 m64bit-doubles +MULTILIB_DIRNAMES = g10 64-bit-double
RE: new mul* patterns "U" constraint in rl78
>> +;; [(set_attr "valloc" "umul")] >I think this one needs to be macax also, since the constraints have "v" in >them but the opcodes use ax. > Other than that, it's OK. Committed with above change. Thanks for the quick review. Regards, Kaushik
RE: new mul* patterns "U" constraint in rl78
Hi DJ, > "umul" is used when the insn takes two operands in A and X, and computes a > value into AX. > "macax" is used when the insn pattern itself reads from two virtual registers > and writes to a > virtual register (i.e. V = V op V), but clobbers AX anx BC in the process. Thanks for the clarification. I have updated the patch as below, adding "macax" for *mulhi3_rl78 pattern, while the other 2 use "umul" Let me know if below modified patch is OK to commit. Regards, Kaushik Index: gcc/config/rl78/constraints.md === --- gcc/config/rl78/constraints.md (revision 199949) +++ gcc/config/rl78/constraints.md (working copy) @@ -256,6 +256,19 @@ (match_test "!rl78_far_p (op) && rl78_as_legitimate_address (VOIDmode, XEXP (op, 0), true, ADDR_SPACE_GENERIC)")) ) +(define_memory_constraint "U" + "memory references valid with mov to/from a/ax" + (and (match_code "mem") + (match_test "rl78_virt_insns_ok () +|| satisfies_constraint_Wab (op) +|| satisfies_constraint_Wbc (op) +|| satisfies_constraint_Wde (op) +|| satisfies_constraint_Wd2 (op) +|| satisfies_constraint_Whl (op) +|| satisfies_constraint_Wh1 (op) +|| satisfies_constraint_Whb (op) +|| satisfies_constraint_Ws1 (op) +|| satisfies_constraint_Wfr (op) "))) (define_memory_constraint "Qbi" "built-in compare types" Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 199949) +++ gcc/config/rl78/rl78.md (working copy) @@ -276,6 +276,7 @@ mova, x mov%h0, a ; end of mulqi macro" +;; [(set_attr "valloc" "umul")] ) (define_insn "*mulhi3_rl78" @@ -290,6 +291,7 @@ mulhu ; bcax = bc * ax movw%h0, ax ; end of mulhi macro" +;; [(set_attr "valloc" "macax")] ) (define_insn "*mulhi3_g13" @@ -309,6 +311,7 @@ movwax, 0x6 ; MDBL movw%h0, ax ; end of mulhi macro" +;; [(set_attr "valloc" "umul")] ) ;; 0x0 is MACR(L). 0x2 is MACR(H) but we don't care about it
RE: new mul* patterns "U" constraint in rl78
Hi DJ, > Uses a "U" constraint. What should that constraint do? Could you post a > patch to add it? The U constraint was part of a source tree we worked on previously. I have provided the patch for it below. I have also set the valloc attribute for the multiplication insns to 'umul'. Would that be the correct setting as 'macax' is used for the other SI multiplication insns which seem to also include accumulation? Please let me know if OK. Thanks & Regards, Kaushik 2013-06-10 Kaushik Phatak * config/rl78/constraints.md (U): New constraint. * config/rl78/rl78.md (mulqi3_rl78,mulhi3_rl78,mulhi3_g13): Add valloc attribute. Index: gcc/config/rl78/constraints.md === --- gcc/config/rl78/constraints.md (revision 199879) +++ gcc/config/rl78/constraints.md (working copy) @@ -256,6 +256,19 @@ (match_test "!rl78_far_p (op) && rl78_as_legitimate_address (VOIDmode, XEXP (op, 0), true, ADDR_SPACE_GENERIC)")) ) +(define_memory_constraint "U" + "memory references valid with mov to/from a/ax" + (and (match_code "mem") + (match_test "rl78_virt_insns_ok () +|| satisfies_constraint_Wab (op) +|| satisfies_constraint_Wbc (op) +|| satisfies_constraint_Wde (op) +|| satisfies_constraint_Wd2 (op) +|| satisfies_constraint_Whl (op) +|| satisfies_constraint_Wh1 (op) +|| satisfies_constraint_Whb (op) +|| satisfies_constraint_Ws1 (op) +|| satisfies_constraint_Wfr (op) "))) (define_memory_constraint "Qbi" "built-in compare types" Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 199879) +++ gcc/config/rl78/rl78.md (working copy) @@ -276,6 +276,7 @@ mova, x mov%h0, a ; end of mulqi macro" + [(set_attr "valloc" "umul")] ) (define_insn "*mulhi3_rl78" @@ -290,6 +291,7 @@ mulhu ; bcax = bc * ax movw%h0, ax ; end of mulhi macro" + [(set_attr "valloc" "umul")] ) (define_insn "*mulhi3_g13" @@ -309,6 +311,7 @@ movwax, 0x6 ; MDBL movw%h0, ax ; end of mulhi macro" + [(set_attr "valloc" "umul")] ) ;; 0x0 is MACR(L). 0x2 is MACR(H) but we don't care about it
RE: [PATCH:RL78] Add new insn for mulqi3 and mulhi3
Ping. Can I commit this with below changes? Thanks, Kaushik -Original Message- From: Kaushik Phatak Sent: 20 May 2013 20:17 To: gcc-patches@gcc.gnu.org Cc: 'Richard Henderson'; DJ Delorie (d...@redhat.com) Subject: RE: [PATCH:RL78] Add new insn for mulqi3 and mulhi3 Hi Richard, Thanks for the quick review. > No constraints on define_expand, only predicates. >> +(define_insn "mulhi3_g13" >These names are not used. They should be prefixed with "*" to indicate the >name is just for documentation. I have made the suggested changes. Please find below an updated version of this patch. Let me know if OK to commit the same. Regards, Kaushik 2013-05-20 Kaushik Phatak * config/rl78/rl78.md (mulqi3,mulhi3): New define_expands. (mulqi3_rl78,mulhi3_rl78,mulhi3_g13): New define_insns. Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 199105) +++ gcc/config/rl78/rl78.md (working copy) @@ -235,6 +235,24 @@ [(set_attr "valloc" "macax")] ) +(define_expand "mulqi3" + [(set (match_operand:QI 0 "register_operand" "") + (mult:QI (match_operand:QI 1 "general_operand" "") + (match_operand:QI 2 "nonmemory_operand" ""))) + ] + "" ; mulu supported by all targets + "" +) + +(define_expand "mulhi3" + [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (match_operand:HI 1 "general_operand" "") +(match_operand:HI 2 "nonmemory_operand" ""))) + ] + "! RL78_MUL_NONE" + "" +) + (define_expand "mulsi3" [(set (match_operand:SI 0 "register_operand" "=&v") (mult:SI (match_operand:SI 1 "nonmemory_operand" "vi") @@ -244,6 +262,55 @@ "" ) +(define_insn "*mulqi3_rl78" + [(set (match_operand:QI 0 "register_operand" "=&v") + (mult:QI (match_operand:QI 1 "general_operand" "+viU") +(match_operand:QI 2 "general_operand" "vi"))) + ] + "" ; mulu supported by all targets + "; mulqi macro %0 = %1 * %2 + mova, %h1 + movx, a + mova, %h2 + mulu x ; ax = a * x + mova, x + mov%h0, a + ; end of mulqi macro" +) + +(define_insn "*mulhi3_rl78" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_RL78" + "; mulhi macro %0 = %1 * %2 + movwax, %h1 + movwbc, %h2 + mulhu ; bcax = bc * ax + movw%h0, ax + ; end of mulhi macro" +) + +(define_insn "*mulhi3_g13" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_G13" + "; mulhi macro %0 = %1 * %2 + mov a, #0x00 + mov !0xf00e8, a ; MDUC + movwax, %h1 + movw0x0, ax ; MDAL + movwax, %h2 + movw0x2, ax ; MDAH + nop ; mdb = mdal * mdah + movwax, 0x6 ; MDBL + movw%h0, ax +; end of mulhi macro" +) + ;; 0x0 is MACR(L). 0x2 is MACR(H) but we don't care about it ;; because we're only using the lower 16 bits (which is the upper 16 ;; bits of the result).
RE: [PATCH:RL78] Add new insn for mulqi3 and mulhi3
Hi Richard, Thanks for the quick review. > No constraints on define_expand, only predicates. >> +(define_insn "mulhi3_g13" >These names are not used. They should be prefixed with "*" to indicate the >name is just for documentation. I have made the suggested changes. Please find below an updated version of this patch. Let me know if OK to commit the same. Regards, Kaushik 2013-05-20 Kaushik Phatak * config/rl78/rl78.md (mulqi3,mulhi3): New define_expands. (mulqi3_rl78,mulhi3_rl78,mulhi3_g13): New define_insns. Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 199105) +++ gcc/config/rl78/rl78.md (working copy) @@ -235,6 +235,24 @@ [(set_attr "valloc" "macax")] ) +(define_expand "mulqi3" + [(set (match_operand:QI 0 "register_operand" "") + (mult:QI (match_operand:QI 1 "general_operand" "") + (match_operand:QI 2 "nonmemory_operand" ""))) + ] + "" ; mulu supported by all targets + "" +) + +(define_expand "mulhi3" + [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (match_operand:HI 1 "general_operand" "") +(match_operand:HI 2 "nonmemory_operand" ""))) + ] + "! RL78_MUL_NONE" + "" +) + (define_expand "mulsi3" [(set (match_operand:SI 0 "register_operand" "=&v") (mult:SI (match_operand:SI 1 "nonmemory_operand" "vi") @@ -244,6 +262,55 @@ "" ) +(define_insn "*mulqi3_rl78" + [(set (match_operand:QI 0 "register_operand" "=&v") + (mult:QI (match_operand:QI 1 "general_operand" "+viU") +(match_operand:QI 2 "general_operand" "vi"))) + ] + "" ; mulu supported by all targets + "; mulqi macro %0 = %1 * %2 + mova, %h1 + movx, a + mova, %h2 + mulu x ; ax = a * x + mova, x + mov%h0, a + ; end of mulqi macro" +) + +(define_insn "*mulhi3_rl78" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_RL78" + "; mulhi macro %0 = %1 * %2 + movwax, %h1 + movwbc, %h2 + mulhu ; bcax = bc * ax + movw%h0, ax + ; end of mulhi macro" +) + +(define_insn "*mulhi3_g13" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_G13" + "; mulhi macro %0 = %1 * %2 + mov a, #0x00 + mov !0xf00e8, a ; MDUC + movwax, %h1 + movw0x0, ax ; MDAL + movwax, %h2 + movw0x2, ax ; MDAH + nop ; mdb = mdal * mdah + movwax, 0x6 ; MDBL + movw%h0, ax +; end of mulhi macro" +) + ;; 0x0 is MACR(L). 0x2 is MACR(H) but we don't care about it ;; because we're only using the lower 16 bits (which is the upper 16 ;; bits of the result).
[PATCH:RL78] Add new insn for mulqi3 and mulhi3
Hi, The below patch adds expanders and insns for QI and HI mode for the RL78 target. The QI mode uses a generic 'mulu' instruction supported by all variants, while the HI mode creates insn for G13 and G14 target variants using hardware multiply instructions. Tested on hardware and simulator with no additional regressions. Kindly review the same. Thanks, Kaushik 2013-05-15 Kaushik Phatak * config/rl78/rl78.md (mulqi3,mulhi3): New define_expands. (mulqi3_rl78,mulhi3_rl78,mulhi3_g13): New define_insns. Index: gcc/config/rl78/rl78.md === --- gcc/config/rl78/rl78.md (revision 198915) +++ gcc/config/rl78/rl78.md (working copy) @@ -235,6 +235,24 @@ [(set_attr "valloc" "macax")] ) +(define_expand "mulqi3" + [(set (match_operand:QI 0 "register_operand" "=&v") + (mult:QI (match_operand:QI 1 "general_operand" "+vim") + (match_operand:QI 2 "nonmemory_operand" "vi"))) + ] + "" ; mulu supported by all targets + "" +) + +(define_expand "mulhi3" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+vim") +(match_operand:HI 2 "nonmemory_operand" "vi"))) + ] + "! RL78_MUL_NONE" + "" +) + (define_expand "mulsi3" [(set (match_operand:SI 0 "register_operand" "=&v") (mult:SI (match_operand:SI 1 "nonmemory_operand" "vi") @@ -244,6 +262,55 @@ "" ) +(define_insn "mulqi3_rl78" + [(set (match_operand:QI 0 "register_operand" "=&v") + (mult:QI (match_operand:QI 1 "general_operand" "+viU") +(match_operand:QI 2 "general_operand" "vi"))) + ] + "" ; mulu supported by all targets + "; mulqi macro %0 = %1 * %2 + mova, %h1 + movx, a + mova, %h2 + mulu x ; ax = a * x + mova, x + mov%h0, a + ; end of mulqi macro" +) + +(define_insn "mulhi3_rl78" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_RL78" + "; mulhi macro %0 = %1 * %2 + movwax, %h1 + movwbc, %h2 + mulhu ; bcax = bc * ax + movw%h0, ax + ; end of mulhi macro" +) + +(define_insn "mulhi3_g13" + [(set (match_operand:HI 0 "register_operand" "=&v") + (mult:HI (match_operand:HI 1 "general_operand" "+viU") +(match_operand:HI 2 "general_operand" "vi"))) + ] + "RL78_MUL_G13" + "; mulhi macro %0 = %1 * %2 + mov a, #0x00 + mov !0xf00e8, a ; MDUC + movwax, %h1 + movw0x0, ax ; MDAL + movwax, %h2 + movw0x2, ax ; MDAH + nop ; mdb = mdal * mdah + movwax, 0x6 ; MDBL + movw%h0, ax +; end of mulhi macro" +) + ;; 0x0 is MACR(L). 0x2 is MACR(H) but we don't care about it ;; because we're only using the lower 16 bits (which is the upper 16 ;; bits of the result).
RE: [Patch:RL78] Fix hardware multiply on G13 target
Hi DJ, Thanks for quick review. >> +nop ; Additional nop for MAC > > >> mov a, #0x40 > Shouldn't the MOV after the nop add the extra cycle here? Yes, this nop is not required. Tested without this and works OK. Please find below an updated patch. Let me know if ok to commit. Regards, Kaushik 2013-05-13 Kaushik Phatak * config/rl78/rl78.md (mulsi3_g13): Add additional 'nop' required in multiply-accumulate mode --- /home/fsfsrc/gcc-4.8.0-20121219/gcc/config/rl78/rl78.md 2013-01-25 16:26:27.0 +0530 +++ /home/new/gcc-4.8.0-20121219/gcc/config/rl78/rl78.md2013-05-13 10:24:19.0 +0530 @@ -389,6 +389,7 @@ movwax, %H2 movw0x2, ax ; MDAH nop ; mdc += mdal * mdah + nop ; Additional nop for MAC movwax, !0xf00e0; MDCL movw%H0, ax ; end of mulsi macro"
[Patch:RL78] Fix hardware multiply on G13 target
Hi, The following patch fixes an issue with the inline hardware multiply used in the RL78 G13 target. The G13 target does not have a multiply instruction, but achieves this using set of data and control registers. This patch adds an additional 'nop' after control and data registers are loaded in the multiply-accumulation operation. Currently, there is only 1 'nop'. As per the data sheet, regular multiply operation: 1 nop multiply-accumulate operation: 2 nops Section 17.4.2 of G13 hardware manual: After <6>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished (<5>).) Note: The multiplication fails on hardware (for certain testcases), but always works as expected using rl78-elf-run simulator. I do not think the simulator has any cycle check for nop's. Please let me know if this is OK to commit. Regards, Kaushik 2013-05-10 Kaushik Phatak * config/rl78/rl78.md (mulsi3_g13): Add additional 'nop' required in multiply-accumulate mode diff -uprN /home/kpit/fsfsrc/gcc-4.8.0-20121219/gcc/config/rl78/rl78.md gcc/config/rl78/rl78.md --- /home/kpit/fsfsrc/gcc-4.8.0-20121219/gcc/config/rl78/rl78.md2013-01-25 16:26:27.0 +0530 +++ gcc/config/rl78/rl78.md 2013-05-10 16:57:26.0 +0530 @@ -381,6 +381,7 @@ movwax, %h2 movw0x2, ax ; MDAH nop ; mdc += mdal * mdah + nop ; Additional nop for MAC mov a, #0x40 mov !0xf00e8, a ; MDUC @@ -389,6 +390,7 @@ movwax, %H2 movw0x2, ax ; MDAH nop ; mdc += mdal * mdah + nop ; Additional nop for MAC movwax, !0xf00e0; MDCL movw%H0, ax ; end of mulsi macro"
RE: [RFA] New port: CR16: BFD Changes required by the gdb port
Hi Pedro, >> - cr16-*-*) >> -noconfigdirs="$noconfigdirs gdb" >> -;; >> Dunno why these were removed with that merge. The >> ChangeLog entries brought in don't seen to mention these changes. Thanks for looking this up. The below patch includes these above entries into configure.ac and configure(regenerated). Not sure if this should be submitted to gcc-patches, adding them in cc. Additionally, I have tried to answer queries related to my gdbserver port here, http://sourceware.org/ml/gdb-patches/2012-12/msg00832.html Let me know if you have any comments on the same. Thanks, Kaushik 2013-01-15 Kaushik Phatak * configure.ac (cr16-*-*): Adding cr16 target. * configure (cr16-*-*): Regenerate. Index: configure === RCS file: /cvs/src/src/configure,v retrieving revision 1.440 diff -u -a -r1.440 configure --- configure 16 Dec 2012 07:10:07 - 1.440 +++ configure 15 Jan 2013 07:30:06 - @@ -3600,6 +3600,9 @@ tic54x-*-*) noconfigdirs="$noconfigdirs target-libgloss gdb" ;; + cr16-*-*) +noconfigdirs="$noconfigdirs target-libgloss" +;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss" ;; Index: configure.ac === RCS file: /cvs/src/src/configure.ac,v retrieving revision 1.184 diff -u -a -r1.184 configure.ac --- configure.ac16 Dec 2012 07:10:07 - 1.184 +++ configure.ac15 Jan 2013 07:30:06 - @@ -939,6 +939,9 @@ tic54x-*-*) noconfigdirs="$noconfigdirs target-libgloss gdb" ;; + cr16-*-*) +noconfigdirs="$noconfigdirs target-libgloss" +;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss" ;;
RE: [RFA 1/5] New port: CR16: Remove "gdb" from noconfigdirs in configure.ac
Hi, Thanks for the feedback. > I can't see how adding target-libgloss is relevant to a gdb port. This was actually a part of some simulator fixes to update nltvals.def as it was not emulating the correct system calls. The Newlib changes have been already checked in and nltvals.def has been regenerated in latest build, so I guess the target-libgloss will not be necessary. > config.sub is maintained elsewhere. Ok, I will send this patch to config-patches at gnu dot org. Regards, Kaushik Updated Patch: - Removed "target-libgloss" - Removed config.sub from this mailing list 2012-10-05 Kaushik Phatak Changelog * configure.ac (noconfigdirs): Remove gdb. * configure: Regenerate. --- ./gdb_src.orig/configure2012-06-28 17:20:52.0 +0530 +++ ./gdb_src/configure 2012-08-17 16:56:10.0 +0530 @@ -3447,7 +3447,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-libgloss gdb" ;; cr16-*-*) -noconfigdirs="$noconfigdirs gdb" +noconfigdirs="$noconfigdirs" ;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss" --- ./gdb_src.orig/configure.ac 2012-08-17 23:07:18.0 +0530 +++ ./gdb_src/configure.ac 2012-08-17 16:56:17.0 +0530 @@ -873,7 +873,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-libgloss gdb" ;; cr16-*-*) -noconfigdirs="$noconfigdirs gdb" +noconfigdirs="$noconfigdirs" ;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss"
[RFA 1/5] New port: CR16: Remove "gdb" from noconfigdirs in configure.ac
Hi, This patch is one of patch set to add a new port (National Instruments CR16) in gdb. This patch will, - Remove "gdb" from noconfigdirs in top-level configure.ac. - Add target-lobgloss - Make target OS independent in config.sub OK for gcc and binutils? Regards, Kaushik 2012-10-04 Kaushik Phatak Changelog * configure.ac (noconfigdirs): Remove gdb. Add target-libgloss. * configure: Regenerate. * config.sub: Make target OS independent --- ./gdb_src.orig/configure2012-06-28 17:20:52.0 +0530 +++ ./gdb_src/configure 2012-08-17 16:56:10.0 +0530 @@ -3447,7 +3447,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-libgloss gdb" ;; cr16-*-*) -noconfigdirs="$noconfigdirs gdb" +noconfigdirs="$noconfigdirs target-libgloss" ;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss" --- ./gdb_src.orig/configure.ac 2012-08-17 23:07:18.0 +0530 +++ ./gdb_src/configure.ac 2012-08-17 16:56:17.0 +0530 @@ -873,7 +873,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-libgloss gdb" ;; cr16-*-*) -noconfigdirs="$noconfigdirs gdb" +noconfigdirs="$noconfigdirs target-libgloss" ;; d10v-*-*) noconfigdirs="$noconfigdirs target-libgloss" --- ./gdb_src.orig/config.sub 2012-04-25 21:23:25.0 +0530 +++ ./gdb_src/config.sub2012-09-24 11:26:00.0 +0530 @@ -575,7 +575,6 @@ case $basic_machine in ;; cr16 | cr16-*) basic_machine=cr16-unknown - os=-elf ;; crds | unos) basic_machine=m68k-crds
RE: [Patch : H8300] Bug fix for bit insn and minor tweaks to insns
Hi Jeff, Thanks for the quick review. >> the right test is rtx_equal_p(operands[0], operands[1]) Committed with above changes to the bsetqi_msx, bclrqi_msx and bnotqi_msx patterns. Thanks & Regards, Kaushik Phatak www.kpitgnutools.com -Original Message- From: Jeff Law [mailto:l...@redhat.com] Sent: 11 June 2011 00:01 To: Kaushik Phatak Cc: gcc-patches@gcc.gnu.org; Prafulla Thakare Subject: Re: [Patch : H8300] Bug fix for bit insn and minor tweaks to insns -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/09/11 01:20, Kaushik Phatak wrote: > Hi, > The following patch fixes an ICE that is generated when the compiler tries > to perform bit manipulation for logical operations when the source and > destination address does not match. The testcase is also included in the > patch(gcc.dg). > The additional condition in the insn takes care of the ICE which occurs at > '-O1'. > The other insn's are reordered to give preference to bit instructions using > existing > constraints. > Ok to apply? > > Thanks & Regards, > Kaushik Phatak > www.kpitgnutools.com > > 2011-06-09 Kaushik Phatak > > * config/h8300/h8300.md (bsetqi_msx, bclrqi_msx, bnotqi_msx): Added > condition to disallow non-identical memory locations. > (*andqi3_2, andqi3_1, iorqi3_1, xorqi3_1): Reorder insn to give > preference to bit manipulation instructions. > * gcc.dg/h8300-bit-insn-ice2.2: New testcase. Can't the operand be MEM (reg) or MEM (const_int)? In which case INTVAL (XEXP (operands[], 0)) is the wrong test since you shouldn't be applying INTVAL to a REG. Furthermore, if you're trying to compare CONST_INTs, those are shared and you can use pointer equality rather than their underlying value. Regardless, I think the right test is rtx_equal_p (operands[0], operands[1], NULL) With that change to bsetqi_msx, bclrqi_msx and bnotqi_msx this patch is OK. jeff -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJN8mMBAAoJEBRtltQi2kC7NjUIAJDylrPPoI6YMk4lfRwclIPT VCzk31q3DpZ3H5CEv8e6u7DmmJl9ng78uYHXejAqTbpAn/mDOtEWasBIUIhTACFF UgH3bK3wwhF412Dbr/6ND/dPCMiImzSUR8PC8N6S31k8q5JmXIkfVfX/oKaSH/n6 9VxyIfh7PmGRqjMlH434DyvOvH+qPfN3jSNLVHDvUeVYKI6gnfXtR8tuHTlIw4LO eiubgvmD4RXa6Nnpeuafs8GyTCRA5jbVU2jf3ZR3jBA08YpS/cSeECd19ytSdVuS Au20hmDPStkJwr/0kw+QtqeZRg5BP4JWF0COYQJDFQVa64Gt6LEterBmntPJr8g= =JdgV -END PGP SIGNATURE-
[Patch : H8300] Bug fix for bit insn and minor tweaks to insns
Hi, The following patch fixes an ICE that is generated when the compiler tries to perform bit manipulation for logical operations when the source and destination address does not match. The testcase is also included in the patch(gcc.dg). The additional condition in the insn takes care of the ICE which occurs at '-O1'. The other insn's are reordered to give preference to bit instructions using existing constraints. Ok to apply? Thanks & Regards, Kaushik Phatak www.kpitgnutools.com 2011-06-09 Kaushik Phatak * config/h8300/h8300.md (bsetqi_msx, bclrqi_msx, bnotqi_msx): Added condition to disallow non-identical memory locations. (*andqi3_2, andqi3_1, iorqi3_1, xorqi3_1): Reorder insn to give preference to bit manipulation instructions. * gcc.dg/h8300-bit-insn-ice2.2: New testcase. h8_bit.diff Description: h8_bit.diff