[gem5-dev] Change in gem5/gem5[master]: sim: Add a function for decoding the field(s) of an m5op address.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23183 )


Change subject: sim: Add a function for decoding the field(s) of an m5op  
address.

..

sim: Add a function for decoding the field(s) of an m5op address.

These have at one time included both a func and subfunc, although the
subfunc was unused and is now excluded.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ic35ced7a012aa72af5454768f3cbd11b431b061a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23183
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Marjan Fariborz 
Reviewed-by: Jason Lowe-Power 
---
M src/sim/pseudo_inst.hh
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Marjan Fariborz: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index caada36..44227af 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -86,6 +86,12 @@
 namespace PseudoInst
 {

+static inline void
+decodeAddrOffset(Addr offset, uint8_t &func)
+{
+func = bits(offset, 15, 8);
+}
+
 void arm(ThreadContext *tc);
 void quiesce(ThreadContext *tc);
 void quiesceSkip(ThreadContext *tc);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic35ced7a012aa72af5454768f3cbd11b431b061a
Gerrit-Change-Number: 23183
Gerrit-PatchSet: 11
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Marjan Fariborz 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: x86: Use the m5 op range in the system.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23182 )


Change subject: x86: Use the m5 op range in the system.
..

x86: Use the m5 op range in the system.

Don't hard code a range into the TLB.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0ead4353672ccf6e3e51ddbb4676be3a09f1136a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23182
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Pouya Fotouhi 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/x86/X86TLB.py
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
3 files changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Pouya Fotouhi: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 2e61d02..b3200ec 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -55,5 +55,6 @@
 cxx_class = 'X86ISA::TLB'
 cxx_header = 'arch/x86/tlb.hh'
 size = Param.Unsigned(64, "TLB size")
+system = Param.System(Parent.any, "system object")
 walker = Param.X86PagetableWalker(\
 X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 2985a8b..65ed9c0 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -61,7 +61,7 @@

 TLB::TLB(const Params *p)
 : BaseTLB(p), configAddress(0), size(p->size),
-  tlb(size), lruSeq(0)
+  tlb(size), lruSeq(0), m5opRange(p->system->m5opRange())
 {
 if (!size)
 fatal("TLBs must have a non-zero size.\n");
@@ -229,8 +229,6 @@
 {
 Addr paddr = req->getPaddr();

-AddrRange m5opRange(0x, 0x1);
-
 if (m5opRange.contains(paddr)) {
 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
   Request::STRICT_ORDER);
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index b969bca..21bd640 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,8 @@
 TlbEntryTrie trie;
 uint64_t lruSeq;

+AddrRange m5opRange;
+
 // Statistics
 Stats::Scalar rdAccesses;
 Stats::Scalar wrAccesses;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0ead4353672ccf6e3e51ddbb4676be3a09f1136a
Gerrit-Change-Number: 23182
Gerrit-PatchSet: 11
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch, sim: Use _m5opRange in System::allocPhysPages.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23181 )


Change subject: arch,sim: Use _m5opRange in System::allocPhysPages.
..

arch,sim: Use _m5opRange in System::allocPhysPages.

This removes the hardcoded assumption that the m5 ops live at the
address they use in x86.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ia551d7cf5b08f926c7756541c92a2af9bb73b88a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23181
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/system.hh
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 7 insertions(+), 8 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 90fed14..771d738 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -269,12 +269,6 @@
 return mask(physAddrRange());
 }

-/**
- * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
- * an invalid/empty range if disabled.
- */
-const AddrRange &m5opRange() const { return _m5opRange; }
-
 /** Is Arm Semihosting support enabled? */
 bool haveSemihosting() const { return semihosting != nullptr; }

diff --git a/src/sim/system.cc b/src/sim/system.cc
index b5b59ef..46fa384 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -432,8 +432,7 @@

 Addr next_return_addr = pagePtr << PageShift;

-AddrRange m5opRange(0x, 0x1);
-if (m5opRange.contains(next_return_addr)) {
+if (_m5opRange.contains(next_return_addr)) {
 warn("Reached m5ops MMIO region\n");
 return_addr = 0x;
 pagePtr = 0x >> PageShift;
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 638e352..6a8b502 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -584,6 +584,12 @@

 const Params *params() const { return (const Params *)_params; }

+/**
+ * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
+ * an invalid/empty range if disabled.
+ */
+const AddrRange &m5opRange() const { return _m5opRange; }
+
   public:

 /**

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia551d7cf5b08f926c7756541c92a2af9bb73b88a
Gerrit-Change-Number: 23181
Gerrit-PatchSet: 11
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sim: Add a typetraits style mechanism to test for VarArgs.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23750 )


Change subject: sim: Add a typetraits style mechanism to test for VarArgs.
..

sim: Add a typetraits style mechanism to test for VarArgs.

This family of types can be cumbersome to check for when building
ABI rules. This struct template makes that a little easier.

Change-Id: Ic3a1b8424f8ca04564f8228365371b357f33276c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23750
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
2 files changed, 17 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index 5432af3..9726c49 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -284,6 +284,12 @@
 }
 };

+template 
+struct IsVarArgs : public std::false_type {};
+
+template 
+struct IsVarArgs> : public std::true_type {};
+
 template 
 std::ostream &
 operator << (std::ostream &os, const VarArgs &va)
diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
index 506163e..bd444aa 100644
--- a/src/sim/guest_abi.test.cc
+++ b/src/sim/guest_abi.test.cc
@@ -362,3 +362,14 @@
 std::string dump = dumpSimcall("test", &tc, testIntVoid);
 EXPECT_EQ(dump, "test(0, 11, 2, 13, ...)");
 }
+
+TEST(GuestABI, isVarArgs)
+{
+EXPECT_TRUE(GuestABI::IsVarArgs>::value);
+EXPECT_FALSE(GuestABI::IsVarArgs::value);
+EXPECT_FALSE(GuestABI::IsVarArgs::value);
+struct FooStruct {};
+EXPECT_FALSE(GuestABI::IsVarArgs::value);
+union FooUnion {};
+EXPECT_FALSE(GuestABI::IsVarArgs::value);
+}

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic3a1b8424f8ca04564f8228365371b357f33276c
Gerrit-Change-Number: 23750
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: cpu: Remove the ancient do_quiesce config option.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25143 )



Change subject: cpu: Remove the ancient do_quiesce config option.
..

cpu: Remove the ancient do_quiesce config option.

This option has existed for a very long time, defaults to True, and is
not used in any of the checked in configs. It enables the "quiesce"
mechanism, originally just pseudo instructions, and it's not clear
why you'd ever want to turn it off.

Change-Id: I92c7e5af22157e8435c7326634857d30bb5d7254
---
M src/cpu/BaseCPU.py
M src/cpu/thread_context.cc
2 files changed, 0 insertions(+), 7 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 57f0f2f..3262418 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -164,7 +164,6 @@
 "enable statistics pseudo instructions")

 profile = Param.Latency('0ns', "trace the kernel stack")
-do_quiesce = Param.Bool(True, "enable quiesce instructions")

 wait_for_remote_gdb = Param.Bool(False,
 "Wait for a remote GDB connection");
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index f8c422c..bebfe91 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -132,9 +132,6 @@
 void
 ThreadContext::quiesce()
 {
-if (!getCpuPtr()->params()->do_quiesce)
-return;
-
 DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());

 suspend();
@@ -148,9 +145,6 @@
 {
 BaseCPU *cpu = getCpuPtr();

-if (!cpu->params()->do_quiesce)
-return;
-
 EndQuiesceEvent *quiesceEvent = getQuiesceEvent();

 cpu->reschedule(quiesceEvent, resume, true);

--
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Gerrit-Change-Id: I92c7e5af22157e8435c7326634857d30bb5d7254
Gerrit-Change-Number: 25143
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Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch, cpu, sim: Eliminate the now empty kernel statistics classes.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25149 )



Change subject: arch,cpu,sim: Eliminate the now empty kernel statistics  
classes.

..

arch,cpu,sim: Eliminate the now empty kernel statistics classes.

This includes the base and ISA specific Kernel::Statistics classes, the
plumbing through ThreadContext to access them, and the switching
header file associated with them.

Change-Id: Ia511a59325b629aa9ccc0e695ddd47ff11916499
---
M src/arch/SConscript
D src/arch/alpha/kernel_stats.hh
M src/arch/arm/fastmodel/iris/thread_context.hh
D src/arch/arm/kernel_stats.hh
M src/arch/mips/idle_event.cc
D src/arch/mips/kernel_stats.hh
D src/arch/power/kernel_stats.hh
M src/arch/riscv/idle_event.cc
D src/arch/riscv/kernel_stats.hh
D src/arch/sparc/kernel_stats.hh
D src/arch/x86/kernel_stats.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
D src/kern/kernel_stats.hh
M src/sim/system.cc
24 files changed, 8 insertions(+), 532 deletions(-)



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 0661db7..3d39a01 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -62,7 +62,6 @@
 decoder.hh
 isa.hh
 isa_traits.hh
-kernel_stats.hh
 locked_mem.hh
 microcode_rom.hh
 mmapped_ipr.hh
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
deleted file mode 100644
index 4a0618e..000
--- a/src/arch/alpha/kernel_stats.hh
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- *  Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_KERNEL_STATS_HH__
-#define __ARCH_ALPHA_KERNEL_STATS_HH__
-
-#include "kern/kernel_stats.hh"
-
-namespace AlphaISA {
-namespace Kernel {
-
-class Statistics : public ::Kernel::Statistics {};
-
-} // namespace Kernel
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_KERNEL_STATS_HH__
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 5acc813..daa79a3 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -215,12 +215,6 @@
 panic("%s not implemented.", __FUNCTION__);
 }

-Kernel::Statistics *
-getKernelStats() override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
 PortProxy &getPhysProxy() override { return *physProxy; }
 PortProxy &getVirtProxy() override { return *virtProxy; }
 void initMemProxies(::ThreadContext *tc) override;
diff --git a/src/arch/arm/kernel_stats.hh b/src/arch/arm/kernel_stats.hh
deleted file mode 100644
index dd184f8..000
--- a/src/arch/arm/kernel_stats.hh
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and th

[gem5-dev] Change in gem5/gem5[master]: sim: Move guts of quiesce and quisceTick from ThreadContext to System.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25145 )



Change subject: sim: Move guts of quiesce and quisceTick from ThreadContext  
to System.

..

sim: Move guts of quiesce and quisceTick from ThreadContext to System.

The functions in ThreadContext are now just convenience wrappers.

Change-Id: Ib56c4bdd27e611fb667a8056dfae37065f4034eb
---
M src/cpu/thread_context.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 90 insertions(+), 37 deletions(-)



diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index bebfe91..f3c8c4f 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -132,28 +132,14 @@
 void
 ThreadContext::quiesce()
 {
-DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
-
-suspend();
-if (getKernelStats())
-getKernelStats()->quiesce();
+getSystemPtr()->threads.quiesce(contextId());
 }


 void
 ThreadContext::quiesceTick(Tick resume)
 {
-BaseCPU *cpu = getCpuPtr();
-
-EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
-
-cpu->reschedule(quiesceEvent, resume, true);
-
-DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
-
-suspend();
-if (getKernelStats())
-getKernelStats()->quiesce();
+getSystemPtr()->threads.quiesceTick(contextId(), resume);
 }

 void
@@ -250,26 +236,8 @@
 ntc.setContextId(otc.contextId());
 ntc.setThreadId(otc.threadId());

-if (FullSystem) {
+if (FullSystem)
 assert(ntc.getSystemPtr() == otc.getSystemPtr());

-BaseCPU *ncpu(ntc.getCpuPtr());
-assert(ncpu);
-EndQuiesceEvent *oqe(otc.getQuiesceEvent());
-assert(oqe);
-assert(oqe->tc == &otc);
-
-BaseCPU *ocpu(otc.getCpuPtr());
-assert(ocpu);
-EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
-assert(nqe);
-assert(nqe->tc == &ntc);
-
-if (oqe->scheduled()) {
-ncpu->schedule(nqe, oqe->when());
-ocpu->deschedule(oqe);
-}
-}
-
 otc.setStatus(ThreadContext::Halted);
 }
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 547bdd5..a7c0a9f 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -87,6 +87,31 @@

 vector System::systemList;

+void
+System::Threads::Thread::resume()
+{
+#   if THE_ISA != NULL_ISA
+DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
+context->activate();
+#   endif
+}
+
+std::string
+System::Threads::Thread::name() const
+{
+assert(context);
+return csprintf("%s.threads[%d]", context->getSystemPtr()->name(),
+context->contextId());
+}
+
+void
+System::Threads::Thread::quiesce() const
+{
+context->suspend();
+if (context->getKernelStats())
+context->getKernelStats()->quiesce();
+}
+
 ContextID
 System::Threads::insert(ThreadContext *tc, ContextID id)
 {
@@ -105,6 +130,7 @@

 auto &t = thread(id);
 t.context = tc;
+t.resumeEvent = new EventWrapper(t);
 #   if THE_ISA != NULL_ISA
 int port = getRemoteGDBPort();
 if (port) {
@@ -120,9 +146,17 @@
 System::Threads::replace(ThreadContext *tc, ContextID id)
 {
 auto &t = thread(id);
-t.context = tc;
+panic_if(!t.context, "Can't replace a context which doesn't exist.");
 if (t.gdb)
 t.gdb->replaceThreadContext(tc);
+#   if THE_ISA != NULL_ISA
+if (t.resumeEvent->scheduled()) {
+Tick when = t.resumeEvent->when();
+t.context->getCpuPtr()->deschedule(t.resumeEvent);
+tc->getCpuPtr()->schedule(t.resumeEvent, when);
+}
+#   endif
+t.context = tc;
 }

 ThreadContext *
@@ -149,6 +183,31 @@
 return count;
 }

+void
+System::Threads::quiesce(ContextID id)
+{
+auto &t = thread(id);
+#   if THE_ISA != NULL_ISA
+BaseCPU *cpu = t.context->getCpuPtr();
+DPRINTFS(Quiesce, cpu, "quiesce()\n");
+#   endif
+t.quiesce();
+}
+
+void
+System::Threads::quiesceTick(ContextID id, Tick when)
+{
+#   if THE_ISA != NULL_ISA
+auto &t = thread(id);
+BaseCPU *cpu = t.context->getCpuPtr();
+
+DPRINTFS(Quiesce, cpu, "quiesceTick until %u\n", when);
+t.quiesce();
+
+cpu->reschedule(t.resumeEvent, when, true);
+#   endif
+}
+
 int System::numSystemsRunning = 0;

 System::System(Params *p)
@@ -372,6 +431,14 @@
 {
 SERIALIZE_SCALAR(pagePtr);

+for (auto &t: threads.threads) {
+Tick when = 0;
+if (t.resumeEvent && t.resumeEvent->scheduled())
+when = t.resumeEvent->when();
+ContextID id = t.context->contextId();
+paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
+}
+
 // also serialize the memories in the system
 physmem.serializeSection(cp, "physmem");
 }
@@ -382,6 +449,18 @@
 {
 UNSERIALIZE_SCALAR(pagePtr);

+for (auto &t: threads.threads) {
+Tick when;
+ContextID id = t.context->contextId();
+if (!optParamIn(cp, csprintf("quiesc

[gem5-dev] Change in gem5/gem5[master]: fastmodel, cpu, sim: Eliminate EndQuiesceEvent and plumbing.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25146 )



Change subject: fastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing.
..

fastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing.

Change-Id: Ifca504bc298c09cbc16ef7cded21da455fb1e118
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/SConscript
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/o3/thread_state.hh
D src/cpu/quiesce_event.cc
D src/cpu/quiesce_event.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/sim/pseudo_inst.cc
16 files changed, 1 insertion(+), 163 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 5590f7f..5acc813 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -256,12 +256,6 @@

 void regStats(const std::string &name) override {}

-EndQuiesceEvent *
-getQuiesceEvent() override
-{
-panic("%s not implemented.", __FUNCTION__);
-}
-
 // Not necessarily the best location for these...
 // Having an extra function just to read these is obnoxious
 Tick
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 0cbe013..291b3f7 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -99,7 +99,6 @@
 Source('intr_control.cc')
 Source('nativetrace.cc')
 Source('profile.cc')
-Source('quiesce_event.cc')
 Source('reg_class.cc')
 Source('static_inst.cc')
 Source('simple_thread.cc')
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index e01a00d..6a7e5e1 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -51,7 +51,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Checker.hh"

-class EndQuiesceEvent;
 namespace Kernel {
 class Statistics;
 };
@@ -223,12 +222,6 @@
 checkerTC->regStats(name);
 }

-EndQuiesceEvent *
-getQuiesceEvent() override
-{
-return actualTC->getQuiesceEvent();
-}
-
 Tick readLastActivate() override { return  
actualTC->readLastActivate(); }

 Tick readLastSuspend() override { return actualTC->readLastSuspend(); }

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bf9ff7e..d212303 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -54,7 +54,6 @@
 #include "cpu/checker/thread_context.hh"
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/thread_context.hh"
-#include "cpu/quiesce_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Activity.hh"
@@ -353,9 +352,6 @@
 assert(o3_tc->cpu);
 o3_tc->thread = this->thread[tid];

-// Setup quiesce event.
-this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-
 // Give the thread the TC.
 this->thread[tid]->tc = tc;

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 9607f73..1319ca1 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -48,7 +48,6 @@
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/thread_context.hh"

-class EndQuiesceEvent;
 namespace Kernel {
 class Statistics;
 }
@@ -456,12 +455,6 @@
 /** Reads the funcExeInst counter. */
 Counter readFuncExeInst() const override { return thread->funcExeInst;  
}


-/** Returns pointer to the quiesce event. */
-EndQuiesceEvent *
-getQuiesceEvent() override
-{
-return this->thread->quiesceEvent;
-}
 /** check if the cpu is currently in state update mode and squash if  
not.

  * This function will return true if a trap is pending or if a fault or
  * similar is currently writing to the thread context and doesn't want
diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index e05721b..5389407 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -50,7 +50,6 @@
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
-#include "cpu/quiesce_event.hh"
 #include "debug/O3CPU.hh"

 template 
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index bd5c51f..8a81216 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -50,7 +50,6 @@
 #include "sim/full_system.hh"
 #include "sim/sim_exit.hh"

-class EndQuiesceEvent;
 class Event;
 class FunctionalMemory;
 class FunctionProfile;
diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc
deleted file mode 100644
index a152448..000
--- a/src/cpu/quiesce_event.cc
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All ri

[gem5-dev] Change in gem5/gem5[master]: arch, cpu, dev, sim, mem: Collect System thread elements into a subclass.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25144 )



Change subject: arch,cpu,dev,sim,mem: Collect System thread elements into a  
subclass.

..

arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.

The System class has a few different arrays of values which each
correspond to a thread of execution based on their position. This
change collects them together into a single class to make managing them
easier and less error prone. It also collects methods for manipulating
those threads as an API for that class.

This class acts as a collection point for thread based state which the
System class can look into to get at all its state. It also acts as an
interface for interacting with threads for other classes. This forces
external consumers to use the API instead of accessing the individual
arrays which improves consistency.

Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc
---
M src/arch/alpha/fs_workload.cc
M src/arch/alpha/linux/fs_workload.cc
M src/arch/alpha/process.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/kvm/gic.cc
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/linux/process.cc
M src/arch/arm/process.cc
M src/arch/arm/tlbi_op.hh
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/process.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/arch/x86/fs_workload.cc
M src/arch/x86/interrupts.cc
M src/arch/x86/linux/fs_workload.cc
M src/arch/x86/process.cc
M src/cpu/base.hh
M src/cpu/intr_control.cc
M src/cpu/kvm/vm.cc
M src/cpu/o3/cpu.cc
M src/dev/alpha/backdoor.cc
M src/dev/alpha/tsunami_cchip.cc
M src/dev/arm/a9scu.cc
M src/dev/arm/generic_timer.cc
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/timer_cpulocal.cc
M src/dev/arm/vgic.cc
M src/dev/mips/malta_cchip.cc
M src/dev/net/dist_iface.cc
M src/dev/sparc/iob.cc
M src/dev/x86/i82094aa.cc
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/queued.cc
M src/sim/process.cc
M src/sim/pseudo_inst.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/system.cc
M src/sim/system.hh
52 files changed, 358 insertions(+), 253 deletions(-)



diff --git a/src/arch/alpha/fs_workload.cc b/src/arch/alpha/fs_workload.cc
index ef7da35..013245b 100644
--- a/src/arch/alpha/fs_workload.cc
+++ b/src/arch/alpha/fs_workload.cc
@@ -76,7 +76,7 @@
 {
 KernelWorkload::initState();

-for (auto *tc: system->threadContexts) {
+for (auto *tc: system->threads) {
 int cpuId = tc->contextId();
 initIPRs(tc, cpuId);

diff --git a/src/arch/alpha/linux/fs_workload.cc  
b/src/arch/alpha/linux/fs_workload.cc

index 20e3a65..8568e75 100644
--- a/src/arch/alpha/linux/fs_workload.cc
+++ b/src/arch/alpha/linux/fs_workload.cc
@@ -90,7 +90,7 @@
  * so we don't through the lengthly process of trying to
  * calculated it by using the PIT, RTC, etc.
  */
-uint64_t frequency =  
system->getThreadContext(0)->getCpuPtr()->frequency();

+uint64_t frequency = system->threads[0]->getCpuPtr()->frequency();
 it = kernelSymtab.find("est_cycle_freq");
 if (it != kernelSymtab.end())
 virt_proxy.write(it->address, frequency);
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 718a29d..1f200cf 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -169,7 +169,7 @@
 auxv_array_end += sizeof(aux);
 }

-ThreadContext *tc = system->getThreadContext(contextIds[0]);
+ThreadContext *tc = system->threads[contextIds[0]];

 tc->setIntReg(FirstArgumentReg, argc);
 tc->setIntReg(FirstArgumentReg + 1, argv_array_base);
@@ -181,7 +181,7 @@
 void
 AlphaProcess::setupASNReg()
 {
-ThreadContext *tc = system->getThreadContext(contextIds[0]);
+ThreadContext *tc = system->threads[contextIds[0]];
 tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
 }

@@ -207,7 +207,7 @@

 argsInit(MachineBytes, PageBytes);

-ThreadContext *tc = system->getThreadContext(contextIds[0]);
+ThreadContext *tc = system->threads[contextIds[0]];
 tc->setIntReg(GlobalPointerReg, 0);
 //Operate in user mode
 tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index cd04359..5e2afdc 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -41,8 +41,10 @@
 void
 CortexA76::initState()
 {
-for (auto *tc : threadContexts)
-tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,  
params()

[gem5-dev] Change in gem5/gem5[master]: alpha: Move the guts of Kernel::Statistics into FsWorkload.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25148 )



Change subject: alpha: Move the guts of Kernel::Statistics into FsWorkload.
..

alpha: Move the guts of Kernel::Statistics into FsWorkload.

Change-Id: I4707d973402148401510697c95e2fea003a7a9e2
---
M src/arch/alpha/SConscript
M src/arch/alpha/ev5.cc
M src/arch/alpha/fs_workload.cc
M src/arch/alpha/fs_workload.hh
M src/arch/alpha/idle_event.cc
M src/arch/alpha/isa/decoder.isa
M src/arch/alpha/isa/main.isa
D src/arch/alpha/kernel_stats.cc
M src/arch/alpha/kernel_stats.hh
9 files changed, 287 insertions(+), 353 deletions(-)



diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 235ae0f..e28fa56 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -41,7 +41,6 @@
 Source('interrupts.cc')
 Source('ipr.cc')
 Source('isa.cc')
-Source('kernel_stats.cc')
 Source('linux/linux.cc')
 Source('linux/process.cc')
 Source('linux/fs_workload.cc')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 3613d30..e1e46e4 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -30,8 +30,8 @@
  */

 #include "arch/alpha/faults.hh"
+#include "arch/alpha/fs_workload.hh"
 #include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/kernel_stats.hh"
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/tlb.hh"
 #include "base/cp_annotate.hh"
@@ -189,9 +189,9 @@
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
-auto *stats = dynamic_cast(
-tc->getKernelStats());
-assert(stats || !tc->getKernelStats());
+auto *workload = dynamic_cast(
+tc->getSystemPtr()->workload);
+assert(workload || !tc->getSystemPtr()->workload);
 switch (idx) {
   case IPR_PALtemp0:
   case IPR_PALtemp1:
@@ -240,8 +240,8 @@

   case IPR_PALtemp23:
 // write entire quad w/ no side-effect
-if (stats)
-stats->context(ipr[idx], val, tc);
+if (workload)
+workload->recordContext(ipr[idx], val, tc);
 ipr[idx] = val;
 break;

@@ -264,17 +264,17 @@
   case IPR_IPLR:
 // only write least significant five bits - interrupt level
 ipr[idx] = val & 0x1f;
-if (stats)
-stats->swpipl(ipr[idx]);
+if (workload)
+workload->recordSwpipl(ipr[idx]);
 break;

   case IPR_DTB_CM:
 if (val & 0x18) {
-if (stats)
-stats->mode(Kernel::user, tc);
+if (workload)
+workload->recordMode(AlphaISA::FsWorkload::UserMode, tc);
 } else {
-if (stats)
-stats->mode(Kernel::kernel, tc);
+if (workload)
+workload->recordMode(AlphaISA::FsWorkload::KernelMode, tc);
 }
 M5_FALLTHROUGH;

diff --git a/src/arch/alpha/fs_workload.cc b/src/arch/alpha/fs_workload.cc
index 013245b..d3e4585 100644
--- a/src/arch/alpha/fs_workload.cc
+++ b/src/arch/alpha/fs_workload.cc
@@ -35,10 +35,14 @@

 #include "arch/alpha/ev5.hh"
 #include "arch/alpha/faults.hh"
+#include "arch/alpha/osfpal.hh"
+#include "arch/generic/linux/threadinfo.hh"
 #include "arch/vtophys.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
+#include "base/statistics.hh"
 #include "base/trace.hh"
+#include "debug/Context.hh"
 #include "debug/Loader.hh"
 #include "mem/fs_translating_port_proxy.hh"
 #include "params/AlphaFsWorkload.hh"
@@ -48,7 +52,11 @@
 namespace AlphaISA
 {

-FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p)
+const char *FsWorkload::modeStr[] = { "kernel", "user", "idle" };
+
+FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p),
+idleProcess((Addr)-1), theMode(KernelMode), lastModeTick(0),
+iplLast(0), iplLastTick(0)
 {
 // Load Console Code
 console = Loader::createObjectFile(params()->console);
@@ -130,6 +138,181 @@
 }

 void
+FsWorkload::regStats()
+{
+KernelWorkload::regStats();
+
+using namespace Stats;
+
+_callpal
+.init(256)
+.name(name() + ".callpal")
+.desc("number of callpals executed")
+.flags(total | pdf | nozero | nonan)
+;
+
+for (int i = 0; i < PAL::NumCodes; ++i) {
+const char *str = PAL::name(i);
+if (str)
+_callpal.subname(i, str);
+}
+
+_hwrei
+.name(name() + ".inst.hwrei")
+.desc("number of hwrei instructions executed")
+;
+
+_mode
+.init(NumModes)
+.name(name() + ".mode_switch")
+.desc("number of protection mode switches")
+;
+
+for (int i = 0; i < NumModes; ++i)
+_mode.subname(i, modeStr[i]);
+
+_modeGood
+.init(NumModes)
+.name(name() + ".mode_good")
+;
+
+for (int i = 0; i < NumModes; ++i)
+_modeGood.subname(i, modeStr[i]);
+
+_modeFraction
+.nam

[gem5-dev] Change in gem5/gem5[master]: arch, kern, sim: Move the stats in Kernel::Statistics to Workload.

2020-02-06 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25147 )



Change subject: arch,kern,sim: Move the stats in Kernel::Statistics to  
Workload.

..

arch,kern,sim: Move the stats in Kernel::Statistics to Workload.

These are the stats in the base class, not in any derived classes. Only
Alpha has an additional stats. These were not really "kernel"
statistics, they were just applicable primarily in FS. They are
potentially applicable to any simulation, but will probably not be
incremented in SE simulations.

Also this merges these stats from being per thread to being per
workload, ie operating system instance. This is probably more relevant
since exactly what thread within a workload runs which particular
instruction is not very important/predictable, but the aggregate
behavior is. If necessary, this could be adjusted in the future to
split things back out again into stats per thread while keeping them
inside the single workload object.

Change-Id: I130e11a9022bdfcadcfb02c7995871503114cd53
---
M src/arch/sparc/ua2005.cc
M src/kern/SConscript
D src/kern/kernel_stats.cc
M src/kern/kernel_stats.hh
M src/sim/pseudo_inst.cc
M src/sim/system.cc
M src/sim/workload.hh
7 files changed, 33 insertions(+), 81 deletions(-)



diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 3403451..65928b6 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -28,7 +28,6 @@

 #include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa.hh"
-#include "arch/sparc/kernel_stats.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -36,7 +35,6 @@
 #include "cpu/thread_context.hh"
 #include "debug/Quiesce.hh"
 #include "debug/Timer.hh"
-#include "sim/full_system.hh"
 #include "sim/system.hh"

 using namespace SparcISA;
@@ -232,8 +230,9 @@
 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
 // Time to go to sleep
 tc->suspend();
-if (FullSystem && tc->getKernelStats())
-tc->getKernelStats()->quiesce();
+auto *workload = tc->getSystemPtr()->workload;
+if (workload)
+workload->recordQuiesce();
 }
 break;

diff --git a/src/kern/SConscript b/src/kern/SConscript
index d079cbe..b799a70 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -33,7 +33,6 @@
 if env['TARGET_ISA'] == 'null':
 Return()

-Source('kernel_stats.cc')
 Source('linux/events.cc')
 Source('linux/linux.cc')
 Source('linux/helpers.cc')
diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc
deleted file mode 100644
index 2d1d4fa..000
--- a/src/kern/kernel_stats.cc
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- *  Nathan Binkert
- */
-
-#include 
-
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "kern/kernel_stats.hh"
-#include "sim/system.hh"
-
-using namespace std;
-using namespace Stats;
-
-namespace Kernel {
-
-void
-Statistics::regStats(const string &_name)
-{
-myname = _name;
-
-_arm
-.name(name() + ".inst.arm")
-.desc("number of arm instructions executed")
-;
-
-_quiesce
-.name(name() + ".inst.quiesce")
-.desc("number of quiesce instructions executed")
-

Re: [gem5-dev] Ruby Checkpointing Broken

2020-02-06 Thread Timothy Hayes 
I've done a git bisect and found the problematic commit.

bb94296373dde1d0ce971ee58ad111f4225c425e is the first bad commit
commit bb94296373dde1d0ce971ee58ad111f4225c425e
Author: Joe Gross 
Date:   Mon Jul 20 09:15:18 2015 -0500

mem-ruby: Fixed pipeline squashes caused by aliased requests

This patch was created by Bihn Pham during his internship at AMD.

This patch fixes a very significant performance bug when using the O3
CPU model and Ruby. The issue was Ruby returned false when it received
a request to the same address that already has an outstanding request or
when the memory is blocked. As a result, O3 unnecessary squashed the
pipeline and re-executed instructions. This fix merges readRequestTable
and writeRequestTable in Sequencer into a single request table that
keeps track of all requests and allows multiple outstanding requests to
the same address. This prevents O3 from squashing the pipeline.

Change-Id: If934d57b4736861e342de0ab18be4feec464273d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 


From: gem5-dev  on behalf of Timothy Hayes 

Sent: 06 February 2020 17:55
To: gem5-dev@gem5.org 
Subject: [gem5-dev] Ruby Checkpointing Broken

I’m using a workflow that relies on checkpoints created by Gem5/Ruby w/ the 
MOESI_hammer protocol. I successfully created a set of checkpoints last 
September using the public branch up to date at the time. I’ve now pulled the 
latest changes from upstream and tried to recreate them, however, the 
checkpointing mechanism is no longer working. My Linux disk image boots 
successfully, but calling “/sbin/m5 checkpoint” fails silently. No checkpoint 
is created and the simulation tries to resume from the end of time in an 
infinite loop. I’ve tried this with hack_back_ckpt.rcS as well as manually on 
an interactive terminal (same result).

Has something changed between last September and now that might have corrupted 
the checkpointing mechanism w/ Ruby? It was functioning correctly as of 
September 27th 2019.

I’ve tried creating a checkpoint using AtomicCPU w/ the classic memory system 
and it seems to work okay.

Extra details are in the post-script.

--
Timothy Hayes
Senior Research Engineer
Arm Research
Phone: +44-1223405170
timothy.ha...@arm.com


== compile ==
scons CC=gcc-8 CXX=g++-8 build/ARM_MOESI_hammer/gem5.opt TARGET_ISA=arm 
PROTOCOL=MOESI_hammer SLICC_HTML=True 
CPU_MODELS=AtomicSimpleCPU,TimingSimpleCPU,O3CPU -j 8

== run ==
./gem5/build/ARM_MOESI_hammer/gem5.opt ./gem5/configs/example/fs.py --ruby 
--num-cpus=1 --mem-type=SimpleMemory --mem-size=4GB --cpu-type=TimingSimpleCPU 
--kernel=vmlinux.vexpress_gem5_v1_64 --machine-type=VExpress_GEM5_V1 
--disk-image=arm64-ff2-gem5-D1-1.img 
--script=./gem5/configs/boot/hack_back_ckpt.rcS

== stdout ==
warn: You are trying to use Ruby on ARM, which is not working properly yet.
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb  6 2020 14:39:34
gem5 started Feb  6 2020 17:19:51
gem5 executing on machine, pid 18966
command line: ./gem5/build/ARM_MOESI_hammer/gem5.opt 
./gem5/configs/example/fs.py --ruby --num-cpus=1 --mem-type=SimpleMemory 
--mem-size=4GB --cpu-type=TimingSimpleCPU --kernel=vmlinux.vexpress_gem5_v1_64 
--machine-type=VExpress_GEM5_V1 --disk-image=arm64-ff2-gem5-D1-1.img 
–script=./gem5/configs/boot/hack_back_ckpt.rcS

Global frequency set at 1 ticks per second
info: kernel located at: ./dist/binaries/vmlinux.vexpress_gem5_v1_64
warn: Bootloader entry point 0x10 overriding reset address 0
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. 
Assuming you wanted these to match.
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3456
0: system.remote_gdb: listening for remote gdb on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: . /m5out/system.dtb at address 0x8800
 REAL SIMULATION 
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC 
state machines. Make sure to setMRU() near callbacks in .sm files!
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Cache maintenance operations are not supported in Ruby.
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.3-JSConv

2020-02-06 Thread Jordi Vaquero (Gerrit) 
Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25023 )


Change subject: arch-arm: Implement ARMv8.3-JSConv
..

arch-arm: Implement ARMv8.3-JSConv

This commit implements Armv8 javascript float point convertion instructions
VJVCT and FJCVTZS.

Change-Id: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25023
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/insts/fplib.cc
M src/arch/arm/insts/fplib.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/insts/fp.isa
M src/arch/arm/isa/insts/fp64.isa
6 files changed, 124 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/fplib.cc b/src/arch/arm/insts/fplib.cc
index 49305ec..460ca7c 100644
--- a/src/arch/arm/insts/fplib.cc
+++ b/src/arch/arm/insts/fplib.cc
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
+* Copyright (c) 2020 Metempsy Technology Consulting
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
@@ -37,10 +38,10 @@
 * Authors: Edmund Grimley Evans
 *  Thomas Grocutt
 */
-
 #include 

 #include 
+#include 

 #include "base/logging.hh"
 #include "fplib.hh"
@@ -429,6 +430,8 @@
 fp64_unpack(int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode,
 int *flags)
 {
+
+
 *sgn = x >> (FP64_BITS - 1);
 *exp = FP64_EXP(x);
 *mnt = FP64_MANT(x);
@@ -4737,6 +4740,71 @@
 return result;
 }

+uint32_t
+fplibFPToFixedJS(uint64_t op, FPSCR &fpscr, bool is64, uint8_t& nz)
+{
+int flags = 0;
+uint32_t result;
+bool Z = true;
+
+uint32_t sgn = bits(op, 63);
+int32_t exp  = bits(op, 62, 52);
+uint64_t mnt = bits(op, 51, 0);
+
+if (exp == 0) {
+if (mnt != 0) {
+   if (fpscr.fz) {
+flags |= FPLIB_IDC;
+} else {
+flags |= FPLIB_IXC;
+Z = 0;
+}
+}
+result = 0;
+} else if (exp == 0x7ff) {
+flags |= FPLIB_IOC;
+result = 0;
+Z = 0;
+} else {
+mnt |= 1ULL << FP64_MANT_BITS;
+int mnt_shft = exp - FP64_EXP_BIAS - 52;
+bool err = true;
+
+if (abs(mnt_shft) >= FP64_BITS) {
+result = 0;
+Z = 0;
+} else if (mnt_shft >= 0) {
+result = lsl64(mnt, mnt_shft);
+} else if (mnt_shft < 0) {
+err = lsl64(mnt, mnt_shft+FP64_BITS) != 0;
+result = lsr64(mnt, abs(mnt_shft));
+}
+uint64_t max_result = (1UL << (FP32_BITS - 1)) -!sgn;
+if ((exp - FP64_EXP_BIAS) > 31 || result > max_result) {
+flags |= FPLIB_IOC;
+Z = false;
+} else if (err) {
+flags |= FPLIB_IXC;
+Z = false;
+}
+result =  sgn ? -result : result;
+}
+if (sgn == 1 && result == 0)
+Z = false;
+
+if (is64) {
+nz = Z? 0x1: 0x0;
+} else {
+fpscr.n = 0;
+fpscr.z = (int)Z;
+fpscr.c = 0;
+fpscr.v = 0;
+}
+
+set_fpscr0(fpscr, flags);
+return result;
+}
+
 template <>
 uint64_t
 fplibFPToFixed(uint16_t op, int fbits, bool u, FPRounding rounding,
diff --git a/src/arch/arm/insts/fplib.hh b/src/arch/arm/insts/fplib.hh
index d3d7790..a90999d 100644
--- a/src/arch/arm/insts/fplib.hh
+++ b/src/arch/arm/insts/fplib.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2020 Metempsy Technology Consulting
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -174,6 +175,8 @@
 /** Foating-point value for default NaN. */
 template 
 T fplibDefaultNaN();
+/** Floating-point  JS convert to a signed integer, with rounding to zero.  
*/
+uint32_t fplibFPToFixedJS(uint64_t op, FPSCR &fpscr, bool Is64, uint8_t  
&nz);


 /* Function specializations... */
 template <>
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 55959f5..76c7fd5 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2790,6 +2790,8 @@
 if (rmode != 0)
 return new Unknown64(machInst);
 return new FmovRegCoreW(machInst, rd, rn);
+  case 2:
+return new FJcvtFpSFixedDW(machInst, rd, rn);
   case 3: // FMOV Xd = Dn
 if (rmode != 0)
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/fp.isa  
b/src/arch/arm/isa/formats/fp.isa

index 133

[gem5-dev] Cron /z/m5/regression/do-regression quick

2020-02-06 Thread Cron Daemon 
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
scons: *** [build/HSAIL_X86/gpu-compute/gpu_static_inst.do] Error 1
scons: *** [build/HSAIL_X86/gpu-compute/gpu_dyn_inst.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/gpu_static_inst.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/branch.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/gen_exec.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/main.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/mem.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/pseudo_inst.do] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/gpu_decoder.do] Error 1
scons: *** [build/ARM/arch/arm/generated/generic_cpu_exec_3.fo] Error 1
scons: *** [build/HSAIL_X86/gpu-compute/gpu_static_inst.fo] Error 1
scons: *** [build/HSAIL_X86/gpu-compute/gpu_dyn_inst.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/gpu_static_inst.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/gen_exec.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/branch.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/main.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/pseudo_inst.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/insts/mem.fo] Error 1
scons: *** [build/HSAIL_X86/arch/hsail/gpu_decoder.fo] Error 1
scons: `build/ALPHA/tests/opt/quick/se' is up to date.
scons: `build/ALPHA/tests/opt/quick/fs' is up to date.
scons: `build/MIPS/tests/opt/quick/fs' is up to date.
scons: `build/NULL/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_hammer/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MESI_Two_Level/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_CMP_directory/tests/opt/quick/fs' is up to date.
scons: `build/NULL_MOESI_CMP_token/tests/opt/quick/fs' is up to date.
scons: `build/POWER/tests/opt/quick/se' is up to date.
scons: `build/POWER/tests/opt/quick/fs' is up to date.
scons: *** [build/SPARC/python/_m5/param_PciVirtIO.o] Error 1
scons: *** [build/SPARC/python/_m5/param_PioDevice.o] Error 1
scons: *** [build/SPARC/python/_m5/param_Platform.o] Error 1
scons: *** [build/SPARC/python/_m5/param_Prefetcher.o] Error 1
scons: *** [build/SPARC/python/_m5/param_Process.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSFixedPriorityPolicy.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSMemCtrl.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSMemSinkCtrl.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSPolicy.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSPropFairPolicy.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSTurnaroundPolicy.o] Error 1
scons: *** [build/SPARC/python/_m5/param_QoSTurnaroundPolicyIdeal.o] Error 1
scons: *** [build/SPARC/python/_m5/param_RubyController.o] Error 1
scons: *** [build/SPARC/python/_m5/param_RubyPort.o] Error 1
scons: *** [build/SPARC/python/_m5/param_RubyTester.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SimPoint.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SimpleCache.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SimpleDisk.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SimpleTrace.o] Error 1
scons: *** [build/SPARC/python/_m5/param_Sinic.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SnoopFilter.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SparcISA.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SparcInterrupts.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SparcNativeTrace.o] Error 1
scons: *** [build/SPARC/python/_m5/param_SparcSystem.o] Error 1
scons: *** [build/SPARC/python/_m5/param_StackDistProbe.o] Error 1
scons: *** [build/SPARC/python/_m5/param_StatisticalCorrector.o] Error 1
scons: *** [build/SPARC/python/_m5/param_System.o] Error 1
scons: *** [build/SPARC/python/_m5/param_T1000.o] Error 1
scons: *** [build/SPARC/python/_m5/param_TAGE.o] Error 1
scons: *** [build/SPARC/python/_m5/param_TAGEBase.o] Error 1
scons: *** [build/SPARC/python/_m5/param_TAGE_SC_L.o] Error 1
s

[gem5-dev] Ruby Checkpointing Broken

2020-02-06 Thread Timothy Hayes 
I’m using a workflow that relies on checkpoints created by Gem5/Ruby w/ the 
MOESI_hammer protocol. I successfully created a set of checkpoints last 
September using the public branch up to date at the time. I’ve now pulled the 
latest changes from upstream and tried to recreate them, however, the 
checkpointing mechanism is no longer working. My Linux disk image boots 
successfully, but calling “/sbin/m5 checkpoint” fails silently. No checkpoint 
is created and the simulation tries to resume from the end of time in an 
infinite loop. I’ve tried this with hack_back_ckpt.rcS as well as manually on 
an interactive terminal (same result).

Has something changed between last September and now that might have corrupted 
the checkpointing mechanism w/ Ruby? It was functioning correctly as of 
September 27th 2019.

I’ve tried creating a checkpoint using AtomicCPU w/ the classic memory system 
and it seems to work okay.

Extra details are in the post-script.

--
Timothy Hayes
Senior Research Engineer
Arm Research
Phone: +44-1223405170
timothy.ha...@arm.com


== compile ==
scons CC=gcc-8 CXX=g++-8 build/ARM_MOESI_hammer/gem5.opt TARGET_ISA=arm 
PROTOCOL=MOESI_hammer SLICC_HTML=True 
CPU_MODELS=AtomicSimpleCPU,TimingSimpleCPU,O3CPU -j 8

== run ==
./gem5/build/ARM_MOESI_hammer/gem5.opt ./gem5/configs/example/fs.py --ruby 
--num-cpus=1 --mem-type=SimpleMemory --mem-size=4GB --cpu-type=TimingSimpleCPU 
--kernel=vmlinux.vexpress_gem5_v1_64 --machine-type=VExpress_GEM5_V1 
--disk-image=arm64-ff2-gem5-D1-1.img 
--script=./gem5/configs/boot/hack_back_ckpt.rcS

== stdout ==
warn: You are trying to use Ruby on ARM, which is not working properly yet.
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb  6 2020 14:39:34
gem5 started Feb  6 2020 17:19:51
gem5 executing on machine, pid 18966
command line: ./gem5/build/ARM_MOESI_hammer/gem5.opt 
./gem5/configs/example/fs.py --ruby --num-cpus=1 --mem-type=SimpleMemory 
--mem-size=4GB --cpu-type=TimingSimpleCPU --kernel=vmlinux.vexpress_gem5_v1_64 
--machine-type=VExpress_GEM5_V1 --disk-image=arm64-ff2-gem5-D1-1.img 
–script=./gem5/configs/boot/hack_back_ckpt.rcS

Global frequency set at 1 ticks per second
info: kernel located at: ./dist/binaries/vmlinux.vexpress_gem5_v1_64
warn: Bootloader entry point 0x10 overriding reset address 0
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. 
Assuming you wanted these to match.
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3456
0: system.remote_gdb: listening for remote gdb on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: . /m5out/system.dtb at address 0x8800
 REAL SIMULATION 
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC 
state machines. Make sure to setMRU() near callbacks in .sm files!
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Cache maintenance operations are not supported in Ruby.
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: EnergyCtrl: Disabled handler, ignoring read from reg 0
info: Entering event queue @ 848156507000.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
info: Entering event queue @ 18446744073709551615.  Starting simulation...
ad infitum


== system.terminal ==

[0.389716] EXT4-fs (sd

[gem5-dev] Change in gem5/gem5[master]: tests: Simplify testignore by using ignore patterns

2020-02-06 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25084 )



Change subject: tests: Simplify testignore by using ignore patterns
..

tests: Simplify testignore by using ignore patterns

Rather than checking for exact match in the testignore we reverse
the logic: we check for the presence of ignore patterns (substrings)
in the testname.
In this way several test's flavours (like:

test-hello-RISCV-opt
test-hello-RISCV-debug
test-hello-RISCV-fast

)

will require a single entry in the .testignore:

test-hello-RISCV-

Change-Id: I54ff8947fd662483d1a086ec23adb9f612b6c654
Signed-off-by: Giacomo Travaglini 
---
M tests/gem5/.testignore
M tests/gem5/suite.py
2 files changed, 10 insertions(+), 13 deletions(-)



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index 99911b8..aa1fa03 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -1,12 +1,4 @@
-test-hello-RISCV-opt
-test-hello-RISCV-debug
-test-hello-RISCV-fast
-test-hello-SPARC-opt
-test-hello-SPARC-debug
-test-hello-SPARC-fast
-test-hello-MIPS-opt
-test-hello-MIPS-debug
-test-hello-MIPS-fast
-test-hello-ALPHA-opt
-test-hello-ALPHA-debug
-test-hello-ALPHA-fast
+test-hello-RISCV-
+test-hello-SPARC-
+test-hello-MIPS-
+test-hello-ALPHA-
diff --git a/tests/gem5/suite.py b/tests/gem5/suite.py
index 2c48797..3c6eea0 100644
--- a/tests/gem5/suite.py
+++ b/tests/gem5/suite.py
@@ -103,7 +103,12 @@

 # We check to see if this test suite is to be ignored. If so,  
we

 # skip it.
-if _name in ignore:
+ignored = False
+for ignore_pattern in ignore:
+if ignore_pattern in _name:
+ignored = True
+
+if ignored:
 continue

 # Create the running of gem5 subtest.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I54ff8947fd662483d1a086ec23adb9f612b6c654
Gerrit-Change-Number: 25084
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: ext: Add failure node to JUnit xml file

2020-02-06 Thread Giacomo Travaglini (Gerrit) 

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/25083

to review the following change.


Change subject: ext: Add failure node to JUnit xml file
..

ext: Add failure node to JUnit xml file

"failure" is a child of the testcase node:

https://llg.cubic.org/docs/junit/

It allows xml parsers to understand which testcase failed the run.
Otherwise CI frameworks like jenkins wouldn't be able to classify every
single testcase. Prior to this patch testlib was using
testsuites.failures and testsuite.failures only. These are simply
reporting the number of failures.

Change-Id: I0d498eca029c3232f2a588b153b6b6829b789394
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M ext/testlib/result.py
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 22c0248..786c21b 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -269,6 +269,20 @@
 LargeFileElement('system-out', test_result.stdout),
 ]

+if str(test_result.result) == 'Failed':
+self.elements.append(JUnitFailure('Test failed', 'ERROR'))
+
+
+class JUnitFailure(XMLElement):
+name = 'failure'
+def __init__(self, message, fail_type):
+self.attributes = [
+XMLAttribute('message', message),
+XMLAttribute('type', fail_type),
+]
+self.elements = []
+
+
 class LargeFileElement(XMLElement):
 def __init__(self, name, filename):
 self.name = name

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0d498eca029c3232f2a588b153b6b6829b789394
Gerrit-Change-Number: 25083
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: tests: Move old quick regressions back into their original set

2020-02-06 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25025 )


Change subject: tests: Move old quick regressions back into their original  
set

..

tests: Move old quick regressions back into their original set

realview64-simple-atomic and realview64-simple-timing had been moved
to the long list by:

https://gem5-review.googlesource.com/c/public/gem5/+/22686

in order to reduce computation time.
Since the timeout has been increased on kokoro we can safely put them
back where they were

Change-Id: Ib86f02b8ef493f450509b9f826a80faaec9ef579
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25025
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index d9d380e..c716004 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -44,17 +44,16 @@
 from testlib import *

 arm_fs_quick_tests = [
+'realview64-simple-atomic',
 'realview64-simple-atomic-dual',
 'realview64-simple-atomic-checkpoint',
+'realview64-simple-timing',
 'realview64-simple-timing-dual',
 'realview64-switcheroo-atomic',
 'realview64-switcheroo-timing',
-
 ]

 arm_fs_long_tests = [
-'realview64-simple-atomic', # TODO: Move this to quick regressions
-'realview64-simple-timing', # TODO: Move this to quick regressions
 'realview-simple-atomic',
 'realview-simple-atomic-dual',
 'realview-simple-atomic-checkpoint',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib86f02b8ef493f450509b9f826a80faaec9ef579
Gerrit-Change-Number: 25025
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Cron /z/m5/regression/do-regression --scratch all

2020-02-06 Thread Cron Daemon 
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
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* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
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* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
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build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
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* build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing: CHANGED!
* build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing: 
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* build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic: 
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build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
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* build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing: CHANGED!
* 
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* build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing: CHANGED!
* build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing: CHANGED!
* build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing: CHANGED!
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