Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
On Fri, 16 Mar 2018, matthew.s.atw...@intel.com wrote: > From: Matt Atwood> > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are advantages to a panel advertising a > higher rate then it needs for a its given mode. For panels that did, the > driver previously used a higher rate then necessary for that mode. Makes me wonder if the check here should be for those features (that should be mentioned, I guess you mean DSC, perhaps rate select) instead of the spec version. Please do send patches that compile, though. Gives you more credibility. ;) BR, Jani. > > Signed-off-by: Matt Atwood > --- > drivers/gpu/drm/i915/intel_dp.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index a2eeede..57b309c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1766,8 +1766,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, >* configuration, and typically these values correspond to the >* native resolution of the panel. >*/ > - min_lane_count = max_lane_count; > - min_clock = max_clock; > + if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ > + min_lane_count = max_lane_count; > + min_clock = max_clock; > + } > } > > for (; bpp >= 6*3; bpp -= 2*3) { -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
Hi Matt, Thank you for the patch! Yet something to improve: [auto build test ERROR on v4.16-rc4] [also build test ERROR on next-20180316] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/matthew-s-atwood-intel-com/drm-i915-make-edp-optimize-config/20180319-065307 config: i386-randconfig-a1-201811 (attached as .config) compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4 reproduce: # save the attached .config to linux build tree make ARCH=i386 All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_compute_config': >> drivers/gpu/drm/i915/intel_dp.c:1729:6: error: 'dpcd' undeclared (first use >> in this function) if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^ drivers/gpu/drm/i915/intel_dp.c:1729:6: note: each undeclared identifier is reported only once for each function it appears in >> drivers/gpu/drm/i915/intel_dp.c:1729:26: error: 'DPCD_REV_14' undeclared >> (first use in this function) if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^ vim +/dpcd +1729 drivers/gpu/drm/i915/intel_dp.c 1607 1608 bool 1609 intel_dp_compute_config(struct intel_encoder *encoder, 1610 struct intel_crtc_state *pipe_config, 1611 struct drm_connector_state *conn_state) 1612 { 1613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1614 struct drm_display_mode *adjusted_mode = _config->base.adjusted_mode; 1615 struct intel_dp *intel_dp = enc_to_intel_dp(>base); 1616 enum port port = encoder->port; 1617 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1618 struct intel_connector *intel_connector = intel_dp->attached_connector; 1619 struct intel_digital_connector_state *intel_conn_state = 1620 to_intel_digital_connector_state(conn_state); 1621 int lane_count, clock; 1622 int min_lane_count = 1; 1623 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1624 /* Conveniently, the link BW constants become indices with a shift...*/ 1625 int min_clock = 0; 1626 int max_clock; 1627 int bpp, mode_rate; 1628 int link_avail, link_clock; 1629 int common_len; 1630 uint8_t link_bw, rate_select; 1631 bool reduce_m_n = drm_dp_has_quirk(_dp->desc, 1632 DP_DPCD_QUIRK_LIMITED_M_N); 1633 1634 common_len = intel_dp_common_len_rate_limit(intel_dp, 1635 intel_dp->max_link_rate); 1636 1637 /* No common link rates between source and sink */ 1638 WARN_ON(common_len <= 0); 1639 1640 max_clock = common_len - 1; 1641 1642 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1643 pipe_config->has_pch_encoder = true; 1644 1645 pipe_config->has_drrs = false; 1646 if (IS_G4X(dev_priv) || port == PORT_A) 1647 pipe_config->has_audio = false; 1648 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1649 pipe_config->has_audio = intel_dp->has_audio; 1650 else 1651 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 1652 1653 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1654 struct drm_display_mode *panel_mode = 1655 intel_connector->panel.alt_fixed_mode; 1656 struct drm_display_mode *req_mode = _config->base.mode; 1657 1658 if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) 1659 panel_mode = intel_connector->panel.fixed_mode; 1660 1661 drm_mode_debug_printmodeline(panel_mode); 1662 1663 intel_fixed_panel_mode(panel_mode, adjusted_mode); 1664 1665 if (INTEL_GEN(dev_priv) >= 9) { 1666 int ret; 1667 ret = skl_update_scaler_crtc(pipe_config); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 if (HAS_GMCH_DISPLAY(dev_priv)) 1673 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1674 conn_state->scaling_mode); 1675 else 1676 intel_pch_panel_fitting(intel_crtc, pipe_config, 1677 conn_state->scaling_mode); 1678 } 1679 1680 if ((IS_VALLEYVIEW(dev_priv)
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
Hi Matt, Thank you for the patch! Yet something to improve: [auto build test ERROR on v4.16-rc4] [also build test ERROR on next-20180316] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/matthew-s-atwood-intel-com/drm-i915-make-edp-optimize-config/20180319-065307 config: x86_64-randconfig-x002-201811 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_compute_config': >> drivers/gpu/drm/i915/intel_dp.c:1729:6: error: 'dpcd' undeclared (first use >> in this function); did you mean 'dpll'? if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^~~~ dpll drivers/gpu/drm/i915/intel_dp.c:1729:6: note: each undeclared identifier is reported only once for each function it appears in >> drivers/gpu/drm/i915/intel_dp.c:1729:26: error: 'DPCD_REV_14' undeclared >> (first use in this function); did you mean 'BPF_REG_10'? if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ ^~~ BPF_REG_10 vim +1729 drivers/gpu/drm/i915/intel_dp.c 1607 1608 bool 1609 intel_dp_compute_config(struct intel_encoder *encoder, 1610 struct intel_crtc_state *pipe_config, 1611 struct drm_connector_state *conn_state) 1612 { 1613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1614 struct drm_display_mode *adjusted_mode = _config->base.adjusted_mode; 1615 struct intel_dp *intel_dp = enc_to_intel_dp(>base); 1616 enum port port = encoder->port; 1617 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1618 struct intel_connector *intel_connector = intel_dp->attached_connector; 1619 struct intel_digital_connector_state *intel_conn_state = 1620 to_intel_digital_connector_state(conn_state); 1621 int lane_count, clock; 1622 int min_lane_count = 1; 1623 int max_lane_count = intel_dp_max_lane_count(intel_dp); 1624 /* Conveniently, the link BW constants become indices with a shift...*/ 1625 int min_clock = 0; 1626 int max_clock; 1627 int bpp, mode_rate; 1628 int link_avail, link_clock; 1629 int common_len; 1630 uint8_t link_bw, rate_select; 1631 bool reduce_m_n = drm_dp_has_quirk(_dp->desc, 1632 DP_DPCD_QUIRK_LIMITED_M_N); 1633 1634 common_len = intel_dp_common_len_rate_limit(intel_dp, 1635 intel_dp->max_link_rate); 1636 1637 /* No common link rates between source and sink */ 1638 WARN_ON(common_len <= 0); 1639 1640 max_clock = common_len - 1; 1641 1642 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1643 pipe_config->has_pch_encoder = true; 1644 1645 pipe_config->has_drrs = false; 1646 if (IS_G4X(dev_priv) || port == PORT_A) 1647 pipe_config->has_audio = false; 1648 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1649 pipe_config->has_audio = intel_dp->has_audio; 1650 else 1651 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 1652 1653 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1654 struct drm_display_mode *panel_mode = 1655 intel_connector->panel.alt_fixed_mode; 1656 struct drm_display_mode *req_mode = _config->base.mode; 1657 1658 if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) 1659 panel_mode = intel_connector->panel.fixed_mode; 1660 1661 drm_mode_debug_printmodeline(panel_mode); 1662 1663 intel_fixed_panel_mode(panel_mode, adjusted_mode); 1664 1665 if (INTEL_GEN(dev_priv) >= 9) { 1666 int ret; 1667 ret = skl_update_scaler_crtc(pipe_config); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 if (HAS_GMCH_DISPLAY(dev_priv)) 1673 intel_gmch_panel_fitting(intel_crtc, pipe_config, 1674 conn_state->scaling_mode); 1675 else 1676 intel_pch_panel_fitting(intel_crtc, pipe_config, 1677
[Intel-gfx] [PATCH] drm/i915: make edp optimize config
From: Matt AtwoodPreviously it was assumed that eDP panels would advertise the lowest link rate required for their singular mode to function. With the introduction of more advanced features there are advantages to a panel advertising a higher rate then it needs for a its given mode. For panels that did, the driver previously used a higher rate then necessary for that mode. Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/intel_dp.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a2eeede..57b309c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1766,8 +1766,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, * configuration, and typically these values correspond to the * native resolution of the panel. */ - min_lane_count = max_lane_count; - min_clock = max_clock; + if(dpcd[DP_DPCD_REV] < DPCD_REV_14){ + min_lane_count = max_lane_count; + min_clock = max_clock; + } } for (; bpp >= 6*3; bpp -= 2*3) { -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
On Sat, Mar 10, 2018 at 12:07:34AM +, Atwood, Matthew S wrote: > On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote: > > On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > > > > > > From: Matt Atwood> > > > > > Previously it was assumed that eDP panels would advertise the > > > lowest link > > > rate required for their singular mode to function. With the > > > introduction > > > of more advanced features there are advantages to a panel > > > advertising a > > > higher rate then it needs for a its given mode. For panels that > > > did, the > > > driver previously used a higher rate then necessary for that mode. > > > > > > Signed-off-by: Matt Atwood > > > --- > > > drivers/gpu/drm/i915/intel_dp.c | 10 -- > > > 1 file changed, 10 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > b/drivers/gpu/drm/i915/intel_dp.c > > > index a2eeede..aa6d77d 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder > > > *encoder, > > > dev_priv->vbt.edp.bpp); > > > bpp = dev_priv->vbt.edp.bpp; > > > } > > > - > > > - /* > > > - * Use the maximum clock and number of lanes the > > > eDP panel > > > - * advertizes being capable of. The panels are > > > generally > > > - * designed to support only a single clock and > > > lane > > > - * configuration, and typically these values > > > correspond to the > > > - * native resolution of the panel. > > > - */ > > > - min_lane_count = max_lane_count; > > > - min_clock = max_clock; > > Please see my reply to Manasi's identical patch [1]. If we apply this > > as-is, it will regress and will be reverted. > > > > BR, > > Jani. > > > > > > [1] http://patchwork.freedesktop.org/patch/msgid/1520579339-14745-1- > > git-send-email-manasi.d.nav...@intel.com > to consolidate some of the information the bug that's referenced in > Manasi's patch is https://bugs.freedesktop.org/show_bug.cgi?id=73539. I > understand this bug as the following some panels may advertise a mode > that requires less then MAX_LANE_COUNT, however those panels would fail > if less lanes were used. > > When this bug was filed the compute config inner for loop iterated on > rate and the outer iterated on lanes; this is now flipped. It *should* > be the case that the lowest frequency with the max amount of lanes is > preferred. Given the opposite behavior of the alogorithm to select I > dont think we'd come across this again. Even if I'm wrong we could > still min_lane_count = max_lane count and let the clock optimize > itself. > > I guess my question is, is there also a bug where if MAX_RATE wasnt > used we saw a panel fail as well? Looking to eDP 1.4 spec I'm convinced that max link rate approach is the ideal for eDP 1.3 and older, regardless of the issues we had on previous attempts. But eDP 1.4 seems to introduce the new link rates flexibility and selection in order to provide improved system-specific link rate optimization and power efficiency. I believe what we want here is: - min_lane_count = max_lane_count; - min_clock = max_clock; + if (intel_dp->edp_dpcd[0] <= DP_EDP_13) { + min_lane_count = max_lane_count; + min_clock = max_clock; + } for me it seems that eDP 1.4 brings eDP link rates handling close to DP ones. So imho this move here should be safe. Besides, with this difference in place, we don't break the world and if new bugs appear we can work on those individually to figure out if we are missing something else and this block was only masking other issues. Thoughts? > > Matt > > > > > > > > > > } > > > > > > for (; bpp >= 6*3; bpp -= 2*3) { > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote: > On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > > > > From: Matt Atwood> > > > Previously it was assumed that eDP panels would advertise the > > lowest link > > rate required for their singular mode to function. With the > > introduction > > of more advanced features there are advantages to a panel > > advertising a > > higher rate then it needs for a its given mode. For panels that > > did, the > > driver previously used a higher rate then necessary for that mode. > > > > Signed-off-by: Matt Atwood > > --- > > drivers/gpu/drm/i915/intel_dp.c | 10 -- > > 1 file changed, 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index a2eeede..aa6d77d 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder > > *encoder, > > dev_priv->vbt.edp.bpp); > > bpp = dev_priv->vbt.edp.bpp; > > } > > - > > - /* > > - * Use the maximum clock and number of lanes the > > eDP panel > > - * advertizes being capable of. The panels are > > generally > > - * designed to support only a single clock and > > lane > > - * configuration, and typically these values > > correspond to the > > - * native resolution of the panel. > > - */ > > - min_lane_count = max_lane_count; > > - min_clock = max_clock; > Please see my reply to Manasi's identical patch [1]. If we apply this > as-is, it will regress and will be reverted. > > BR, > Jani. > > > [1] http://patchwork.freedesktop.org/patch/msgid/1520579339-14745-1- > git-send-email-manasi.d.nav...@intel.com to consolidate some of the information the bug that's referenced in Manasi's patch is https://bugs.freedesktop.org/show_bug.cgi?id=73539. I understand this bug as the following some panels may advertise a mode that requires less then MAX_LANE_COUNT, however those panels would fail if less lanes were used. When this bug was filed the compute config inner for loop iterated on rate and the outer iterated on lanes; this is now flipped. It *should* be the case that the lowest frequency with the max amount of lanes is preferred. Given the opposite behavior of the alogorithm to select I dont think we'd come across this again. Even if I'm wrong we could still min_lane_count = max_lane count and let the clock optimize itself. I guess my question is, is there also a bug where if MAX_RATE wasnt used we saw a panel fail as well? Matt > > > > > > } > > > > for (; bpp >= 6*3; bpp -= 2*3) { ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > From: Matt Atwood> > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are advantages to a panel advertising a > higher rate then it needs for a its given mode. For panels that did, the > driver previously used a higher rate then necessary for that mode. > > Signed-off-by: Matt Atwood > --- > drivers/gpu/drm/i915/intel_dp.c | 10 -- > 1 file changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index a2eeede..aa6d77d 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, > dev_priv->vbt.edp.bpp); > bpp = dev_priv->vbt.edp.bpp; > } > - > - /* > - * Use the maximum clock and number of lanes the eDP panel > - * advertizes being capable of. The panels are generally > - * designed to support only a single clock and lane > - * configuration, and typically these values correspond to the > - * native resolution of the panel. > - */ > - min_lane_count = max_lane_count; > - min_clock = max_clock; Please see my reply to Manasi's identical patch [1]. If we apply this as-is, it will regress and will be reverted. BR, Jani. [1] http://patchwork.freedesktop.org/patch/msgid/1520579339-14745-1-git-send-email-manasi.d.nav...@intel.com > } > > for (; bpp >= 6*3; bpp -= 2*3) { -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config
Hi Matt, Minor commit message nits. On Thu, Mar 08, 2018 at 05:17:38PM -0800, matthew.s.atw...@intel.com wrote: > From: Matt Atwood> > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are advantages to a panel advertising a > higher rate then s/then/than > it needs for a its given mode. Don't need "its" here. > For panels that did, the > driver previously used a higher rate then necessary for that mode. > s/then/than > Signed-off-by: Matt Atwood Tested-by: Benson Leung Tested this on a panel and system with the following source and sink rates: [1.623225] [drm:intel_dp_print_rates] source rates: 162000, 216000, 27, 324000, 432000, 54 [1.623230] [drm:intel_dp_print_rates] sink rates: 162000, 216000, 243000, 27, 324000, 432000, 54 [1.623234] [drm:intel_dp_print_rates] common rates: 162000, 216000, 27, 324000, 432000, 54 Prior to this patch, the driver would pick and train at 54: [2.865653] [drm:intel_dp_start_link_train] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 54, Lane count = 4 After this patch, the driver picks and trains at 324000, which is enough for the panel's native mode: [5.359499] [drm:intel_dp_start_link_train] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 324000, Lane count = 4 Thanks! Benson -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. ble...@google.com Chromium OS Project ble...@chromium.org signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: make edp optimize config
From: Matt AtwoodPreviously it was assumed that eDP panels would advertise the lowest link rate required for their singular mode to function. With the introduction of more advanced features there are advantages to a panel advertising a higher rate then it needs for a its given mode. For panels that did, the driver previously used a higher rate then necessary for that mode. Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/intel_dp.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a2eeede..aa6d77d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, dev_priv->vbt.edp.bpp); bpp = dev_priv->vbt.edp.bpp; } - - /* -* Use the maximum clock and number of lanes the eDP panel -* advertizes being capable of. The panels are generally -* designed to support only a single clock and lane -* configuration, and typically these values correspond to the -* native resolution of the panel. -*/ - min_lane_count = max_lane_count; - min_clock = max_clock; } for (; bpp >= 6*3; bpp -= 2*3) { -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx