> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register
> writes for legacy LUT
>
> From: Ville Syrjälä
>
> The DSB has problems writing the legacy LUT. The two workarounds I've
> discoverted are:
> - write each entry twice back to back
> - use non-posted writes
>
> Let's use non-posted writes as that seems a bit more standard.
Change looks good but I feel it will be good to get this documented in spec.
Not able to locate any reference.
Anyways, with empirical data based on your findings no concern as such.
Reviewed-by: Uma Shankar
> TODO: measure which is faster
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 077e45372dab..b3dd4013d058 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1265,9 +1265,20 @@ static void ilk_load_lut_8(const struct
> intel_crtc_state
> *crtc_state,
>
> lut = blob->data;
>
> + /*
> + * DSB fails to correctly load the legacy LUT
> + * unless we either write each entry twice,
> + * or use non-posted writes
> + */
> + if (crtc_state->dsb)
> + intel_dsb_nonpost_start(crtc_state->dsb);
> +
> for (i = 0; i < 256; i++)
> ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
> i9xx_lut_8([i]));
> +
> + if (crtc_state->dsb)
> + intel_dsb_nonpost_end(crtc_state->dsb);
> }
>
> static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
> --
> 2.39.3
