[PATCH V6 8/9] clk: imx: implement new clk_hw based APIs
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v4:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 62 +++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned
int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 3886979..cf0596d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char
*name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name,
int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char
*name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char
*name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long
flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char
*parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -143,6 +175,13 @@ static inline struct clk *imx_clk_gate_flags(const char
*name, const char *paren
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char
*parent,
+
[PATCH V6 9/9] clk: imx: add imx7ulp clk driver
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v5->v6:
* sosc/firc/dpll/ddr clock should use divider table as they're not 1:1
v4->v5:
* clk-composite API name changed accordingly
v3->v4:
* update after changing scg and pcc into separete nodes according to
Rob's suggestion
v2->v3:
* no changes
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 220 ++
2 files changed, 221 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index a5cab3e..615b413 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -30,4 +30,5 @@ obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
new file mode 100644
index 000..3b7507f
--- /dev/null
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static const char * const pll_pre_sels[] = { "sosc", "firc", };
+static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1",
"spll_pfd2", "spll_pfd3", };
+static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
+static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1",
"apll_pfd2", "apll_pfd3", };
+static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
+static const char * const scs_sels[] = { "dummy", "sosc", "sirc",
"firc", "dummy", "apll_sel", "spll_sel", "upll", };
+static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
+static const char * const nic_sels[] = { "firc", "ddr_clk", };
+static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+
+/* used by sosc/sirc/firc/ddr/spll/apll dividers */
+static const struct clk_div_table ulp_div_table[] = {
+ { .val = 1, .div = 1, },
+ { .val = 2, .div = 2, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 8, },
+ { .val = 5, .div = 16, },
+ { .val = 6, .div = 32, },
+ { .val = 7, .div = 64, },
+};
+
+static void __init imx7ulp_clk_scg1_init(struct device_node *np)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ void __iomem *base;
+
+ clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
+ IMX7ULP_CLK_SCG1_END, GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_SCG1_END;
+ clks = clk_data->hws;
+
+ clks[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+
+ clks[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
+ clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
+ clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
+ clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
+ clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
+
[PATCH V6 6/9] dt-bindings: clock: add imx7ulp clock binding doc
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* fix a typo that clock-name -> clock-names
* one compatible string per line
* add input clocks for pcc2/3
v3->v4:
* make scg, pcc separate nodes according to Rob's suggestion
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt| 104
include/dt-bindings/clock/imx7ulp-clock.h | 109 +
2 files changed, 213 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 000..a4f8cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,104 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+System Clock Generation (SCG) modules:
+-
+The System Clock Generation (SCG) is responsible for clock generation
+and distribution across this device. Functions performed by the SCG
+include: clock reference selection, generation of clock used to derive
+processor, system, peripheral bus and external memory interface clocks,
+source selection for peripheral clocks and control of power saving
+clock gating mode.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-scg1".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-names: Should contain the following clock names:
+ "rosc", "sosc", "sirc", "firc", "upll", "mpll".
+
+Peripheral Clock Control (PCC) modules:
+-
+The Peripheral Clock Control (PCC) is responsible for clock selection,
+optional division and clock gating mode for peripherals in their
+respected power domain
+
+Required properties:
+- compatible: Should be one of:
+ "fsl,imx7ulp-pcc2",
+ "fsl,imx7ulp-pcc3".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-names: Should contain the following clock names:
+ "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
+ "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
+ "mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs of each module.
+
+Examples:
+
+#include
+
+scg1: scg1@403e {
+ compatible = "fsl,imx7ulp-scg1;
+ reg = <0x403e 0x1>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+<&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+pcc2: pcc2@403f {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f 0x1>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+<&scg1 IMX7ULP_CLK_NIC1_DIV>,
+<&scg1 IMX7ULP_CLK_DDR_DIV>,
+<&scg1 IMX7ULP_CLK_APLL_PFD2>,
+<&scg1 IMX7ULP_CLK_APLL_PFD1>,
+<&scg1 IMX7ULP_CLK_APLL_PFD0>,
+<&scg1 IMX7ULP_CLK_UPLL>,
+<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+<&scg1 IMX7ULP_CLK_MIPI_PLL>,
+<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+<&scg1 IMX7ULP_CLK_ROSC>,
+<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+
[PATCH V6 3/9] clk: imx: add pllv4 support
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* other minor changes
---
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-pllv4.c | 182
drivers/clk/imx/clk.h | 3 +
3 files changed, 186 insertions(+)
create mode 100644 drivers/clk/imx/clk-pllv4.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 077e732..4cac28b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,6 +12,7 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
+ clk-pllv4.o \
clk-pfd.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
new file mode 100644
index 000..67c64c7
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/* PLL Control Status Register (xPLLCSR) */
+#define PLL_CSR_OFFSET 0x0
+#define PLL_VLDBIT(24)
+#define PLL_EN BIT(0)
+
+/* PLL Configuration Register (xPLLCFG) */
+#define PLL_CFG_OFFSET 0x08
+#define BP_PLL_MULT16
+#define BM_PLL_MULT(0x7f << 16)
+
+/* PLL Numerator Register (xPLLNUM) */
+#define PLL_NUM_OFFSET 0x10
+
+/* PLL Denominator Register (xPLLDENOM) */
+#define PLL_DENOM_OFFSET 0x14
+
+struct clk_pllv4 {
+ struct clk_hw hw;
+ void __iomem*base;
+};
+
+/* Valid PLL MULT Table */
+static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+
+#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
+{
+ u32 csr;
+
+ return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
+ csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pllv4_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ if (readl_relaxed(pll->base) & PLL_EN)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 div;
+
+ div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ div &= BM_PLL_MULT;
+ div >>= BP_PLL_MULT;
+
+ return parent_rate * div;
+}
+
+static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long round_rate, i;
+
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate)
+ return round_rate;
+ }
+
+ return round_rate;
+}
+
+static bool clk_pllv4_is_valid_mult(unsigned int mult)
+{
+ int i;
+
+ /* check if mult is in valid MULT table */
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
+
+ return false;
+}
+
+static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 val, mult;
+
+ mult = rate / parent_rate;
+
+ if (!clk_pllv4_is_valid_mult(mult))
+ return -EINVAL;
+
+ val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ val &= ~BM_PLL_MULT;
+ val |= mult << BP_PLL_MULT;
+ writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
+
+ return 0;
+}
+
+static int clk_pllv4_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val |= PLL_EN;
+ writel_relaxed(val, pll->base);
+
+ return clk_pllv4_wait_lock(pll);
+}
+
+static void clk_pllv4_disable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val &= ~PLL_EN;
+ writel_relaxed(v
[PATCH V6 4/9] clk: imx: add pfdv2 support
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile| 3 +-
drivers/clk/imx/clk-pfdv2.c | 201
drivers/clk/imx/clk.h | 3 +
3 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 4cac28b..e7248de 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -13,7 +13,8 @@ obj-y += \
clk-pllv2.o \
clk-pllv3.o \
clk-pllv4.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-pfdv2.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
new file mode 100644
index 000..afb2904
--- /dev/null
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/**
+ * struct clk_pfdv2 - IMX PFD clock
+ * @clk_hw:clock source
+ * @reg: PFD register address
+ * @gate_bit: Gate bit offset
+ * @vld_bit: Valid bit offset
+ * @frac_off: PLL Fractional Divider offset
+ */
+
+struct clk_pfdv2 {
+ struct clk_hw hw;
+ void __iomem*reg;
+ u8 gate_bit;
+ u8 vld_bit;
+ u8 frac_off;
+};
+
+#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
+
+#define CLK_PFDV2_FRAC_MASK 0x3f
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static DEFINE_SPINLOCK(pfd_lock);
+
+static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
+{
+ u32 val;
+
+ return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+ 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pfdv2_enable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return clk_pfdv2_wait(pfd);
+}
+
+static void clk_pfdv2_disable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val |= pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+}
+
+static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
+ & CLK_PFDV2_FRAC_MASK;
+
+ if (!frac) {
+ pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
+clk_hw_get_name(hw));
+ return 0;
+ }
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfdv2_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+
+ if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+ return 0;
+
+ return 1;
+}
+
+static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u64 tmp = parent_rate;
+ u32 val;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~(CLK_PFDV2_FRAC_MAS
[PATCH V6 5/9] clk: imx: add imx7ulp composite clk support
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* rename to clk-composite-7ulp.c as we have another
clk-composite-8m.c, function name also changed accordingly
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove an unneeded blank line change
* use clk_hw_register
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-composite-7ulp.c | 85
drivers/clk/imx/clk.h| 6 +++
3 files changed, 92 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite-7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index e7248de..a5cab3e 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-composite-7ulp.o \
clk-divider-gate.o \
clk-fixup-div.o \
clk-fixup-mux.o \
diff --git a/drivers/clk/imx/clk-composite-7ulp.c
b/drivers/clk/imx/clk-composite-7ulp.c
new file mode 100644
index 000..22f679c
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ */
+
+#include
+#include
+#include
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+#define PCG_CGC_SHIFT 30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK BIT(3)
+#define PCG_PCD_SHIFT 0
+#define PCG_PCD_WIDTH 3
+#define PCG_PCD_MASK 0x7
+
+struct clk_hw *imx7ulp_clk_composite(const char *name,
+const char * const *parent_names,
+int num_parents, bool mux_present,
+bool rate_present, bool gate_present,
+void __iomem *reg)
+{
+ struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+ struct clk_fractional_divider *fd = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk_hw *hw;
+
+ if (mux_present) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ }
+
+ if (rate_present) {
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+ fd_hw = &fd->hw;
+ fd->reg = reg;
+ fd->mshift = PCG_FRAC_SHIFT;
+ fd->mwidth = PCG_FRAC_WIDTH;
+ fd->mmask = PCG_FRAC_MASK;
+ fd->nshift = PCG_PCD_SHIFT;
+ fd->nwidth = PCG_PCD_WIDTH;
+ fd->nmask = PCG_PCD_MASK;
+ fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+ }
+
+ if (gate_present) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ kfree(fd);
+ return ERR_PTR(-ENOMEM);
+ }
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, fd_hw,
+ &clk_fractional_divider_ops, gate_hw,
+ &clk_gate_ops, CLK_SET_RATE_GATE |
+ CLK_SET_PARENT_GATE);
+ if (IS_ERR(hw)) {
+ kfree(mux);
+ kfree(fd);
+ kfree(gate);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index ebeb754..2e3bcfa 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -71,6 +71,12 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem
*reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
const char **parent_names, int num_parents);
+struct clk_hw *imx7ulp_clk_composite(const char *name,
+const char * const *parent_names,
+int num_parents, bool mux_present,
+bool rate_present, bool gate_present,
+void __iomem *reg);
+
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void __iomem *
[PATCH V6 0/9] clk: add imx7ulp clk support
This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. Note: this series only adds A7 clock domain support as M4 clock domain will be handled by M4 seperately. Change Log: v5->v6: * move gatable divider from common divider to imx specfic folder(suggested by Michael) * a small update of PATCH 9 for ddr/firc/dpll/sosc clocks to use divider table v4->v5: * rename to clk-composite-7ulp.c as we have another clk-composite-8m.c, function name also changed accordingly * binding doc updated with adding input clocks for PCC module v3->v4: * update after changing scg and pcc into separete nodes according to Rob's suggestion v2->v3: * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy Others no changes. v1->v2: * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers * use clk_hw apis to register clocks * use of_clk_add_hw_provider * split the clocks register process into two parts: early part for possible timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for the left normal peripheral clocks registered by a platform driver. Dong Aisheng (9): clk: imx: add gatable clock divider support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add pllv4 support clk: imx: add pfdv2 support clk: imx: add imx7ulp composite clk support dt-bindings: clock: add imx7ulp clock binding doc clk: imx: make mux parent strings const clk: imx: implement new clk_hw based APIs clk: imx: add imx7ulp clk driver .../devicetree/bindings/clock/imx7ulp-clock.txt| 104 ++ drivers/clk/clk-fractional-divider.c | 10 + drivers/clk/imx/Makefile | 7 +- drivers/clk/imx/clk-busy.c | 2 +- drivers/clk/imx/clk-composite-7ulp.c | 85 drivers/clk/imx/clk-divider-gate.c | 219 drivers/clk/imx/clk-fixup-mux.c| 2 +- drivers/clk/imx/clk-imx7ulp.c | 220 + drivers/clk/imx/clk-pfdv2.c| 201 +++ drivers/clk/imx/clk-pllv4.c| 182 + drivers/clk/imx/clk.c | 22 +++ drivers/clk/imx/clk.h | 96 - include/dt-bindings/clock/imx7ulp-clock.h | 109 ++ include/linux/clk-provider.h | 8 + 14 files changed, 1257 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 drivers/clk/imx/clk-composite-7ulp.c create mode 100644 drivers/clk/imx/clk-divider-gate.c create mode 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.7.4
[PATCH V6 1/9] clk: imx: add gatable clock divider support
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v5->v6:
* move gatable divider code into imx specific clock folder as suggested
by Michael. Patch title also updated accordingly.
v4->v5:
* no changes
v3->v4:
* no changes
v2->v3:
* split normal and gate ops
* fix the possible racy
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-divider-gate.c | 219 +
drivers/clk/imx/clk.h | 4 +
3 files changed, 224 insertions(+)
create mode 100644 drivers/clk/imx/clk-divider-gate.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 8c3baa7..077e732 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-divider-gate.o \
clk-fixup-div.o \
clk-fixup-mux.o \
clk-gate-exclusive.o \
diff --git a/drivers/clk/imx/clk-divider-gate.c
b/drivers/clk/imx/clk-divider-gate.c
new file mode 100644
index 000..b48fba2
--- /dev/null
+++ b/drivers/clk/imx/clk-divider-gate.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP.
+ * Dong Aisheng
+ */
+
+#include
+#include
+#include
+#include
+
+struct clk_divider_gate {
+ struct clk_divider divider;
+ u32 cached_val;
+};
+
+static inline struct clk_divider_gate *to_clk_divider_gate(struct clk_hw *hw)
+{
+ struct clk_divider *div = to_clk_divider(hw);
+
+ return container_of(div, struct clk_divider_gate, divider);
+}
+
+static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+ struct clk_divider *div = to_clk_divider(hw);
+ unsigned int val;
+
+ val = clk_readl(div->reg) >> div->shift;
+ val &= clk_div_mask(div->width);
+ if (!val)
+ return 0;
+
+ return divider_recalc_rate(hw, parent_rate, val, div->table,
+ div->flags, div->width);
+}
+
+static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
+ struct clk_divider *div = to_clk_divider(hw);
+ unsigned long flags = 0;
+ unsigned int val;
+
+ spin_lock_irqsave(div->lock, flags);
+
+ if (!clk_hw_is_enabled(hw)) {
+ val = div_gate->cached_val;
+ } else {
+ val = clk_readl(div->reg) >> div->shift;
+ val &= clk_div_mask(div->width);
+ }
+
+ spin_unlock_irqrestore(div->lock, flags);
+
+ if (!val)
+ return 0;
+
+ return divider_recalc_rate(hw, parent_rate, val, div->table,
+ div->flags, div->width);
+}
+
+static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return clk_divider_ops.round_rate(hw, rate, prate);
+}
+
+static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider_gate *div_gate = to_clk_divider_gate(hw);
+ struct clk_divider *div = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, div->table,
+ div->width, div->flags);
+ if (value < 0)
+ return value;
+
+ spin_lock_irqsave(div->lock, flags);
+
+ if (clk_hw_is_enabled(hw)) {
+ val = clk_readl(div->reg);
+ val &= ~(clk_div_mask(div->width) << div->shift);
+
[PATCH V6 7/9] clk: imx: make mux parent strings const
As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base +
0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v4: no changes
---
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk.h | 18 +++---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 9903652..e695622 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -154,7 +154,7 @@ static const struct clk_ops clk_busy_mux_ops = {
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents)
+const char * const *parent_names, int num_parents)
{
struct clk_busy_mux *busy;
struct clk *clk;
diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index c9b327e..44817c1 100644
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -70,7 +70,7 @@ static const struct clk_ops clk_fixup_mux_ops = {
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 2e3bcfa..3886979 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,7 +69,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char
*parent_name,
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents);
+const char * const *parent_names, int num_parents);
struct clk_hw *imx7ulp_clk_composite(const char *name,
const char * const *parent_names,
@@ -82,7 +82,7 @@ struct clk *imx_clk_fixup_divider(const char *name, const
char *parent,
void (*fixup)(u32 *val));
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
static inline struct clk *imx_clk_fixed(const char *name, int rate)
@@ -91,7 +91,8 @@ static inline struct clk *imx_clk_fixed(const char *name, int
rate)
}
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
@@ -204,7 +205,8 @@ static inline struct clk *imx_clk_gate4(const char *name,
const char *parent,
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
@@ -212,7 +214,8 @@ static inline struct clk *imx_clk_mux(const char *name,
void __iomem *reg,
}
static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
@@ -220,8
[PATCH V6 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++
include/linux/clk-provider.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c
b/drivers/clk/clk-fractional-divider.c
index fdf625f..7ccde6b 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m++;
+ n++;
+ }
+
if (!n || !m)
return parent_rate;
@@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned
long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m--;
+ n--;
+ }
+
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08b1aa7..bee6453 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -594,6 +594,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
+ * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
+ * is set then the numerator and denominator are both the value read
+ * plus one.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -613,6 +619,8 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+#define CLK_FRAC_DIVIDER_ZERO_BASEDBIT(0)
+
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
--
2.7.4
RE: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
Hi Michael,
> -Original Message-
> From: Michael Turquette [mailto:mturque...@baylibre.com]
[...]
> Hi Dong,
>
> Quoting A.s. Dong (2018-10-21 06:10:48)
> > For dividers with zero indicating clock is disabled, instead of giving
> > a warning each time like "clkx: Zero divisor and
> > CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce
> enable/disable function for it.
> > e.g.
> > 000b - Clock disabled
> > 001b - Divide by 1
> > 010b - Divide by 2
> > ...
>
> I feel bad to NAK this patch after it's been on the list for so long,
Never mind, I feel better than no response about it. :-)
> but this
> implementation really should belong in your hardware specific clock provider
> driver.
>
Got your point.
> This patch expands clk-divider to also be a gate, which is a non-starter.
> Basic
> clock types were meant to remain basic. I'm already imagining how this
> precedent would cause other submissions: "why should I use composite clock
> when we can just add new clk_ops to the basic clock types!" :-(
>
> Also the implementation becomes cleaner when you don't have to make it
> coexist with clk-divider.c. You can drop the flags and just implement a
> machine
> specific clock type that combines gates and dividers.
Sound good to me. The original purpose to put it in framework is in order to
save possible duplicated codes for a similar SoC as the implementation actually
is HW independent. But I think we could start from putting it in machine code
first.
Thanks for the suggestion.
Will update soon and resend.
Regards
Dong Aisheng
>
> Best regards,
> Mike
>
> >
> > Set rate when the clk is disabled will cache the rate request and only
> > when the clk is enabled will the driver actually program the hardware
> > to have the requested divider value. Similarly, when the clk is
> > disabled we'll write a 0 there, but when the clk is enabled we'll
> > restore whatever rate
> > (divider) was chosen last.
> >
> > It does mean that recalc rate will be sort of odd, because when the
> > clk is off it will return 0, and when the clk is on it will return the
> > right rate.
> > So to make things work, we'll need to return the cached rate in recalc
> > rate when the clk is off and read the hardware when the clk is on.
> >
> > NOTE for the default off divider, the recalc rate will still return 0
> > as there's still no proper preset rate. Enable such divider will give
> > user a reminder error message.
> >
> > Cc: Stephen Boyd
> > Cc: Michael Turquette
> > Cc: Shawn Guo
> > Signed-off-by: Dong Aisheng
> >
> > ---
> > ChangeLog:
> > v3->v4:
> > * no changes
> > v2->v3:
> > * split normal and gate ops
> > * fix the possible racy
> > v1->v2:
> > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
> > ---
> > drivers/clk/clk-divider.c| 152
> +++
> > include/linux/clk-provider.h | 9 +++
> > 2 files changed, 161 insertions(+)
> >
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index b6234a5..b3566fd 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -122,6 +122,9 @@ unsigned long divider_recalc_rate(struct clk_hw
> > *hw, unsigned long parent_rate,
> >
> > div = _get_div(table, val, flags, width);
> > if (!div) {
> > + if (flags & CLK_DIVIDER_ZERO_GATE)
> > + return 0;
> > +
> > WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> > "%s: Zero divisor and
> CLK_DIVIDER_ALLOW_ZERO not set\n",
> > clk_hw_get_name(hw)); @@ -145,6 +148,34
> @@
> > static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> >divider->flags, divider->width); }
> >
> > +static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
> > + unsigned long
> > +parent_rate) {
> > + struct clk_divider *divider = to_clk_divider(hw);
> > + unsigned long flags = 0;
> > + unsigned int val;
> > +
> > + if (divider->lock)
> > + spin_lock_irqsave(divider->lock, flags);
> > + else
> > + __acquire(divider->lock);
> > +
> > + if (!clk_hw_is_enabled(hw)) {
> > + val = divider->cac
RE: [PATCH] pinctrl: imx: make sure that maps are fully initialized
Hi Martin,
> -Original Message-
> From: Martin Kaiser [mailto:mar...@kaiser.cx]
> Sent: Sunday, November 11, 2018 1:37 AM
[...]
>
> The commit that added scu based pinctrl support introduced a regression for
> the mmio case. In the for-loop where the maps are initialized, we end up
> creating a partially initialized map in some cases. This causes a kernel panic
> when such a map is used at a later stage.
>
> When scu is not used and and a pin uses the default pad configuration, the
> current code sets the map's type and data.configs.group_or_pin but no configs
> or num_configs are set. The previous code without scu support did not create a
> new map at all in this case and did not increment the counter.
>
> Fix this by setting the map type and data.configs.group_or_pin only when a
> configuration was set before, either by scu or by mmio using a non-default pad
> config. Increment the counter only if a new map was created.
>
> Fixes: b96eea718bf6 ("pinctrl: fsl: add scu based pinctrl support")
> Cc: A.s. Dong
> Signed-off-by: Martin Kaiser
Thanks for reporting this issue.
The original code intended to save 3 common lines for both SCU and MMIO pads,
but it did change the code logic a bit which resulted in a regression specificly
for NO_PAD_CTL cases used on a few legacy boards. (NO_PAD_CTL is deprecated
for new boards dts).
I agree with Leonard that this fixes is not so good.
A simpler and proper fix could be:
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index b704f7c..ab962f5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -109,6 +109,15 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
+
+ /*
+* We only create config maps for SCU pads or MMIO pads that
+* are not using the default config (a.k.a NO_PAD_CTL)
+*/
+ if (!(info->flags & IMX_USE_SCU) &&
+ (pin->conf.mmio.config & IMX_NO_PAD_CTL))
+ continue;
+
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
@@ -121,7 +130,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
new_map[j].data.configs.configs =
(unsigned long *)&pin->conf.scu;
new_map[j].data.configs.num_configs = 2;
- } else if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) {
+ } else {
new_map[j].data.configs.configs =
&pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
@@ -550,6 +559,8 @@ static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl
*ipctl,
pin_mmio->config = config & ~IMX_PAD_SION;
}
+ *list_p = list; //thanks to Leonard for pointing out this
+
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
pin_mmio->mux_mode, pin_mmio->config);
As you both had a patch, i'm not sure who i'm going to expect for a updated one,
so I would send it my own with both of your tags.
Thanks for the effort.
Regards
Dong Aisheng
> ---
>
> A crash looks like this
>
> [4.028525] Unable to handle kernel NULL pointer dereference at virtual
> address
> [4.036667] pgd = (ptrval)
> [4.039505] [] *pgd=
> [4.043162] Internal error: Oops: 5 [#1] ARM
> [4.047466] Modules linked in:
> [4.050582] CPU: 0 PID: 1 Comm: swapper Not tainted
> 4.20.0-rc1-next-20181106+ #2269
> [4.058270] Hardware name: Freescale i.MX25 (Device Tree Support)
> [4.064456] PC is at strcmp+0xc/0x40
> [4.068111] LR is at create_pinctrl+0x104/0x36c
> [4.072680] pc : []lr : []psr: 6013
> [4.078980] sp : d38bbce8 ip : d38bbcf8 fp : d38bbcf4
> [4.084236] r10: d3b2e0e0 r9 : d3b2e0c0 r8 :
> [4.089494] r7 : d3b2e238 r6 : d3b2e1c0 r5 : r4 :
> d3b0df00
> [4.096054] r3 : 85981bcd r2 : 85981bcd r1 : d3a729e0 r0 :
>
> [4.102615] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM
> Segment none
> [4.109786] Control: 0005317f Table: 80004000 DAC: 0053
> [4.115569] Process swapper (pid: 1, stack limit = 0x(ptrval))
> [4.121437] Stack: (0xd38bbce8 to 0xd38bc000)
> [4.125849] bce0: d38bbd3c d38bbcf8 c0220bc8
>
RE: [PATCH v9 3/5] clk: imx: add SCCG PLL type
Hi Stephen, [...] > > I already sent the 12th version of this current patch series and I > > would really like to get this in ASAP so that the booting up of imx8mq will > not be delayed. > > > > Ok. Well we're in rc1 right now, and so we're not merging new drivers into > mainline. I can merge the clk driver into clk-next, but you'll have to wait > for the > stabilization period to end (approximately 6 or 7 weeks) before this can get > into the next kernel version. It will be in linux-next much sooner of course. That would be great if you can help that. We're now working with SUSE to enable i.MX8 support. Their criteria is only backporting patches which must be at least in maintainer's next tree already. So either picked up by you or Shawn would help a lot on it. BTW, one simple question is that because MX8MQ DTS patches depends on this clock driver series. How would you suggest this series to go through your tree or Shawn's tree? Regards Dong Aisheng
[PATCH V5 3/9] clk: imx: add pllv4 support
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* other minor changes
---
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-pllv4.c | 182
drivers/clk/imx/clk.h | 3 +
3 files changed, 186 insertions(+)
create mode 100644 drivers/clk/imx/clk-pllv4.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 8c3baa7..bfe31bf 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,6 +11,7 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
+ clk-pllv4.o \
clk-pfd.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
new file mode 100644
index 000..67c64c7
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/* PLL Control Status Register (xPLLCSR) */
+#define PLL_CSR_OFFSET 0x0
+#define PLL_VLDBIT(24)
+#define PLL_EN BIT(0)
+
+/* PLL Configuration Register (xPLLCFG) */
+#define PLL_CFG_OFFSET 0x08
+#define BP_PLL_MULT16
+#define BM_PLL_MULT(0x7f << 16)
+
+/* PLL Numerator Register (xPLLNUM) */
+#define PLL_NUM_OFFSET 0x10
+
+/* PLL Denominator Register (xPLLDENOM) */
+#define PLL_DENOM_OFFSET 0x14
+
+struct clk_pllv4 {
+ struct clk_hw hw;
+ void __iomem*base;
+};
+
+/* Valid PLL MULT Table */
+static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+
+#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
+{
+ u32 csr;
+
+ return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
+ csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pllv4_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ if (readl_relaxed(pll->base) & PLL_EN)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 div;
+
+ div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ div &= BM_PLL_MULT;
+ div >>= BP_PLL_MULT;
+
+ return parent_rate * div;
+}
+
+static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long round_rate, i;
+
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate)
+ return round_rate;
+ }
+
+ return round_rate;
+}
+
+static bool clk_pllv4_is_valid_mult(unsigned int mult)
+{
+ int i;
+
+ /* check if mult is in valid MULT table */
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
+
+ return false;
+}
+
+static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 val, mult;
+
+ mult = rate / parent_rate;
+
+ if (!clk_pllv4_is_valid_mult(mult))
+ return -EINVAL;
+
+ val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ val &= ~BM_PLL_MULT;
+ val |= mult << BP_PLL_MULT;
+ writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
+
+ return 0;
+}
+
+static int clk_pllv4_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val |= PLL_EN;
+ writel_relaxed(val, pll->base);
+
+ return clk_pllv4_wait_lock(pll);
+}
+
+static void clk_pllv4_disable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val &= ~PLL_EN;
+ writel_relaxed(v
[PATCH V5 8/9] clk: imx: implement new clk_hw based APIs
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v4:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 62 +++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned
int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 290d4b2..75ad05b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char
*name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name,
int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char
*name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char
*name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long
flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char
*parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -143,6 +175,13 @@ static inline struct clk *imx_clk_gate_flags(const char
*name, const char *paren
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char
*parent,
+
[PATCH V5 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++
include/linux/clk-provider.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c
b/drivers/clk/clk-fractional-divider.c
index fdf625f..7ccde6b 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m++;
+ n++;
+ }
+
if (!n || !m)
return parent_rate;
@@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned
long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m--;
+ n--;
+ }
+
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08f135a..90d7c26 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -603,6 +603,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
+ * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
+ * is set then the numerator and denominator are both the value read
+ * plus one.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -622,6 +628,8 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+#define CLK_FRAC_DIVIDER_ZERO_BASEDBIT(0)
+
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
--
2.7.4
[PATCH V5 4/9] clk: imx: add pfdv2 support
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile| 3 +-
drivers/clk/imx/clk-pfdv2.c | 201
drivers/clk/imx/clk.h | 3 +
3 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index bfe31bf..e5b0d42 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,8 @@ obj-y += \
clk-pllv2.o \
clk-pllv3.o \
clk-pllv4.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-pfdv2.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
new file mode 100644
index 000..afb2904
--- /dev/null
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/**
+ * struct clk_pfdv2 - IMX PFD clock
+ * @clk_hw:clock source
+ * @reg: PFD register address
+ * @gate_bit: Gate bit offset
+ * @vld_bit: Valid bit offset
+ * @frac_off: PLL Fractional Divider offset
+ */
+
+struct clk_pfdv2 {
+ struct clk_hw hw;
+ void __iomem*reg;
+ u8 gate_bit;
+ u8 vld_bit;
+ u8 frac_off;
+};
+
+#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
+
+#define CLK_PFDV2_FRAC_MASK 0x3f
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static DEFINE_SPINLOCK(pfd_lock);
+
+static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
+{
+ u32 val;
+
+ return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+ 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pfdv2_enable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return clk_pfdv2_wait(pfd);
+}
+
+static void clk_pfdv2_disable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val |= pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+}
+
+static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
+ & CLK_PFDV2_FRAC_MASK;
+
+ if (!frac) {
+ pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
+clk_hw_get_name(hw));
+ return 0;
+ }
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfdv2_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+
+ if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+ return 0;
+
+ return 1;
+}
+
+static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u64 tmp = parent_rate;
+ u32 val;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~(CLK_PFDV2_FRAC_MAS
[PATCH V5 9/9] clk: imx: add imx7ulp clk driver
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* clk-composite API name changed accordingly
v3->v4:
* update after changing scg and pcc into separete nodes according to
Rob's suggestion
v2->v3:
* no changes
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 209 ++
2 files changed, 210 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index c44d3d4..98ec8ed 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -29,4 +29,5 @@ obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
new file mode 100644
index 000..6d2e3ef
--- /dev/null
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static const char * const pll_pre_sels[] = { "sosc", "firc", };
+static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1",
"spll_pfd2", "spll_pfd3", };
+static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
+static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1",
"apll_pfd2", "apll_pfd3", };
+static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
+static const char * const scs_sels[] = { "dummy", "sosc", "sirc",
"firc", "dummy", "apll_sel", "spll_sel", "upll", };
+static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
+static const char * const nic_sels[] = { "firc", "ddr_clk", };
+static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+
+static void __init imx7ulp_clk_scg1_init(struct device_node *np)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ void __iomem *base;
+
+ clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
+ IMX7ULP_CLK_SCG1_END, GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_SCG1_END;
+ clks = clk_data->hws;
+
+ clks[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+
+ clks[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
+ clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
+ clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
+ clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
+ clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
+ clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
+
+ /* SCG1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ /* NOTE: xPLL config can't be changed when xPLL is enabled */
+ clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel",
base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels),
CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_SEL]
[PATCH V5 5/9] clk: imx: add imx7ulp composite clk support
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* rename to clk-composite-7ulp.c as we have another
clk-composite-8m.c, function name also changed accordingly
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove an unneeded blank line change
* use clk_hw_register
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-composite-7ulp.c | 85
drivers/clk/imx/clk.h| 6 +++
3 files changed, 92 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite-7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index e5b0d42..c44d3d4 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-composite-7ulp.o \
clk-fixup-div.o \
clk-fixup-mux.o \
clk-gate-exclusive.o \
diff --git a/drivers/clk/imx/clk-composite-7ulp.c
b/drivers/clk/imx/clk-composite-7ulp.c
new file mode 100644
index 000..22f679c
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ */
+
+#include
+#include
+#include
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+#define PCG_CGC_SHIFT 30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK BIT(3)
+#define PCG_PCD_SHIFT 0
+#define PCG_PCD_WIDTH 3
+#define PCG_PCD_MASK 0x7
+
+struct clk_hw *imx7ulp_clk_composite(const char *name,
+const char * const *parent_names,
+int num_parents, bool mux_present,
+bool rate_present, bool gate_present,
+void __iomem *reg)
+{
+ struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+ struct clk_fractional_divider *fd = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk_hw *hw;
+
+ if (mux_present) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ }
+
+ if (rate_present) {
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+ fd_hw = &fd->hw;
+ fd->reg = reg;
+ fd->mshift = PCG_FRAC_SHIFT;
+ fd->mwidth = PCG_FRAC_WIDTH;
+ fd->mmask = PCG_FRAC_MASK;
+ fd->nshift = PCG_PCD_SHIFT;
+ fd->nwidth = PCG_PCD_WIDTH;
+ fd->nmask = PCG_PCD_MASK;
+ fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+ }
+
+ if (gate_present) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ kfree(fd);
+ return ERR_PTR(-ENOMEM);
+ }
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, fd_hw,
+ &clk_fractional_divider_ops, gate_hw,
+ &clk_gate_ops, CLK_SET_RATE_GATE |
+ CLK_SET_PARENT_GATE);
+ if (IS_ERR(hw)) {
+ kfree(mux);
+ kfree(fd);
+ kfree(gate);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index a5a9374..55a6434 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -71,6 +71,12 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem
*reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
const char **parent_names, int num_parents);
+struct clk_hw *imx7ulp_clk_composite(const char *name,
+const char * const *parent_names,
+int num_parents, bool mux_present,
+bool rate_present, bool gate_present,
+void __iomem *reg);
+
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void __iomem
[PATCH V5 7/9] clk: imx: make mux parent strings const
As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base +
0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v4: no changes
---
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk.h | 18 +++---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 9903652..e695622 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -154,7 +154,7 @@ static const struct clk_ops clk_busy_mux_ops = {
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents)
+const char * const *parent_names, int num_parents)
{
struct clk_busy_mux *busy;
struct clk *clk;
diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index c9b327e..44817c1 100644
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -70,7 +70,7 @@ static const struct clk_ops clk_fixup_mux_ops = {
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 55a6434..290d4b2 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,7 +69,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char
*parent_name,
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents);
+const char * const *parent_names, int num_parents);
struct clk_hw *imx7ulp_clk_composite(const char *name,
const char * const *parent_names,
@@ -82,7 +82,7 @@ struct clk *imx_clk_fixup_divider(const char *name, const
char *parent,
void (*fixup)(u32 *val));
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
static inline struct clk *imx_clk_fixed(const char *name, int rate)
@@ -91,7 +91,8 @@ static inline struct clk *imx_clk_fixed(const char *name, int
rate)
}
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
@@ -204,7 +205,8 @@ static inline struct clk *imx_clk_gate4(const char *name,
const char *parent,
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
@@ -212,7 +214,8 @@ static inline struct clk *imx_clk_mux(const char *name,
void __iomem *reg,
}
static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
@@ -220,8
[PATCH V5 6/9] dt-bindings: clock: add imx7ulp clock binding doc
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v4->v5:
* fix a typo that clock-name -> clock-names
* one compatible string per line
* add input clocks for pcc2/3
v3->v4:
* make scg, pcc separate nodes according to Rob's suggestion
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt| 104
include/dt-bindings/clock/imx7ulp-clock.h | 109 +
2 files changed, 213 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 000..a4f8cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,104 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+System Clock Generation (SCG) modules:
+-
+The System Clock Generation (SCG) is responsible for clock generation
+and distribution across this device. Functions performed by the SCG
+include: clock reference selection, generation of clock used to derive
+processor, system, peripheral bus and external memory interface clocks,
+source selection for peripheral clocks and control of power saving
+clock gating mode.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-scg1".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-names: Should contain the following clock names:
+ "rosc", "sosc", "sirc", "firc", "upll", "mpll".
+
+Peripheral Clock Control (PCC) modules:
+-
+The Peripheral Clock Control (PCC) is responsible for clock selection,
+optional division and clock gating mode for peripherals in their
+respected power domain
+
+Required properties:
+- compatible: Should be one of:
+ "fsl,imx7ulp-pcc2",
+ "fsl,imx7ulp-pcc3".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-names: Should contain the following clock names:
+ "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
+ "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
+ "mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs of each module.
+
+Examples:
+
+#include
+
+scg1: scg1@403e {
+ compatible = "fsl,imx7ulp-scg1;
+ reg = <0x403e 0x1>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+<&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+pcc2: pcc2@403f {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f 0x1>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+<&scg1 IMX7ULP_CLK_NIC1_DIV>,
+<&scg1 IMX7ULP_CLK_DDR_DIV>,
+<&scg1 IMX7ULP_CLK_APLL_PFD2>,
+<&scg1 IMX7ULP_CLK_APLL_PFD1>,
+<&scg1 IMX7ULP_CLK_APLL_PFD0>,
+<&scg1 IMX7ULP_CLK_UPLL>,
+<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+<&scg1 IMX7ULP_CLK_MIPI_PLL>,
+<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+<&scg1 IMX7ULP_CLK_ROSC>,
+<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+
[PATCH V5 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* split normal and gate ops
* fix the possible racy
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
---
drivers/clk/clk-divider.c| 152 +++
include/linux/clk-provider.h | 9 +++
2 files changed, 161 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b6234a5..b3566fd 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -122,6 +122,9 @@ unsigned long divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate,
div = _get_div(table, val, flags, width);
if (!div) {
+ if (flags & CLK_DIVIDER_ZERO_GATE)
+ return 0;
+
WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_hw_get_name(hw));
@@ -145,6 +148,34 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
divider->flags, divider->width);
}
+static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ unsigned int val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (!clk_hw_is_enabled(hw)) {
+ val = divider->cached_val;
+ } else {
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
static bool _is_valid_table_div(const struct clk_div_table *table,
unsigned int div)
{
@@ -437,6 +468,108 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
return 0;
}
+static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (clk_hw_is_enabled(hw)) {
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift +
16);
+ } else {
+ val = clk_readl(divider->reg);
+ val &= ~(clk_div_mask(divider->width) <<
divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ clk_writel(val, divider->reg);
+ } else {
+ divider->cached_val = value;
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static int clk_divider_enable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (!divider->cached_val) {
+ pr_err("%s: no valid pr
[PATCH V5 0/9] clk: add imx7ulp clk support
This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. Note: this series only adds A7 clock domain support as M4 clock domain will be handled by M4 seperately. Change Log: v4->v5: * rename to clk-composite-7ulp.c as we have another clk-composite-8m.c, function name also changed accordingly * binding doc updated with adding input clocks for PCC module v3->v4: * update after changing scg and pcc into separete nodes according to Rob's suggestion v2->v3: * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy Others no changes. v1->v2: * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers * use clk_hw apis to register clocks * use of_clk_add_hw_provider * split the clocks register process into two parts: early part for possible timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for the left normal peripheral clocks registered by a platform driver. Dong Aisheng (9): clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add pllv4 support clk: imx: add pfdv2 support clk: imx: add imx7ulp composite clk support dt-bindings: clock: add imx7ulp clock binding doc clk: imx: make mux parent strings const clk: imx: implement new clk_hw based APIs clk: imx: add imx7ulp clk driver .../devicetree/bindings/clock/imx7ulp-clock.txt| 104 ++ drivers/clk/clk-divider.c | 152 +++ drivers/clk/clk-fractional-divider.c | 10 + drivers/clk/imx/Makefile | 6 +- drivers/clk/imx/clk-busy.c | 2 +- drivers/clk/imx/clk-composite-7ulp.c | 85 + drivers/clk/imx/clk-fixup-mux.c| 2 +- drivers/clk/imx/clk-imx7ulp.c | 209 + drivers/clk/imx/clk-pfdv2.c| 201 drivers/clk/imx/clk-pllv4.c| 182 ++ drivers/clk/imx/clk.c | 22 +++ drivers/clk/imx/clk.h | 92 - include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ include/linux/clk-provider.h | 17 ++ 14 files changed, 1183 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 drivers/clk/imx/clk-composite-7ulp.c create mode 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.7.4
RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support
> -Original Message- > From: Leonard Crestez > Sent: Tuesday, November 6, 2018 11:34 PM [...] > > On Tue, 2018-11-06 at 15:30 +, A.s. Dong wrote: > > Gently Ping... > > > drivers/clk/imx/clk-composite.c| 85 + > > During review for 8m clocks a separate but different composite clk was added. > In order to avoid confusion that was named "clk-composite-8m.c", it would > make sense to move the 7ulp code to clk-composite-7ulp.c. > I guess we can do it, thanks. Regards Dong Aisheng > -- > Regards, > Leonard
RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support
Gently Ping... > -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:15 PM > To: sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > ; Jacky Bai ; dl-linux-imx > ; linux-...@vger.kernel.org > Subject: RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support > > Hi Stephen, > > In case you might miss to queue this series into your review list, so I > resend this > series again. > This series actually has been pending for a couple of months without > comments. > Hopefully you could help find some time to handle it when you're free. > > Thanks > > Regards > Dong Aisheng > > > -Original Message- > > From: A.s. Dong > > Sent: Sunday, October 21, 2018 9:11 PM > > To: linux-...@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > Anson > > Huang ; Jacky Bai ; > > dl-linux-imx ; A.s. Dong > > Subject: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support > > > > This is a rebased version of below patch series against latest clk tree. > > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > https://lkml.org/lkml/2018/3/16/310 > > > > It only updates the license to SPDX format as well as a minor fix of pllv4. > > > > This patch series intends to add imx7ulp clk support. > > > > i.MX7ULP Clock functions are under joint control of the System Clock > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > Core Mode Controller (CMC)1 blocks > > > > The clocking scheme provides clear separation between M4 domain and A7 > > domain. Except for a few clock sources shared between two domains, > > such as the System Oscillator clock, the Slow IRC (SIRC), and and the > > Fast IRC clock (FIRCLK), clock sources and clock management are > > separated and contained within each domain. > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > Note: this series only adds A7 clock domain support as M4 clock domain > > will be handled by M4 seperately. > > > > Change Log: > > v3->v4: > > * update after changing scg and pcc into separete nodes according to > >Rob's suggestion > > v2->v3: > > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy > >Others no changes. > > > > v1->v2: > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > > * use clk_hw apis to register clocks > > * use of_clk_add_hw_provider > > * split the clocks register process into two parts: early part for possible > >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for > >the left normal peripheral clocks registered by a platform driver. > > > > Dong Aisheng (9): > > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > > clk: imx: add pllv4 support > > clk: imx: add pfdv2 support > > clk: imx: add composite clk support > > dt-bindings: clock: add imx7ulp clock binding doc > > clk: imx: make mux parent strings const > > clk: imx: implement new clk_hw based APIs > > clk: imx: add imx7ulp clk driver > > > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + > > drivers/clk/clk-divider.c | 152 > > +++ > > drivers/clk/clk-fractional-divider.c | 10 + > > drivers/clk/imx/Makefile | 6 +- > > drivers/clk/imx/clk-busy.c | 2 +- > > drivers/clk/imx/clk-composite.c| 85 + > > drivers/clk/imx/clk-fixup-mux.c| 2 +- > > drivers/clk/imx/clk-imx7ulp.c | 209 > > + > > drivers/clk/imx/clk-pfdv2.c| 201 > > > > drivers/clk/imx/clk-pllv4.c| 182 > > ++ > > drivers/clk/imx/clk.c | 22 +++ > > drivers/clk/imx/clk.h | 92 - > > include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ > > include/linux/clk-provider.h | 17 ++ > > 14 files changed, 1166 insertions(+), 10 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > create mode 100644 drivers/clk/imx/clk-composite.c create mode > > 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 > > drivers/clk/imx/clk-pfdv2.c create mode 100644 > > drivers/clk/imx/clk-pllv4.c create mode 100644 > > include/dt-bindings/clock/imx7ulp-clock.h > > > > -- > > 2.7.4
RE: [PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc
> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, October 23, 2018 6:17 AM [...] > > On Sun, Oct 21, 2018 at 01:11:09PM +, A.s. Dong wrote: > > i.MX7ULP Clock functions are under joint control of the System Clock > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > Core Mode Controller (CMC)1 blocks > > > > Note IMX7ULP has two clock domains: M4 and A7. This binding doc is > > only for A7 clock domain. > > > > Cc: Rob Herring > > Cc: Mark Rutland > > Cc: Stephen Boyd > > Cc: Michael Turquette > > Cc: devicet...@vger.kernel.org > > Cc: Shawn Guo > > Cc: Anson Huang > > Cc: Bai Ping > > Signed-off-by: Dong Aisheng > > > > --- > > ChangeLog: > > v3->v4: > > * make scg, pcc separate nodes according to Rob's suggestion > > v2->v3: > > * no changes > > v1->v2: no changes > > --- > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 > > > include/dt-bindings/clock/imx7ulp-clock.h | 109 > + > > 2 files changed, 196 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h > > > > diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > new file mode 100644 > > index 000..2239383 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > @@ -0,0 +1,87 @@ > > +* Clock bindings for Freescale i.MX7ULP > > + > > +i.MX7ULP Clock functions are under joint control of the System Clock > > +Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > +Core Mode Controller (CMC)1 blocks > > + > > +The clocking scheme provides clear separation between M4 domain and > > +A7 domain. Except for a few clock sources shared between two domains, > > +such as the System Oscillator clock, the Slow IRC (SIRC), and and the > > +Fast IRC clock (FIRCLK), clock sources and clock management are > > +separated and contained within each domain. > > + > > +M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > +A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Where's the CMC1 binding? > CMC module is more related to low power control, so did not put in clock series. But yes, it's missed in early series, will add it in next Arch patch series. > > + > > +Note: this binding doc is only for A7 clock domain. > > + > > +System Clock Generation (SCG) modules: > > +- > > +The System Clock Generation (SCG) is responsible for clock generation > > +and distribution across this device. Functions performed by the SCG > > +include: clock reference selection, generation of clock used to > > +derive processor, system, peripheral bus and external memory > > +interface clocks, source selection for peripheral clocks and control > > +of power saving clock gating mode. > > + > > +Required properties: > > + > > +- compatible: Should be "fsl,imx7ulp-scg1". > > +- reg :Should contain registers location and length. > > +- #clock-cells:Should be <1>. > > +- clocks: Should contain the fixed input clocks. > > +- clock-name: Should contain the following clock names:"rosc", "sosc", > > clock-names > Got it > > + "sirc", "firc", "upll", "mpll". > > + > > +Peripheral Clock Control (PCC) modules: > > +- > > +The Peripheral Clock Control (PCC) is responsible for clock > > +selection, optional division and clock gating mode for peripherals in > > +their respected power domain > > + > > +Required properties: > > +- compatible: Should be "fsl,imx7ulp-pcc2" or "fsl,imx7ulp-pcc3". > > Please format one per line. > Got it > There's some register layout difference between PCC2 and PCC3? > Yes, they're for different clocks and the layout may be slightly different. For example, some clocks support rate setting (with dividers) while some of them not. > > +- reg :Should contain registers location and length. > > +- #clock-cells:Should be <1>. > > No input clocks to list? > Sorry for missing
RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support
Hi Stephen, In case you might miss to queue this series into your review list, so I resend this series again. This series actually has been pending for a couple of months without comments. Hopefully you could help find some time to handle it when you're free. Thanks Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:11 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; Anson > Huang ; Jacky Bai ; dl-linux-imx > ; A.s. Dong > Subject: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support > > This is a rebased version of below patch series against latest clk tree. > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > https://lkml.org/lkml/2018/3/16/310 > > It only updates the license to SPDX format as well as a minor fix of pllv4. > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core > Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such as > the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock > (FIRCLK), clock sources and clock management are separated and contained > within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain will > be handled by M4 seperately. > > Change Log: > v3->v4: > * update after changing scg and pcc into separete nodes according to >Rob's suggestion > v2->v3: > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy >Others no changes. > > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for possible >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for >the left normal peripheral clocks registered by a platform driver. > > Dong Aisheng (9): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + > drivers/clk/clk-divider.c | 152 > +++ > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c| 85 + > drivers/clk/imx/clk-fixup-mux.c| 2 +- > drivers/clk/imx/clk-imx7ulp.c | 209 > + > drivers/clk/imx/clk-pfdv2.c| 201 > > drivers/clk/imx/clk-pllv4.c| 182 > ++ > drivers/clk/imx/clk.c | 22 +++ > drivers/clk/imx/clk.h | 92 - > include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ > include/linux/clk-provider.h | 17 ++ > 14 files changed, 1166 insertions(+), 10 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 > drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c > create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4
[PATCH RESEND V4 3/9] clk: imx: add pllv4 support
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove clk_pllv4_is_enabled() check in set_rate, instead it will
be handled by core later.
* use readl_poll_timeout
* use clk_hw_register instead of clk_register
* other minor changes
---
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-pllv4.c | 182
drivers/clk/imx/clk.h | 3 +
3 files changed, 186 insertions(+)
create mode 100644 drivers/clk/imx/clk-pllv4.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 8c3baa7..bfe31bf 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -11,6 +11,7 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
+ clk-pllv4.o \
clk-pfd.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
new file mode 100644
index 000..67c64c7
--- /dev/null
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/* PLL Control Status Register (xPLLCSR) */
+#define PLL_CSR_OFFSET 0x0
+#define PLL_VLDBIT(24)
+#define PLL_EN BIT(0)
+
+/* PLL Configuration Register (xPLLCFG) */
+#define PLL_CFG_OFFSET 0x08
+#define BP_PLL_MULT16
+#define BM_PLL_MULT(0x7f << 16)
+
+/* PLL Numerator Register (xPLLNUM) */
+#define PLL_NUM_OFFSET 0x10
+
+/* PLL Denominator Register (xPLLDENOM) */
+#define PLL_DENOM_OFFSET 0x14
+
+struct clk_pllv4 {
+ struct clk_hw hw;
+ void __iomem*base;
+};
+
+/* Valid PLL MULT Table */
+static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+
+#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
+{
+ u32 csr;
+
+ return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
+ csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pllv4_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ if (readl_relaxed(pll->base) & PLL_EN)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 div;
+
+ div = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ div &= BM_PLL_MULT;
+ div >>= BP_PLL_MULT;
+
+ return parent_rate * div;
+}
+
+static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ unsigned long round_rate, i;
+
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate)
+ return round_rate;
+ }
+
+ return round_rate;
+}
+
+static bool clk_pllv4_is_valid_mult(unsigned int mult)
+{
+ int i;
+
+ /* check if mult is in valid MULT table */
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
+
+ return false;
+}
+
+static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+ u32 val, mult;
+
+ mult = rate / parent_rate;
+
+ if (!clk_pllv4_is_valid_mult(mult))
+ return -EINVAL;
+
+ val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
+ val &= ~BM_PLL_MULT;
+ val |= mult << BP_PLL_MULT;
+ writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
+
+ return 0;
+}
+
+static int clk_pllv4_enable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val |= PLL_EN;
+ writel_relaxed(val, pll->base);
+
+ return clk_pllv4_wait_lock(pll);
+}
+
+static void clk_pllv4_disable(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
+
+ val = readl_relaxed(pll->base);
+ val &= ~PLL_EN;
+ writel_relaxed(v
[PATCH RESEND V4 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* improve comments suggested by Stephen
---
drivers/clk/clk-fractional-divider.c | 10 ++
include/linux/clk-provider.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/clk-fractional-divider.c
b/drivers/clk/clk-fractional-divider.c
index fdf625f..7ccde6b 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m++;
+ n++;
+ }
+
if (!n || !m)
return parent_rate;
@@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned
long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
+ if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) {
+ m--;
+ n--;
+ }
+
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08f135a..90d7c26 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -603,6 +603,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
+ *
+ * Flags:
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
+ * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
+ * is set then the numerator and denominator are both the value read
+ * plus one.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -622,6 +628,8 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
+#define CLK_FRAC_DIVIDER_ZERO_BASEDBIT(0)
+
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
--
2.7.4
[PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring
Cc: Mark Rutland
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: devicet...@vger.kernel.org
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* make scg, pcc separate nodes according to Rob's suggestion
v2->v3:
* no changes
v1->v2: no changes
---
.../devicetree/bindings/clock/imx7ulp-clock.txt| 87
include/dt-bindings/clock/imx7ulp-clock.h | 109 +
2 files changed, 196 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 000..2239383
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,87 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+System Clock Generation (SCG) modules:
+-
+The System Clock Generation (SCG) is responsible for clock generation
+and distribution across this device. Functions performed by the SCG
+include: clock reference selection, generation of clock used to derive
+processor, system, peripheral bus and external memory interface clocks,
+source selection for peripheral clocks and control of power saving
+clock gating mode.
+
+Required properties:
+
+- compatible: Should be "fsl,imx7ulp-scg1".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+- clocks: Should contain the fixed input clocks.
+- clock-name: Should contain the following clock names:"rosc", "sosc",
+ "sirc", "firc", "upll", "mpll".
+
+Peripheral Clock Control (PCC) modules:
+-
+The Peripheral Clock Control (PCC) is responsible for clock selection,
+optional division and clock gating mode for peripherals in their
+respected power domain
+
+Required properties:
+- compatible: Should be "fsl,imx7ulp-pcc2" or "fsl,imx7ulp-pcc3".
+- reg :Should contain registers location and length.
+- #clock-cells:Should be <1>.
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs of each module.
+
+Examples:
+
+#include
+
+scg1: scg1@403e {
+ compatible = "fsl,imx7ulp-scg1;
+ reg = <0x403e 0x1>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+<&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+};
+
+pcc2: pcc2@403f {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f 0x1>;
+ #clock-cells = <1>;
+};
+
+pcc3: pcc3@40b3 {
+ compatible = "fsl,imx7ulp-pcc3";
+ reg = <0x40b3 0x1>;
+ #clock-cells = <1>;
+};
+
+usdhc1: usdhc@4038 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x4038 0x1>;
+ interrupts = ;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+<&scg1 IMX7ULP_CLK_NIC1_DIV>,
+<&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+};
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h
b/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 000..008c5ee
--- /dev/null
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+/* SCG1 */
+
+#define IMX7ULP_CLK_DUMMY 0
+#define IMX7ULP_CLK_ROSC 1
+#define IMX7ULP_CLK_SOSC 2
+#define IMX7ULP_CLK_FIRC
[PATCH RESEND V4 4/9] clk: imx: add pfdv2 support
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pfdv2 can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* change to readl_poll_timeout
* add pfd lock to protect share reg access between rate and enable/disable
operations and multiple pfd instances.
* use clk_hw_register
---
drivers/clk/imx/Makefile| 3 +-
drivers/clk/imx/clk-pfdv2.c | 201
drivers/clk/imx/clk.h | 3 +
3 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-pfdv2.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index bfe31bf..e5b0d42 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,8 @@ obj-y += \
clk-pllv2.o \
clk-pllv3.o \
clk-pllv4.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-pfdv2.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
new file mode 100644
index 000..afb2904
--- /dev/null
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/**
+ * struct clk_pfdv2 - IMX PFD clock
+ * @clk_hw:clock source
+ * @reg: PFD register address
+ * @gate_bit: Gate bit offset
+ * @vld_bit: Valid bit offset
+ * @frac_off: PLL Fractional Divider offset
+ */
+
+struct clk_pfdv2 {
+ struct clk_hw hw;
+ void __iomem*reg;
+ u8 gate_bit;
+ u8 vld_bit;
+ u8 frac_off;
+};
+
+#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
+
+#define CLK_PFDV2_FRAC_MASK 0x3f
+
+#define LOCK_TIMEOUT_USUSEC_PER_MSEC
+
+static DEFINE_SPINLOCK(pfd_lock);
+
+static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
+{
+ u32 val;
+
+ return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+ 0, LOCK_TIMEOUT_US);
+}
+
+static int clk_pfdv2_enable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+
+ return clk_pfdv2_wait(pfd);
+}
+
+static void clk_pfdv2_disable(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val |= pfd->gate_bit;
+ writel_relaxed(val, pfd->reg);
+ spin_unlock_irqrestore(&pfd_lock, flags);
+}
+
+static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
+ & CLK_PFDV2_FRAC_MASK;
+
+ if (!frac) {
+ pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
+clk_hw_get_name(hw));
+ return 0;
+ }
+
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *prate)
+{
+ u64 tmp = *prate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ tmp = *prate;
+ tmp *= 18;
+ do_div(tmp, frac);
+
+ return tmp;
+}
+
+static int clk_pfdv2_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+
+ if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+ return 0;
+
+ return 1;
+}
+
+static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
+ unsigned long flags;
+ u64 tmp = parent_rate;
+ u32 val;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ spin_lock_irqsave(&pfd_lock, flags);
+ val = readl_relaxed(pfd->reg);
+ val &= ~(CLK_PFDV2_FRAC_MAS
[PATCH RESEND V4 7/9] clk: imx: make mux parent strings const
As the commit 2893c379461a ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:
drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
'imx_clk_mux_flags' discards 'const' qualifier from pointer target type
clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base +
0x508, 0,
1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
of type 'const char * const*'
...
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v1->v4: no changes
---
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk.h | 18 +++---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 9903652..e695622 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -154,7 +154,7 @@ static const struct clk_ops clk_busy_mux_ops = {
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents)
+const char * const *parent_names, int num_parents)
{
struct clk_busy_mux *busy;
struct clk *clk;
diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c
index c9b327e..44817c1 100644
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
@@ -70,7 +70,7 @@ static const struct clk_ops clk_fixup_mux_ops = {
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index bc43f68..7fca912 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,7 +69,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char
*parent_name,
struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
-const char **parent_names, int num_parents);
+const char * const *parent_names, int num_parents);
struct clk_hw *imx_clk_composite(const char *name,
const char * const *parent_names,
@@ -82,7 +82,7 @@ struct clk *imx_clk_fixup_divider(const char *name, const
char *parent,
void (*fixup)(u32 *val));
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents,
+ u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
static inline struct clk *imx_clk_fixed(const char *name, int rate)
@@ -91,7 +91,8 @@ static inline struct clk *imx_clk_fixed(const char *name, int
rate)
}
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
@@ -204,7 +205,8 @@ static inline struct clk *imx_clk_gate4(const char *name,
const char *parent,
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
@@ -212,7 +214,8 @@ static inline struct clk *imx_clk_mux(const char *name,
void __iomem *reg,
}
static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char **parents, int num_parents)
+ u8 shift, u8 width, const char * const *parents,
+ int num_parents)
{
return clk_register_mux(NULL, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
@@ -220,8 +223,9 @
[PATCH RESEND V4 5/9] clk: imx: add composite clk support
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series. e.g. i.MX7ULP.
NOTE pcc can only be operated when clk is gated.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* no changes
v1->v2:
* remove an unneeded blank line change
* use clk_hw_register
---
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-composite.c | 85 +
drivers/clk/imx/clk.h | 6 +++
3 files changed, 92 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index e5b0d42..f4da12c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -4,6 +4,7 @@ obj-y += \
clk.o \
clk-busy.o \
clk-cpu.o \
+ clk-composite.o \
clk-fixup-div.o \
clk-fixup-mux.o \
clk-gate-exclusive.o \
diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
new file mode 100644
index 000..297974b
--- /dev/null
+++ b/drivers/clk/imx/clk-composite.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ */
+
+#include
+#include
+#include
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+#define PCG_CGC_SHIFT 30
+#define PCG_FRAC_SHIFT 3
+#define PCG_FRAC_WIDTH 1
+#define PCG_FRAC_MASK BIT(3)
+#define PCG_PCD_SHIFT 0
+#define PCG_PCD_WIDTH 3
+#define PCG_PCD_MASK 0x7
+
+struct clk_hw *imx_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, bool mux_present,
+ bool rate_present, bool gate_present,
+ void __iomem *reg)
+{
+ struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
+ struct clk_fractional_divider *fd = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk_hw *hw;
+
+ if (mux_present) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ }
+
+ if (rate_present) {
+ fd = kzalloc(sizeof(*fd), GFP_KERNEL);
+ if (!fd) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+ fd_hw = &fd->hw;
+ fd->reg = reg;
+ fd->mshift = PCG_FRAC_SHIFT;
+ fd->mwidth = PCG_FRAC_WIDTH;
+ fd->mmask = PCG_FRAC_MASK;
+ fd->nshift = PCG_PCD_SHIFT;
+ fd->nwidth = PCG_PCD_WIDTH;
+ fd->nmask = PCG_PCD_MASK;
+ fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+ }
+
+ if (gate_present) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ kfree(fd);
+ return ERR_PTR(-ENOMEM);
+ }
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, fd_hw,
+ &clk_fractional_divider_ops, gate_hw,
+ &clk_gate_ops, CLK_SET_RATE_GATE |
+ CLK_SET_PARENT_GATE);
+ if (IS_ERR(hw)) {
+ kfree(mux);
+ kfree(fd);
+ kfree(gate);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index a5a9374..bc43f68 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -71,6 +71,12 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem
*reg, u8 shift,
u8 width, void __iomem *busy_reg, u8 busy_shift,
const char **parent_names, int num_parents);
+struct clk_hw *imx_clk_composite(const char *name,
+const char * const *parent_names,
+int num_parents, bool mux_present,
+bool rate_present, bool gate_present,
+void __iomem *reg);
+
struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
void __iomem *reg, u8 shift, u8 width,
void (*fixup)(u32 *val));
--
2.7.4
[PATCH RESEND V4 0/9] clk: add imx7ulp clk support
This is a rebased version of below patch series against latest clk tree. [PATCH RESEND V3 0/9] clk: add imx7ulp clk support https://lkml.org/lkml/2018/3/16/310 It only updates the license to SPDX format as well as a minor fix of pllv4. This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. Note: this series only adds A7 clock domain support as M4 clock domain will be handled by M4 seperately. Change Log: v3->v4: * update after changing scg and pcc into separete nodes according to Rob's suggestion v2->v3: * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy Others no changes. v1->v2: * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers * use clk_hw apis to register clocks * use of_clk_add_hw_provider * split the clocks register process into two parts: early part for possible timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for the left normal peripheral clocks registered by a platform driver. Dong Aisheng (9): clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add pllv4 support clk: imx: add pfdv2 support clk: imx: add composite clk support dt-bindings: clock: add imx7ulp clock binding doc clk: imx: make mux parent strings const clk: imx: implement new clk_hw based APIs clk: imx: add imx7ulp clk driver .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + drivers/clk/clk-divider.c | 152 +++ drivers/clk/clk-fractional-divider.c | 10 + drivers/clk/imx/Makefile | 6 +- drivers/clk/imx/clk-busy.c | 2 +- drivers/clk/imx/clk-composite.c| 85 + drivers/clk/imx/clk-fixup-mux.c| 2 +- drivers/clk/imx/clk-imx7ulp.c | 209 + drivers/clk/imx/clk-pfdv2.c| 201 drivers/clk/imx/clk-pllv4.c| 182 ++ drivers/clk/imx/clk.c | 22 +++ drivers/clk/imx/clk.h | 92 - include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ include/linux/clk-provider.h | 17 ++ 14 files changed, 1166 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.7.4
[PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* split normal and gate ops
* fix the possible racy
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
---
drivers/clk/clk-divider.c| 152 +++
include/linux/clk-provider.h | 9 +++
2 files changed, 161 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b6234a5..b3566fd 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -122,6 +122,9 @@ unsigned long divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate,
div = _get_div(table, val, flags, width);
if (!div) {
+ if (flags & CLK_DIVIDER_ZERO_GATE)
+ return 0;
+
WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_hw_get_name(hw));
@@ -145,6 +148,34 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
divider->flags, divider->width);
}
+static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ unsigned int val;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (!clk_hw_is_enabled(hw)) {
+ val = divider->cached_val;
+ } else {
+ val = clk_readl(divider->reg) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
static bool _is_valid_table_div(const struct clk_div_table *table,
unsigned int div)
{
@@ -437,6 +468,108 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
return 0;
}
+static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ if (clk_hw_is_enabled(hw)) {
+ if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+ val = clk_div_mask(divider->width) << (divider->shift +
16);
+ } else {
+ val = clk_readl(divider->reg);
+ val &= ~(clk_div_mask(divider->width) <<
divider->shift);
+ }
+ val |= (u32)value << divider->shift;
+ clk_writel(val, divider->reg);
+ } else {
+ divider->cached_val = value;
+ }
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static int clk_divider_enable(struct clk_hw *hw)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ u32 val;
+
+ if (!divider->cached_val) {
+ pr_err("%s: no valid pr
[PATCH RESEND V4 9/9] clk: imx: add imx7ulp clk driver
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
This driver only adds clock support in A7 domain.
Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.
Cc: Stephen Boyd
Cc: Michael Turquette
Cc: Shawn Guo
Cc: Anson Huang
Cc: Bai Ping
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* update after changing scg and pcc into separete nodes according to
Rob's suggestion
v2->v3:
* no changes
v1->v2:
* use of_clk_add_hw_provider instead
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx7ulp.c | 209 ++
2 files changed, 210 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f4da12c..983c0a5 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -29,4 +29,5 @@ obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
+obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
new file mode 100644
index 000..33dedca
--- /dev/null
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ *
+ * Author: Dong Aisheng
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static const char * const pll_pre_sels[] = { "sosc", "firc", };
+static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1",
"spll_pfd2", "spll_pfd3", };
+static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
+static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1",
"apll_pfd2", "apll_pfd3", };
+static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
+static const char * const scs_sels[] = { "dummy", "sosc", "sirc",
"firc", "dummy", "apll_sel", "spll_sel", "upll", };
+static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
+static const char * const nic_sels[] = { "firc", "ddr_clk", };
+static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk",
"nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
+static const char * const periph_bus_sels[]= { "dummy", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+
+static void __init imx7ulp_clk_scg1_init(struct device_node *np)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ void __iomem *base;
+
+ clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
+ IMX7ULP_CLK_SCG1_END, GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_SCG1_END;
+ clks = clk_data->hws;
+
+ clks[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+
+ clks[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
+ clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
+ clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
+ clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
+ clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
+ clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
+
+ /* SCG1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ /* NOTE: xPLL config can't be changed when xPLL is enabled */
+ clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel",
base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels),
CLK_SET_PARENT_GATE);
+ clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel",
base + 0x608,
[PATCH RESEND V4 8/9] clk: imx: implement new clk_hw based APIs
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v4:
* no changes
v1->v2: new patches
---
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 62 +++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9074e69..1efed86 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -18,6 +18,16 @@ void __init imx_check_clocks(struct clk *clks[], unsigned
int count)
i, PTR_ERR(clks[i]));
}
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+}
+
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;
@@ -49,6 +59,18 @@ struct clk * __init imx_obtain_fixed_clock(
return clk;
}
+struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name)
+{
+ struct clk *clk;
+
+ clk = of_clk_get_by_name(np, name);
+ if (IS_ERR(clk))
+ return ERR_PTR(-ENOENT);
+
+ return __clk_get_hw(clk);
+}
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 7fca912..d3fcaa5 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -8,6 +8,7 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
void imx_register_uart_clocks(struct clk ** const clks[]);
extern void imx_cscmr1_fixup(u32 *val);
@@ -54,6 +55,9 @@ struct clk *clk_register_gate2(struct device *dev, const char
*name,
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
+ const char *name);
+
struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
void __iomem *reg, u8 shift, u32 exclusive_mask);
@@ -90,6 +94,16 @@ static inline struct clk *imx_clk_fixed(const char *name,
int rate)
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
}
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
+static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
+{
+ return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+}
+
static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -113,6 +127,15 @@ static inline struct clk *imx_clk_divider(const char
*name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider_flags(const char *name,
const char *parent, void __iomem *reg, u8 shift, u8 width,
unsigned long flags)
@@ -121,6 +144,15 @@ static inline struct clk *imx_clk_divider_flags(const char
*name,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width, unsigned long
flags)
+{
+ return clk_hw_register_divider(NULL, name, parent, flags,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_divider2(const char *name, const char
*parent,
void __iomem *reg, u8 shift, u8 width)
{
@@ -143,6 +175,13 @@ static inline struct clk *imx_clk_gate_flags(const char
*name, const char *paren
shift, 0, &imx_ccm_lock);
}
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char
*parent,
+
RE: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll
Hi Leonard, > -Original Message- > From: Leonard Crestez > Sent: Monday, October 15, 2018 9:28 PM [...] > Subject: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll > > The DCP block is present on 6sll and 6ull but not enabled. The hardware is > mostly compatible with 6sl, the only important difference is that explicit > clock > enabling is required. > > There were several issues with the functionality of this driver (it didn't > even > probe properly) but they are fixed in cryptodev/master by this series: > https://lore.kernel.org/patchwork/cover/994874/ > Thanks for the work. I will be glad to help the test if you provide some test guides. :-) Regards Dong Aisheng > --- > Changes since v1: > * Add devicetree maintainers for dt-bindings > * Add a patch enabling in imx_v6_v7_defconfig. Since tcrypt now passes this > shouldn't cause any issues > * Link to v1: https://lore.kernel.org/patchwork/cover/994893/ > > Leonard Crestez (4): > dt-bindings: crypto: Mention clocks for mxs-dcp > crypto: mxs-dcp - Add support for dcp clk > ARM: dts: imx6ull: Add dcp node > ARM: imx_v6_v7_defconfig: Enable CRYPTO_DEV_MXS_DCP > > .../devicetree/bindings/crypto/fsl-dcp.txt | 2 ++ > arch/arm/boot/dts/imx6ull.dtsi | 10 ++ > arch/arm/configs/imx_v6_v7_defconfig | 1 + > drivers/crypto/mxs-dcp.c | 18 > ++ > 4 files changed, 31 insertions(+) > > -- > 2.17.1
RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
Ping > -Original Message- > From: A.s. Dong > Sent: Monday, October 8, 2018 6:43 PM > To: thor.tha...@linux.intel.com; linux-...@vger.kernel.org; sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; dl-linux-imx > ; hdego...@redhat.com > Subject: RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks > > Hi Stephen, > > Gently ping again.. > > > > > > > > Just checking on the status of this patch. The clock routines > > > (patches > > > 1-3) are useful for one of my drivers but if they aren't accepted or > > > will take a long time to be accepted, I'll need to refactor my driver. > > > > > > > Thanks for this information. > > > > Stephen, > > Would you help to proceed this? > > > > Regards > Dong Aisheng
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
Ping > -Original Message- > From: A.s. Dong > Sent: Tuesday, September 25, 2018 5:11 PM > To: sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; Anson Huang ; Jacky Bai > ; dl-linux-imx ; > linux-...@vger.kernel.org > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > It's been a few months without comments. > > Shawn & Stephen, > Would you provide some suggestions on how to handle this? > > Regards > Dong Aisheng > > > -Original Message- > > From: A.s. Dong > > Sent: Thursday, September 6, 2018 11:25 AM > > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > mturque...@baylibre.com; Anson Huang ; Jacky > Bai > > ; dl-linux-imx > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > Hi Stephen, > > > > Would you shine some lights on how to proceed? > > > > Regards > > Dong Aisheng > > > > > -Original Message- > > > From: A.s. Dong > > > Sent: Monday, August 27, 2018 11:46 AM > > > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > > > Cc: linux-kernel@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > mturque...@baylibre.com; Anson Huang ; Jacky > > Bai > > > ; dl-linux-imx > > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > Kindly ping again... This is really pending too long... > > > > > > Stephen & Shawn, > > > Any suggestion on how to proceed this patch set? > > > > > > Regards > > > Dong Aisheng > > > > > > > -Original Message- > > > > From: A.s. Dong > > > > Sent: Thursday, July 26, 2018 9:51 AM > > > > To: linux-...@vger.kernel.org; sb...@kernel.org > > > > Cc: linux-kernel@vger.kernel.org; > > > > linux-arm-ker...@lists.infradead.org; > > > > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > > > > ; Jacky Bai ; dl-linux-imx > > > > > > > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > > > Hi Stephen, > > > > > > > > Do you have a chance to look at it? > > > > This patch series has been pending for quite a long time without > > > > much comments. > > > > > > > > Regards > > > > Dong Aisheng > > > > > > > > > -Original Message- > > > > > From: A.s. Dong > > > > > Sent: Wednesday, July 18, 2018 9:37 PM > > > > > To: linux-...@vger.kernel.org > > > > > Cc: linux-kernel@vger.kernel.org; > > > > > linux-arm-ker...@lists.infradead.org; > > > > > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > > > > Anson > > > > > Huang ; Jacky Bai ; dl- > > > > > linux-imx ; A.s. Dong > > > > > Subject: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > > > > > This is a rebased version of below patch series against latest clk > > > > > tree. > > > > > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > > > > https://lkml.org/lkml/2018/3/16/310 > > > > > > > > > > This patch series intends to add imx7ulp clk support. > > > > > > > > > > i.MX7ULP Clock functions are under joint control of the System > > > > > Clock Generation (SCG) modules, Peripheral Clock Control (PCC) > > > > > modules, and Core Mode Controller (CMC)1 blocks > > > > > > > > > > The clocking scheme provides clear separation between M4 domain > > > > > and > > > > > A7 domain. Except for a few clock sources shared between two > > > > > domains, such as the System Oscillator clock, the Slow IRC > > > > > (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and > > > > > clock management are separated and contained within each domain. > > > > > > > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 > > modules. > > > > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 > modules. > > > > > > > > > > Note: this series only adds A7 clock domain support as M4 clock > > &
RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
Hi Stephen, Gently ping again.. > > > > > Just checking on the status of this patch. The clock routines (patches > > 1-3) are useful for one of my drivers but if they aren't accepted or > > will take a long time to be accepted, I'll need to refactor my driver. > > > > Thanks for this information. > > Stephen, > Would you help to proceed this? > Regards Dong Aisheng
RE: [PATCH 1/1] MAINTAINERS: imx: include drivers/firmware/imx path
> > diff --git a/MAINTAINERS b/MAINTAINERS index 9ad052a..d1fb824 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1462,6 +1462,7 @@ F:arch/arm/mach-mxs/ > > F: arch/arm/boot/dts/imx* > > F: arch/arm/configs/imx*_defconfig > > F: drivers/clk/imx/ > > +F: drivers/firmware/imx/ > > Please add include/linux/firmware/imx/ too. > Sorry for missing it. Will update now. Regards Dong Aisheng > Shawn > > > F: drivers/soc/imx/ > > F: include/soc/imx/ > > > > -- > > 2.7.4 > >
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
It's been a few months without comments. Shawn & Stephen, Would you provide some suggestions on how to handle this? Regards Dong Aisheng > -Original Message----- > From: A.s. Dong > Sent: Thursday, September 6, 2018 11:25 AM > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; Anson Huang ; Jacky Bai > ; dl-linux-imx > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > Hi Stephen, > > Would you shine some lights on how to proceed? > > Regards > Dong Aisheng > > > -Original Message- > > From: A.s. Dong > > Sent: Monday, August 27, 2018 11:46 AM > > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > mturque...@baylibre.com; Anson Huang ; Jacky > Bai > > ; dl-linux-imx > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > Kindly ping again... This is really pending too long... > > > > Stephen & Shawn, > > Any suggestion on how to proceed this patch set? > > > > Regards > > Dong Aisheng > > > > > -Original Message- > > > From: A.s. Dong > > > Sent: Thursday, July 26, 2018 9:51 AM > > > To: linux-...@vger.kernel.org; sb...@kernel.org > > > Cc: linux-kernel@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > > > ; Jacky Bai ; dl-linux-imx > > > > > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > Hi Stephen, > > > > > > Do you have a chance to look at it? > > > This patch series has been pending for quite a long time without > > > much comments. > > > > > > Regards > > > Dong Aisheng > > > > > > > -Original Message- > > > > From: A.s. Dong > > > > Sent: Wednesday, July 18, 2018 9:37 PM > > > > To: linux-...@vger.kernel.org > > > > Cc: linux-kernel@vger.kernel.org; > > > > linux-arm-ker...@lists.infradead.org; > > > > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > > > Anson > > > > Huang ; Jacky Bai ; dl- > > > > linux-imx ; A.s. Dong > > > > Subject: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > > > This is a rebased version of below patch series against latest clk tree. > > > > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > > > https://lkml.org/lkml/2018/3/16/310 > > > > > > > > This patch series intends to add imx7ulp clk support. > > > > > > > > i.MX7ULP Clock functions are under joint control of the System > > > > Clock Generation (SCG) modules, Peripheral Clock Control (PCC) > > > > modules, and Core Mode Controller (CMC)1 blocks > > > > > > > > The clocking scheme provides clear separation between M4 domain > > > > and > > > > A7 domain. Except for a few clock sources shared between two > > > > domains, such as the System Oscillator clock, the Slow IRC (SIRC), > > > > and and the Fast IRC clock (FIRCLK), clock sources and clock > > > > management are separated and contained within each domain. > > > > > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 > modules. > > > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > > > > > Note: this series only adds A7 clock domain support as M4 clock > > > > domain will be handled by M4 seperately. > > > > > > > > Change Log: > > > > v3->v4: > > > > * rebased to latest kernel > > > > * make scg and pcc separate nodes according to Rob's suggestion > > > > > > > > v2->v3: > > > > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible > racy > > > >Others no changes. > > > > > > > > v1->v2: > > > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE > > > > dividers > > > > * use clk_hw apis to register clocks > > > > * use of_clk_add_hw_provider > > > > * split the clocks register process into two parts: early part for > > > > possible > > > >timers clocks registered by CLK_OF_DECLARE_DRIVER and the
RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
> -Original Message-
> From: Thor Thayer [mailto:thor.tha...@linux.intel.com]
> Sent: Wednesday, September 19, 2018 10:47 PM
> To: A.s. Dong ; linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> dl-linux-imx ; hdego...@redhat.com
> Subject: Re: [PATCH V6 0/4] clk: new APIs to handle all available clocks
>
> Hi,
>
> On 09/16/2018 08:24 AM, A.s. Dong wrote:
> > Ping again
> >
> >> -Original Message-
> >> From: A.s. Dong
> >> Sent: Thursday, September 6, 2018 11:23 AM
> >> To: linux-...@vger.kernel.org
> >> Cc: linux-kernel@vger.kernel.org;
> >> linux-arm-ker...@lists.infradead.org;
> >> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> >> thor.tha...@linux.intel.com; dl-linux-imx ;
> >> hdego...@redhat.com
> >> Subject: RE: [PATCH V6 0/4] clk: new APIs to handle all available
> >> clocks
> >>
> >> Gently ping...
> >>
> >>> -Original Message-
> >>> From: A.s. Dong
> >>> Sent: Friday, August 31, 2018 12:46 PM
> >>> To: linux-...@vger.kernel.org
> >>> Cc: linux-kernel@vger.kernel.org;
> >>> linux-arm-ker...@lists.infradead.org;
> >>> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> >>> thor.tha...@linux.intel.com; dl-linux-imx ;
> >>> hdego...@redhat.com; A.s. Dong
> >>> Subject: [PATCH V6 0/4] clk: new APIs to handle all available clocks
> >>>
> >>> This patch series is a continue of discussion from here,
> >>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
> >>>
> atchwork.kernel.org%2Fpatch%2F9986293%2F&data=02%7C01%7Caishe
> ng.
> >>>
> dong%40nxp.com%7Cb79f0aa8c74c4f935adb08d61e3e7944%7C686ea1d3bc
> 2b4c6f
> >>>
> a92cd99c5c301635%7C0%7C0%7C636729651014549633&sdata=zh0RP
> Vt4pqyM
> >>> 84SUFRpDcbIH583JNONlBhTQeLYwDFo%3D&reserved=0
> >>> that some users may want to handle all available clocks from device
> >>> tree without need to know the detailed clock information likes clock
> >>> numbers and names. This is useful in writing some generic drivers to
> >>> handle
> >> clock part.
> >>>
> >>> Note:
> >>> This patch series is tested on MX6Q SDB cpufreq driver with a minor
> >>> change to switch to use clk_bulk_get_all.
> >>> But patch 4 only test compiling. Hopefully someone could help test
> >>> the function.
> >>>
> >>> v3->v4:
> >>> * improve 'devres->clks = *clks' according to Stephen's suggestion
> >>> v2->v3:
> >>> * address all comments from Stephen
> >>> * fix build warnings on other architectures.
> >>> v1->v2:
> >>> * add clk_bulk_{get|put}_all() which only supports DT platform
> >>> currently
> >>> * remove _all variants and the wrapper struct clk_bulk
> >>> * make of_clk_bulk_get and of_clk_bulk_get_all private until someone
> >>> proves they need it because they don't have a struct device pointer.
> >>>
> >>> Dong Aisheng (4):
> >>>clk: bulk: add of_clk_bulk_get()
> >>>clk: add new APIs to operate on all available clocks
> >>>clk: add managed version of clk_bulk_get_all
> >>>video: simplefb: switch to use clk_bulk API to simplify clock
> >>> operations
> >>>
> >>> drivers/clk/clk-bulk.c | 80
> >>> ++
> >>> drivers/clk/clk-devres.c | 24 +
> >>> drivers/video/fbdev/simplefb.c | 72
> >>> ++---
> >>> include/linux/clk.h| 65
> >>> +-
> >>> 4 files changed, 186 insertions(+), 55 deletions(-)
> >>>
> >>> --
> >>> 2.7.4
> >
> Just checking on the status of this patch. The clock routines (patches
> 1-3) are useful for one of my drivers but if they aren't accepted or will
> take a
> long time to be accepted, I'll need to refactor my driver.
>
Thanks for this information.
Stephen,
Would you help to proceed this?
Regards
Dong Aisheng
RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
Ping again
> -Original Message-
> From: A.s. Dong
> Sent: Thursday, September 6, 2018 11:23 AM
> To: linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> thor.tha...@linux.intel.com; dl-linux-imx ;
> hdego...@redhat.com
> Subject: RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
>
> Gently ping...
>
> > -Original Message-
> > From: A.s. Dong
> > Sent: Friday, August 31, 2018 12:46 PM
> > To: linux-...@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org;
> > linux-arm-ker...@lists.infradead.org;
> > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> > thor.tha...@linux.intel.com; dl-linux-imx ;
> > hdego...@redhat.com; A.s. Dong
> > Subject: [PATCH V6 0/4] clk: new APIs to handle all available clocks
> >
> > This patch series is a continue of discussion from here,
> > https://patchwork.kernel.org/patch/9986293/
> > that some users may want to handle all available clocks from device
> > tree without need to know the detailed clock information likes clock
> > numbers and names. This is useful in writing some generic drivers to handle
> clock part.
> >
> > Note:
> > This patch series is tested on MX6Q SDB cpufreq driver with a minor
> > change to switch to use clk_bulk_get_all.
> > But patch 4 only test compiling. Hopefully someone could help test the
> > function.
> >
> > v3->v4:
> > * improve 'devres->clks = *clks' according to Stephen's suggestion
> > v2->v3:
> > * address all comments from Stephen
> > * fix build warnings on other architectures.
> > v1->v2:
> > * add clk_bulk_{get|put}_all() which only supports DT platform
> > currently
> > * remove _all variants and the wrapper struct clk_bulk
> > * make of_clk_bulk_get and of_clk_bulk_get_all private until someone
> >proves they need it because they don't have a struct device pointer.
> >
> > Dong Aisheng (4):
> > clk: bulk: add of_clk_bulk_get()
> > clk: add new APIs to operate on all available clocks
> > clk: add managed version of clk_bulk_get_all
> > video: simplefb: switch to use clk_bulk API to simplify clock
> > operations
> >
> > drivers/clk/clk-bulk.c | 80
> > ++
> > drivers/clk/clk-devres.c | 24 +
> > drivers/video/fbdev/simplefb.c | 72 ++---
> > include/linux/clk.h| 65
> > +-
> > 4 files changed, 186 insertions(+), 55 deletions(-)
> >
> > --
> > 2.7.4
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
Hi Stephen, Would you shine some lights on how to proceed? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Monday, August 27, 2018 11:46 AM > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; Anson Huang ; Jacky Bai > ; dl-linux-imx > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > Kindly ping again... This is really pending too long... > > Stephen & Shawn, > Any suggestion on how to proceed this patch set? > > Regards > Dong Aisheng > > > -Original Message- > > From: A.s. Dong > > Sent: Thursday, July 26, 2018 9:51 AM > > To: linux-...@vger.kernel.org; sb...@kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > > ; Jacky Bai ; dl-linux-imx > > > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > Hi Stephen, > > > > Do you have a chance to look at it? > > This patch series has been pending for quite a long time without much > > comments. > > > > Regards > > Dong Aisheng > > > > > -Original Message- > > > From: A.s. Dong > > > Sent: Wednesday, July 18, 2018 9:37 PM > > > To: linux-...@vger.kernel.org > > > Cc: linux-kernel@vger.kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > > Anson > > > Huang ; Jacky Bai ; dl- > > > linux-imx ; A.s. Dong > > > Subject: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > > > This is a rebased version of below patch series against latest clk tree. > > > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > > https://lkml.org/lkml/2018/3/16/310 > > > > > > This patch series intends to add imx7ulp clk support. > > > > > > i.MX7ULP Clock functions are under joint control of the System Clock > > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, > > > and Core Mode Controller (CMC)1 blocks > > > > > > The clocking scheme provides clear separation between M4 domain and > > > A7 domain. Except for a few clock sources shared between two > > > domains, such as the System Oscillator clock, the Slow IRC (SIRC), > > > and and the Fast IRC clock (FIRCLK), clock sources and clock > > > management are separated and contained within each domain. > > > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > > > Note: this series only adds A7 clock domain support as M4 clock > > > domain will be handled by M4 seperately. > > > > > > Change Log: > > > v3->v4: > > > * rebased to latest kernel > > > * make scg and pcc separate nodes according to Rob's suggestion > > > > > > v2->v3: > > > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible > > > racy > > >Others no changes. > > > > > > v1->v2: > > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > > > * use clk_hw apis to register clocks > > > * use of_clk_add_hw_provider > > > * split the clocks register process into two parts: early part for > > > possible > > >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later > > > part > > for > > >the left normal peripheral clocks registered by a platform driver. > > > > > > Dong Aisheng (9): > > > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > > > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag > support > > > clk: imx: add pllv4 support > > > clk: imx: add pfdv2 support > > > clk: imx: add composite clk support > > > dt-bindings: clock: add imx7ulp clock binding doc > > > clk: imx: make mux parent strings const > > > clk: imx: implement new clk_hw based APIs > > > clk: imx: add imx7ulp clk driver > > > > > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + > > > drivers/clk/clk-divider.c | 152 > > +++ > > > drivers/clk/clk-fractional-divider.c | 10 + > > > drivers/clk/imx/Makefile | 6
RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks
Gently ping...
> -Original Message-
> From: A.s. Dong
> Sent: Friday, August 31, 2018 12:46 PM
> To: linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org;
> thor.tha...@linux.intel.com; dl-linux-imx ;
> hdego...@redhat.com; A.s. Dong
> Subject: [PATCH V6 0/4] clk: new APIs to handle all available clocks
>
> This patch series is a continue of discussion from here,
> https://patchwork.kernel.org/patch/9986293/
> that some users may want to handle all available clocks from device tree
> without need to know the detailed clock information likes clock numbers and
> names. This is useful in writing some generic drivers to handle clock part.
>
> Note:
> This patch series is tested on MX6Q SDB cpufreq driver with a minor change to
> switch to use clk_bulk_get_all.
> But patch 4 only test compiling. Hopefully someone could help test the
> function.
>
> v3->v4:
> * improve 'devres->clks = *clks' according to Stephen's suggestion
> v2->v3:
> * address all comments from Stephen
> * fix build warnings on other architectures.
> v1->v2:
> * add clk_bulk_{get|put}_all() which only supports DT platform currently
> * remove _all variants and the wrapper struct clk_bulk
> * make of_clk_bulk_get and of_clk_bulk_get_all private until someone
>proves they need it because they don't have a struct device pointer.
>
> Dong Aisheng (4):
> clk: bulk: add of_clk_bulk_get()
> clk: add new APIs to operate on all available clocks
> clk: add managed version of clk_bulk_get_all
> video: simplefb: switch to use clk_bulk API to simplify clock
> operations
>
> drivers/clk/clk-bulk.c | 80
> ++
> drivers/clk/clk-devres.c | 24 +
> drivers/video/fbdev/simplefb.c | 72 ++---
> include/linux/clk.h| 65
> +-
> 4 files changed, 186 insertions(+), 55 deletions(-)
>
> --
> 2.7.4
RE: [PATCH V4 4/4] video: simplefb: switch to use clk_bulk API to simplify clock operations
> -Original Message-
> From: Hans de Goede [mailto:hdego...@redhat.com]
> Sent: Wednesday, August 29, 2018 9:01 PM
[...]
> > @@ -252,39 +228,21 @@ static int simplefb_clocks_get(struct simplefb_par
> *par,
> > static void simplefb_clocks_enable(struct simplefb_par *par,
> >struct platform_device *pdev)
> > {
> > - int i, ret;
> > + int ret;
> > +
> > + ret = clk_bulk_prepare_enable(par->clk_count, par->clks);
> > + if (ret)
> > + dev_warn(&pdev->dev, "failed to enable clocks\n");
>
> If clk_bulk_prepare_enable() fails, it leaves all clocks disabled, so you
> should
> not set par->clks_enabled = true; then.
>
Thanks for spotting this.
The original code wanted to keep the behavior as before.
But a bit more thinking that unlike the exist code, clk_bulk_prepare_enable will
automatically do reverse clean up once it fails.
So no need to set par->clks_enabled = true anymore.
Will fix it and resend.
Regards
Dong Aisheng
> Otherwise this patch looks good.
>
> Regards,
>
> Hans
RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Wednesday, August 29, 2018 11:09 AM
> To: A.s. Dong
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; shawn...@kernel.org; dl-linux-imx
> ; thor.tha...@linux.intel.com; linux-...@vger.kernel.org
> Subject: RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks
>
> Quoting A.s. Dong (2018-08-16 19:33:52)
> > Hi Stephen,
> >
> > Do you want me to resend this series for review?
> > It seems have been pending for quite a long time.
> >
> > Thor just pinged me for its status as he wants to use it.
> >
>
> I was waiting for someone to try them out or review them. Good that it
> happened!
>
> I've taken a look at the patches and I'm slightly annoyed with the API that
> passes in a double pointer to clk_bulk_data and returns a count of the number
> of clks found. I guess it's ok though. It's really just this
> line:
>
> devres->clks = *clks;
>
> which makes my brain all confused and go think about what's being assigned
> and if it's a struct copy or not.
>
> Maybe this on top would make it easier to take? I'll think about it tonight.
>
Looks like a good idea to me.
Will update and resend.
Thanks for the suggestion.
Regards
Dong Aisheng
> ---8<---
> diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c index
> 6d3ca5ec5de8..12c87457eca1 100644
> --- a/drivers/clk/clk-devres.c
> +++ b/drivers/clk/clk-devres.c
> @@ -81,9 +81,9 @@ int __must_check devm_clk_bulk_get_all(struct device
> *dev,
> if (!devres)
> return -ENOMEM;
>
> - ret = clk_bulk_get_all(dev, clks);
> + ret = clk_bulk_get_all(dev, &devres->clks);
> if (ret > 0) {
> - devres->clks = *clks;
> + *clks = devres->clks;
> devres->num_clks = ret;
> devres_add(dev, devres);
> } else {
RE: [PATCH] pinctrl: Convert to using %pOFn instead of device_node.name
> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, August 28, 2018 9:53 AM > To: linux-kernel@vger.kernel.org > Cc: Linus Walleij ; A.s. Dong > ; Fabio Estevam ; Shawn > Guo ; Stefan Agner ; Pengutronix > Kernel Team ; Sean Wang > ; Matthias Brugger ; > Carlo Caione ; Kevin Hilman ; > Jason Cooper ; Andrew Lunn ; > Gregory Clement ; Sebastian Hesselbarth > ; Jean-Christophe Plagniol-Villard > ; Nicolas Ferre ; > Alexandre Belloni ; Heiko Stuebner > ; Tony Lindgren ; Haojian Zhuang > ; Patrice Chotard ; > Barry Song ; Maxime Coquelin > ; Alexandre Torgue > ; Maxime Ripard ; > Chen-Yu Tsai ; linux-g...@vger.kernel.org; > linux-media...@lists.infradead.org; linux-arm-ker...@lists.infradead.org; > linux-amlo...@lists.infradead.org; linux-rockc...@lists.infradead.org; > linux-o...@vger.kernel.org > Subject: [PATCH] pinctrl: Convert to using %pOFn instead of device_node.name > > In preparation to remove the node name pointer from struct device_node, > convert printf users to use the %pOFn format specifier. > > Cc: Linus Walleij > Cc: Dong Aisheng > Cc: Fabio Estevam > Cc: Shawn Guo > Cc: Stefan Agner > Cc: Pengutronix Kernel Team > Cc: Sean Wang > Cc: Matthias Brugger > Cc: Carlo Caione > Cc: Kevin Hilman > Cc: Jason Cooper > Cc: Andrew Lunn > Cc: Gregory Clement > Cc: Sebastian Hesselbarth > Cc: Jean-Christophe Plagniol-Villard > Cc: Nicolas Ferre > Cc: Alexandre Belloni > Cc: Heiko Stuebner > Cc: Tony Lindgren > Cc: Haojian Zhuang > Cc: Patrice Chotard > Cc: Barry Song > Cc: Maxime Coquelin > Cc: Alexandre Torgue > Cc: Maxime Ripard > Cc: Chen-Yu Tsai > Cc: linux-g...@vger.kernel.org > Cc: linux-media...@lists.infradead.org > Cc: linux-arm-ker...@lists.infradead.org > Cc: linux-amlo...@lists.infradead.org > Cc: linux-rockc...@lists.infradead.org > Cc: linux-o...@vger.kernel.org > Signed-off-by: Rob Herring > --- > drivers/pinctrl/berlin/berlin.c | 6 ++-- > drivers/pinctrl/freescale/pinctrl-imx.c | 7 ++-- > drivers/pinctrl/freescale/pinctrl-imx1-core.c | 12 +++ For i.MX, Acked-by: Dong Aisheng Regards Dong Aisheng
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
Kindly ping again... This is really pending too long... Stephen & Shawn, Any suggestion on how to proceed this patch set? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Thursday, July 26, 2018 9:51 AM > To: linux-...@vger.kernel.org; sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > ; Jacky Bai ; dl-linux-imx > > Subject: RE: [PATCH V4 0/9] clk: add imx7ulp clk support > > Hi Stephen, > > Do you have a chance to look at it? > This patch series has been pending for quite a long time without much > comments. > > Regards > Dong Aisheng > > > -Original Message- > > From: A.s. Dong > > Sent: Wednesday, July 18, 2018 9:37 PM > > To: linux-...@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > Anson > > Huang ; Jacky Bai ; dl- > > linux-imx ; A.s. Dong > > Subject: [PATCH V4 0/9] clk: add imx7ulp clk support > > > > This is a rebased version of below patch series against latest clk tree. > > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > https://lkml.org/lkml/2018/3/16/310 > > > > This patch series intends to add imx7ulp clk support. > > > > i.MX7ULP Clock functions are under joint control of the System Clock > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > Core Mode Controller (CMC)1 blocks > > > > The clocking scheme provides clear separation between M4 domain and A7 > > domain. Except for a few clock sources shared between two domains, > > such as the System Oscillator clock, the Slow IRC (SIRC), and and the > > Fast IRC clock (FIRCLK), clock sources and clock management are > > separated and contained within each domain. > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > Note: this series only adds A7 clock domain support as M4 clock domain > > will be handled by M4 seperately. > > > > Change Log: > > v3->v4: > > * rebased to latest kernel > > * make scg and pcc separate nodes according to Rob's suggestion > > > > v2->v3: > > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy > >Others no changes. > > > > v1->v2: > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > > * use clk_hw apis to register clocks > > * use of_clk_add_hw_provider > > * split the clocks register process into two parts: early part for possible > >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for > >the left normal peripheral clocks registered by a platform driver. > > > > Dong Aisheng (9): > > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > > clk: imx: add pllv4 support > > clk: imx: add pfdv2 support > > clk: imx: add composite clk support > > dt-bindings: clock: add imx7ulp clock binding doc > > clk: imx: make mux parent strings const > > clk: imx: implement new clk_hw based APIs > > clk: imx: add imx7ulp clk driver > > > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + > > drivers/clk/clk-divider.c | 152 > +++ > > drivers/clk/clk-fractional-divider.c | 10 + > > drivers/clk/imx/Makefile | 6 +- > > drivers/clk/imx/clk-busy.c | 2 +- > > drivers/clk/imx/clk-composite.c| 85 + > > drivers/clk/imx/clk-fixup-mux.c| 2 +- > > drivers/clk/imx/clk-imx7ulp.c | 209 > + > > drivers/clk/imx/clk-pfdv2.c| 201 > > > drivers/clk/imx/clk-pllv4.c| 182 > ++ > > drivers/clk/imx/clk.c | 22 +++ > > drivers/clk/imx/clk.h | 92 - > > include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ > > include/linux/clk-provider.h | 17 ++ > > 14 files changed, 1166 insertions(+), 10 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > create mode 100644 drivers/clk/imx/clk-composite.c create mode > > 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 > > drivers/clk/imx/clk- pfdv2.c create mode 100644 > > drivers/clk/imx/clk-pllv4.c create mode 100644 > > include/dt-bindings/clock/imx7ulp-clock.h > > > > -- > > 2.7.4
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
Hi Alexandre, > -Original Message- > From: Alexandre Bailon [mailto:abai...@baylibre.com] > Sent: Wednesday, August 8, 2018 6:01 PM > To: A.s. Dong ; linux-...@vger.kernel.org; > sb...@kernel.org > Cc: Jacky Bai ; Anson Huang ; > mturque...@baylibre.com; linux-kernel@vger.kernel.org; dl-linux-imx > ; shawn...@kernel.org; > linux-arm-ker...@lists.infradead.org > Subject: Re: [PATCH V4 0/9] clk: add imx7ulp clk support > > Hi Dong Aisheng, > > On 07/26/2018 03:50 AM, A.s. Dong wrote: > > Hi Stephen, > > > > Do you have a chance to look at it? > > This patch series has been pending for quite a long time without much > comments. > I'm not a kernel maintainer but I would not review a series that has > checkpatch > errors. > Please run checkpatch, fix the errors and the warnings, and then resubmit a > series. Yes, I did it. There're some warnings. But unlike errors, normally warnings are judgable. For this patch set, all known warnings seems to me not need the fix. E.g. line over 80 or missing maintainer for new files BTW there's one special warning I don't see how to fix, seems reported wrongly. 0005-clk-imx-add-composite-clk-support.patch WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #47: new file mode 100644 WARNING: function definition argument 'const char * const' should also have an identifier name #145: FILE: drivers/clk/imx/clk.h:74: +struct clk_hw *imx_clk_composite(const char *name, total: 0 errors, 2 warnings, 104 lines checked NOTE: For some of the reported defects, checkpatch may be able to mechanically convert to the typical style using --fix or --fix-inplace. If you have better suggestions please let me know. Regards Dong Aisheng
RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks
Hi Stephen,
Do you want me to resend this series for review?
It seems have been pending for quite a long time.
Thor just pinged me for its status as he wants to use it.
Regards
Dong Aisheng
> -Original Message-
> From: A.s. Dong
> Sent: Wednesday, June 20, 2018 10:54 AM
> To: linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; dl-
> linux-imx
> Subject: RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks
>
> Ping
>
> > -----Original Message-
> > From: A.s. Dong
> > Sent: Friday, May 25, 2018 6:37 PM
> > To: linux-...@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org;
> > linux-arm-ker...@lists.infradead.org;
> > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; dl-
> > linux-imx ; A.s. Dong
> > Subject: [PATCH V3 0/4] clk: new APIs to handle all available clocks
> >
> > This patch series is a continue of discussion from here,
> > https://patchwork.kernel.org/patch/9986293/
> > that some users may want to handle all available clocks from device
> > tree without need to know the detailed clock information likes clock
> > numbers and names. This is useful in writing some generic drivers to handle
> clock part.
> >
> > Note:
> > This patch series is tested on MX6Q SDB cpufreq driver with a minor
> > change to switch to use clk_bulk_get_all.
> > But patch 4 only test compiling. Hopefully someone could help test the
> > function.
> >
> > v2->v3:
> > * address all comments from Stephen
> > * fix build warnings on other architectures.
> > v1->v2:
> > * add clk_bulk_{get|put}_all() which only supports DT platform
> > currently
> > * remove _all variants and the wrapper struct clk_bulk
> > * make of_clk_bulk_get and of_clk_bulk_get_all private until someone
> >proves they need it because they don't have a struct device pointer.
> >
> > Dong Aisheng (4):
> > clk: bulk: add of_clk_bulk_get()
> > clk: add new APIs to operate on all available clocks
> > clk: add managed version of clk_bulk_get_all
> > video: simplefb: switch to use clk_bulk API to simplify clock
> > operations
> >
> > drivers/clk/clk-bulk.c | 80
> > ++
> > drivers/clk/clk-devres.c | 24 +
> > drivers/video/fbdev/simplefb.c | 66 +++---
> > include/linux/clk.h| 65 +-
> > 4 files changed, 180 insertions(+), 55 deletions(-)
> >
> > --
> > 2.7.4
RE: [PATCH v7 1/6] dt-bindings: mailbox: allow mbox-cells to be equal to 0
> -Original Message- > From: Jassi Brar [mailto:jassisinghb...@gmail.com] > Sent: Thursday, July 26, 2018 7:37 PM > To: A.s. Dong > Cc: Oleksij Rempel ; Shawn Guo > ; Fabio Estevam ; Rob > Herring ; Mark Rutland ; > Vladimir Zapolskiy ; Sudeep Holla > ; Devicetree List ; > Linux Kernel Mailing List ; , Sascha Hauer > ; , linux-arm-ker...@lists.infradead.org, linux- > media...@lists.infradead.org, srv_heupstream ker...@lists.infradead.org>; dl-linux-imx > Subject: Re: [PATCH v7 1/6] dt-bindings: mailbox: allow mbox-cells to be > equal to 0 > > On Thu, Jul 26, 2018 at 4:30 PM, A.s. Dong wrote: > >> -Original Message- > >> From: Jassi Brar [mailto:jassisinghb...@gmail.com] > >> Sent: Thursday, July 26, 2018 5:42 PM > >> To: Oleksij Rempel > >> Cc: Shawn Guo ; Fabio Estevam > >> ; Rob Herring ; Mark > >> Rutland ; A.s. Dong ; > >> Vladimir Zapolskiy ; Sudeep Holla > >> ; Devicetree List ; > >> Linux Kernel Mailing List ; , Sascha > >> Hauer ; , > >> linux-arm-ker...@lists.infradead.org, linux- > >> media...@lists.infradead.org, srv_heupstream >> ker...@lists.infradead.org>; dl-linux-imx > >> Subject: Re: [PATCH v7 1/6] dt-bindings: mailbox: allow mbox-cells to > >> be equal to 0 > >> > >> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel > >> > >> wrote: > >> > From: Dong Aisheng > >> > > >> > Mailbox devices may have only one channel which means the > >> > mbox-cells at least 1 does not make sense for this type devices. > >> > Let's remove that limitation to allow the mbox-cells to be equal to 0. > >> > > >> OK > >> > >> But please realise that you'll have to write more code -- implement > >> your own > >> of_xlate() callback. > >> Most developers would prefer to call the only channel as channel > >> number 0, and use the common of_xlate implementation. > >> > > > > Yes, that's true because the common of_xlate assuming the mbox-cells is 1. > > And there's already such users: > > arch/arm/boot/dts/bcm283x.dtsi > > > You mean that is a good thing, right? No, I mean there's similar HW in kernel already that only has one channel. Are you suggesting even for one channel mailbox, we should still use Mbox-cells 1 and use 'mboxes = <&mailbox 0>' in devicetree? Regards Dong Aisheng
RE: [PATCH v7 1/6] dt-bindings: mailbox: allow mbox-cells to be equal to 0
> -Original Message- > From: Jassi Brar [mailto:jassisinghb...@gmail.com] > Sent: Thursday, July 26, 2018 5:42 PM > To: Oleksij Rempel > Cc: Shawn Guo ; Fabio Estevam > ; Rob Herring ; Mark > Rutland ; A.s. Dong ; > Vladimir Zapolskiy ; Sudeep Holla > ; Devicetree List ; > Linux Kernel Mailing List ; , Sascha Hauer > ; , linux-arm-ker...@lists.infradead.org, linux- > media...@lists.infradead.org, srv_heupstream ker...@lists.infradead.org>; dl-linux-imx > Subject: Re: [PATCH v7 1/6] dt-bindings: mailbox: allow mbox-cells to be > equal to 0 > > On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel > wrote: > > From: Dong Aisheng > > > > Mailbox devices may have only one channel which means the mbox-cells > > at least 1 does not make sense for this type devices. Let's remove > > that limitation to allow the mbox-cells to be equal to 0. > > > OK > > But please realise that you'll have to write more code -- implement your own > of_xlate() callback. > Most developers would prefer to call the only channel as channel number 0, > and use the common of_xlate implementation. > Yes, that's true because the common of_xlate assuming the mbox-cells is 1. And there's already such users: arch/arm/boot/dts/bcm283x.dtsi More comments will be on your reply of patch-3. Regards Dong Aisheng > -jassi
RE: [PATCH V4 0/9] clk: add imx7ulp clk support
Hi Stephen, Do you have a chance to look at it? This patch series has been pending for quite a long time without much comments. Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Wednesday, July 18, 2018 9:37 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; > Anson Huang ; Jacky Bai ; dl- > linux-imx ; A.s. Dong > Subject: [PATCH V4 0/9] clk: add imx7ulp clk support > > This is a rebased version of below patch series against latest clk tree. > [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > https://lkml.org/lkml/2018/3/16/310 > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > Core Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such > as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock > (FIRCLK), clock sources and clock management are separated and contained > within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain will > be handled by M4 seperately. > > Change Log: > v3->v4: > * rebased to latest kernel > * make scg and pcc separate nodes according to Rob's suggestion > > v2->v3: > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy >Others no changes. > > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for possible >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for >the left normal peripheral clocks registered by a platform driver. > > Dong Aisheng (9): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 87 + > drivers/clk/clk-divider.c | 152 +++ > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c| 85 + > drivers/clk/imx/clk-fixup-mux.c| 2 +- > drivers/clk/imx/clk-imx7ulp.c | 209 > + > drivers/clk/imx/clk-pfdv2.c| 201 > drivers/clk/imx/clk-pllv4.c| 182 ++ > drivers/clk/imx/clk.c | 22 +++ > drivers/clk/imx/clk.h | 92 - > include/dt-bindings/clock/imx7ulp-clock.h | 109 +++ > include/linux/clk-provider.h | 17 ++ > 14 files changed, 1166 insertions(+), 10 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 > include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4
RE: [PATCH v2 2/2] mmc: sdhci-esdhc-imx: fix indent
> -Original Message- > From: Stefan Agner [mailto:ste...@agner.ch] > Sent: Thursday, July 12, 2018 4:07 PM > To: adrian.hun...@intel.com; ulf.hans...@linaro.org > Cc: Fabio Estevam ; Bough Chen > ; A.s. Dong ; linux- > m...@vger.kernel.org; linux-kernel@vger.kernel.org; Stefan Agner > > Subject: [PATCH v2 2/2] mmc: sdhci-esdhc-imx: fix indent > > Fix indent. This also makes disable/enable clock blocks look alike. > > Signed-off-by: Stefan Agner Acked-by: Dong Aisheng Regards Dong Aisheng
RE: [PATCH v2 1/2] mmc: sdhci-esdhc-imx: disable clocks before changing frequency
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Thursday, July 12, 2018 4:07 PM
> To: adrian.hun...@intel.com; ulf.hans...@linaro.org
> Cc: Fabio Estevam ; Bough Chen
> ; A.s. Dong ; linux-
> m...@vger.kernel.org; linux-kernel@vger.kernel.org; Stefan Agner
>
> Subject: [PATCH v2 1/2] mmc: sdhci-esdhc-imx: disable clocks before
> changing frequency
>
> In the uSDHC case (e.g. i.MX 6) clocks only get disabled if frequency is set
> to 0.
> However, it could be that the stack asks for a frequency change while clocks
> are on. In that case the function clears the divider registers (by clearing
> ESDHC_CLOCK_MASK) while the clock is enabled! This causes a short period
> of time where the clock is undivided (on a i.MX 6DL a clock of 196MHz has
> been measured).
>
> For older IP variants the driver disables clock by clearing some bits in
> ESDHC_SYSTEM_CONTROL.
>
> Make sure to disable card clock before changing frequency for uSDHC IP
> variants too.
Looks ok to me.
Acked-by: Dong Aisheng
Regards
Dong Aisheng
>
> Signed-off-by: Stefan Agner
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-
> esdhc-imx.c
> index 85fd5a8b0b6d..acacd8481473 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -708,14 +708,14 @@ static inline void esdhc_pltfm_set_clock(struct
> sdhci_host *host,
> int div = 1;
> u32 temp, val;
>
> + if (esdhc_is_usdhc(imx_data)) {
> + val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
> + writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
> + host->ioaddr + ESDHC_VENDOR_SPEC);
> + }
> +
> if (clock == 0) {
> host->mmc->actual_clock = 0;
> -
> - if (esdhc_is_usdhc(imx_data)) {
> - val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
> - writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
> - host->ioaddr +
> ESDHC_VENDOR_SPEC);
> - }
> return;
> }
>
> --
> 2.18.0
RE: [PATCH V4 3/5] mailbox: imx: add imx mu support
Hi Jassi, > -Original Message- > From: Jassi Brar [mailto:jassisinghb...@gmail.com] > Sent: Thursday, July 12, 2018 1:01 AM > To: A.s. Dong > Cc: Sascha Hauer ; linux-arm- > ker...@lists.infradead.org; donga...@gmail.com; linux- > ker...@vger.kernel.org; Oleksij Rempel ; dl- > linux-imx ; ker...@pengutronix.de; Fabio Estevam > ; shawn...@kernel.org > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > > > > bcm seems is using peek to receive data, not only checking the data > > availability, right? > > drivers/mailbox/bcm-flexrm-mailbox.c > > > As I said, if fetching data from remote don't need to sleep, you can call > mbox_chan_received_data() from peek(). Otherwise not. Got it. So it seems work for i.MX. Thanks. Regards Dong Aisheng
RE: [PATCH V4 3/5] mailbox: imx: add imx mu support
Hi Jassi, > -Original Message- > From: Jassi Brar [mailto:jassisinghb...@gmail.com] > Sent: Thursday, July 12, 2018 12:32 AM > To: A.s. Dong > Cc: Sascha Hauer ; linux-arm- > ker...@lists.infradead.org; donga...@gmail.com; linux- > ker...@vger.kernel.org; Oleksij Rempel ; dl- > linux-imx ; ker...@pengutronix.de; Fabio Estevam > ; shawn...@kernel.org > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > > On Wed, Jul 11, 2018 at 6:28 PM, A.s. Dong wrote: > > Hi Jassi, > > > >> -Original Message- > >> From: Jassi Brar [mailto:jassisinghb...@gmail.com] > >> Sent: Wednesday, July 11, 2018 6:44 PM > >> To: A.s. Dong > >> Cc: Sascha Hauer ; linux-arm- > >> ker...@lists.infradead.org; donga...@gmail.com; linux- > >> ker...@vger.kernel.org; Oleksij Rempel ; dl- > >> linux-imx ; ker...@pengutronix.de; Fabio Estevam > >> ; shawn...@kernel.org > >> Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > >> > >> On Wed, Jul 11, 2018 at 4:07 PM, A.s. Dong > wrote: > >> > > >> > > -Original Message- > >> > > From: Sascha Hauer [mailto:s.ha...@pengutronix.de] > >> > > Sent: Wednesday, July 11, 2018 3:55 PM > >> > > To: A.s. Dong > >> > > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; > >> > > Jassi Brar ; > >> > > linux-kernel@vger.kernel.org; Oleksij Rempel > >> > > ; dl-linux-imx ; > >> > > ker...@pengutronix.de; Fabio Estevam ; > >> > > shawn...@kernel.org > >> > > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > >> > > > >> > > On Wed, Jul 11, 2018 at 07:29:38AM +, A.s. Dong wrote: > >> > > > Hi Sascha, > >> > > > > >> > > > > -Original Message- > >> > > > > From: Sascha Hauer [mailto:s.ha...@pengutronix.de] > >> > > > > Sent: Tuesday, July 10, 2018 10:20 PM > >> > > > > To: A.s. Dong > >> > > > > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; > >> > > > > Jassi Brar ; > >> > > > > linux-kernel@vger.kernel.org; Oleksij Rempel > >> > > > > ; dl-linux-imx ; > >> > > > > ker...@pengutronix.de; Fabio Estevam > ; > >> > > > > shawn...@kernel.org > >> > > > > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > >> > > > > > >> > > > > Hi, > >> > > > > > >> > > > > On Sun, Jul 08, 2018 at 10:56:55PM +0800, Dong Aisheng wrote: > >> > > > > > This is used for i.MX multi core communication. > >> > > > > > e.g. A core to SCU firmware(M core) on MX8. > >> > > > > > > >> > > > > > Tx is using polling mode while Rx is interrupt driven and > >> > > > > > schedule a hrtimer to receive remain words if have more > >> > > > > > than > >> > > > > > 4 words. > >> > > > > > >> > > > > You told us that using interrupts is not possible due to > >> > > > > miserable performance, we then provided you a way with which > >> > > > > you > >> could poll. > >> > > > > Why are you using interrupts now? > >> > > > > > >> > > > > >> > > > Because mailbox framework does not support sync rx now, I think > >> > > > we do not need to wait for that feature done first as it's > >> > > > independent and separate features of framework. > >> > > > >> > > You can wait forever for this feature, nobody will add it for you. > >> > > It's up to you to add support for that feature. Who else should > >> > > add this > >> feature if not you? > >> > > And when will you add that feature if not now when you actually need > it? > >> > > It is common practice that you adjust the frameworks to your > >> > > needs rather than working around them. > >> > > > >> > > >> > I'm willing to add it. Just because you said Jassi already had the > >> > idea on how to Implement it and does not add much complexity. So I > >> > just > >> want to see his patches. > >> > But if he did
RE: [PATCH V4 3/5] mailbox: imx: add imx mu support
Hi Jassi,
> -Original Message-
> From: Jassi Brar [mailto:jassisinghb...@gmail.com]
> Sent: Wednesday, July 11, 2018 6:44 PM
> To: A.s. Dong
> Cc: Sascha Hauer ; linux-arm-
> ker...@lists.infradead.org; donga...@gmail.com; linux-
> ker...@vger.kernel.org; Oleksij Rempel ; dl-
> linux-imx ; ker...@pengutronix.de; Fabio Estevam
> ; shawn...@kernel.org
> Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support
>
> On Wed, Jul 11, 2018 at 4:07 PM, A.s. Dong wrote:
> >
> > > -Original Message-
> > > From: Sascha Hauer [mailto:s.ha...@pengutronix.de]
> > > Sent: Wednesday, July 11, 2018 3:55 PM
> > > To: A.s. Dong
> > > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; Jassi
> > > Brar ; linux-kernel@vger.kernel.org;
> > > Oleksij Rempel ; dl-linux-imx
> > > ; ker...@pengutronix.de; Fabio Estevam
> > > ; shawn...@kernel.org
> > > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support
> > >
> > > On Wed, Jul 11, 2018 at 07:29:38AM +, A.s. Dong wrote:
> > > > Hi Sascha,
> > > >
> > > > > -Original Message-
> > > > > From: Sascha Hauer [mailto:s.ha...@pengutronix.de]
> > > > > Sent: Tuesday, July 10, 2018 10:20 PM
> > > > > To: A.s. Dong
> > > > > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com;
> > > > > Jassi Brar ;
> > > > > linux-kernel@vger.kernel.org; Oleksij Rempel
> > > > > ; dl-linux-imx ;
> > > > > ker...@pengutronix.de; Fabio Estevam ;
> > > > > shawn...@kernel.org
> > > > > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Sun, Jul 08, 2018 at 10:56:55PM +0800, Dong Aisheng wrote:
> > > > > > This is used for i.MX multi core communication.
> > > > > > e.g. A core to SCU firmware(M core) on MX8.
> > > > > >
> > > > > > Tx is using polling mode while Rx is interrupt driven and
> > > > > > schedule a hrtimer to receive remain words if have more than
> > > > > > 4 words.
> > > > >
> > > > > You told us that using interrupts is not possible due to
> > > > > miserable performance, we then provided you a way with which you
> could poll.
> > > > > Why are you using interrupts now?
> > > > >
> > > >
> > > > Because mailbox framework does not support sync rx now, I think we
> > > > do not need to wait for that feature done first as it's
> > > > independent and separate features of framework.
> > >
> > > You can wait forever for this feature, nobody will add it for you.
> > > It's up to you to add support for that feature. Who else should add this
> feature if not you?
> > > And when will you add that feature if not now when you actually need it?
> > > It is common practice that you adjust the frameworks to your needs
> > > rather than working around them.
> > >
> >
> > I'm willing to add it. Just because you said Jassi already had the
> > idea on how to Implement it and does not add much complexity. So I just
> want to see his patches.
> > But if he did not work on it, I can also help on it.
> >
> I am not much aware of the history of this conversation... but it seems you
> need to make use of mbox_chan_ops.peek_data().
>
> If not that, please let me know the requirement.
>
Thanks for the suggestion.
It looks to me may work.
From the definition, it seems it's used to pull data from remote side.
/**
* mbox_client_peek_data - A way for client driver to pull data
* received from remote by the controller.
* @chan: Mailbox channel assigned to this client.
*
* A poke to controller driver for any received data.
* The data is actually passed onto client via the
* mbox_chan_received_data()
* The call can be made from atomic context, so the controller's
* implementation of peek_data() must not sleep.
*
* Return: True, if controller has, and is going to push after this,
* some data.
* False, if controller doesn't have any data to be read.
*/
bool mbox_client_peek_data(struct mbox_chan *chan)
{
if (chan->mbox->ops->peek_data)
return chan->mbox->ops->peek_data(chan);
return false;
}
EXPORT_SYMBOL_GPL(mbox_client_peek_data);
But it seems most users in kernel simply implement it as a data avai
RE: [PATCH V4 3/5] mailbox: imx: add imx mu support
> -Original Message- > From: Sascha Hauer [mailto:s.ha...@pengutronix.de] > Sent: Wednesday, July 11, 2018 3:55 PM > To: A.s. Dong > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; Jassi Brar > ; linux-kernel@vger.kernel.org; Oleksij Rempel > ; dl-linux-imx ; > ker...@pengutronix.de; Fabio Estevam ; > shawn...@kernel.org > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > > On Wed, Jul 11, 2018 at 07:29:38AM +, A.s. Dong wrote: > > Hi Sascha, > > > > > -Original Message- > > > From: Sascha Hauer [mailto:s.ha...@pengutronix.de] > > > Sent: Tuesday, July 10, 2018 10:20 PM > > > To: A.s. Dong > > > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; Jassi > > > Brar ; linux-kernel@vger.kernel.org; > > > Oleksij Rempel ; dl-linux-imx > > > ; ker...@pengutronix.de; Fabio Estevam > > > ; shawn...@kernel.org > > > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > > > > > > Hi, > > > > > > On Sun, Jul 08, 2018 at 10:56:55PM +0800, Dong Aisheng wrote: > > > > This is used for i.MX multi core communication. > > > > e.g. A core to SCU firmware(M core) on MX8. > > > > > > > > Tx is using polling mode while Rx is interrupt driven and schedule > > > > a hrtimer to receive remain words if have more than > > > > 4 words. > > > > > > You told us that using interrupts is not possible due to miserable > > > performance, we then provided you a way with which you could poll. > > > Why are you using interrupts now? > > > > > > > Because mailbox framework does not support sync rx now, I think we do > > not need to wait for that feature done first as it's independent and > > separate features of framework. > > You can wait forever for this feature, nobody will add it for you. It's up to > you > to add support for that feature. Who else should add this feature if not you? > And when will you add that feature if not now when you actually need it? > It is common practice that you adjust the frameworks to your needs rather > than working around them. > I'm willing to add it. Just because you said Jassi already had the idea on how to Implement it and does not add much complexity. So I just want to see his patches. But if he did not work on it, I can also help on it. Another reason is i did not observe regression as before, so it looks like the irq is an applicable way currently and not must use polling at this point as that's an independent new feature of framework. So irq mode is the quickest way to demo the mbox using as we already had experience before. > > > > So for now, we're just using the common way in kernel as arm scpi and ti > > sci. > > When framework supports it, we can easily switch to it. > > > > I optimized the performance a bit by removing the unnecessary memcopy > > between tx/tx messages. The test result of booting time shows there's > > no obvious regressions. I'm not sure whether it's due to we're booting > > a minimum system or the extra cost is very minor to be noticed due to > > not too much cmds sent during booting. > > Your boot time argument seems to be a very weak one. unnecessary > memcpys of a few bytes only take a fraction of the time interrupt latencies > introduce. > Yes, interrupt latency may be the major part. > > (Copy Peng to comments more as he tried and reported that performance > > drop with vendor tree) > > > > From the time measurement of sc_call_rpc, we can see that most rpc > > command In polling mode can finish within 10us and very rare ones over > 20us. > > If switched to irq mode, those 10us cmds will change to about 20us. > > > > But the overall booting time did not increase much. Maybe the irq mode > > also saves some CPU MIPS to execute other works in parallel? > > > > > We also suggested a way how the SCU mode could be integrated into > > > the generic MU support driver Oleksij posted and now you send a > > > driver which uses the same name as Oleksijs driver, but it only and > > > exclusively works in SCU mode. This doesn't bring us forward. > > > > > > > Can Oleksij's patch be implemented against this one? > > As I remember you said we've still not determined whether Oleksij's > > approach is the most suitable way and it's still under discussion. > > (Actually TI's approach looks better which is more simiar as SCU way?) > > > > Furthermore, from this patch, you wi
RE: [PATCH V4 3/5] mailbox: imx: add imx mu support
Hi Sascha, > -Original Message- > From: Sascha Hauer [mailto:s.ha...@pengutronix.de] > Sent: Tuesday, July 10, 2018 10:20 PM > To: A.s. Dong > Cc: linux-arm-ker...@lists.infradead.org; donga...@gmail.com; Jassi Brar > ; linux-kernel@vger.kernel.org; Oleksij Rempel > ; dl-linux-imx ; > ker...@pengutronix.de; Fabio Estevam ; > shawn...@kernel.org > Subject: Re: [PATCH V4 3/5] mailbox: imx: add imx mu support > > Hi, > > On Sun, Jul 08, 2018 at 10:56:55PM +0800, Dong Aisheng wrote: > > This is used for i.MX multi core communication. > > e.g. A core to SCU firmware(M core) on MX8. > > > > Tx is using polling mode while Rx is interrupt driven and schedule a > > hrtimer to receive remain words if have more than > > 4 words. > > You told us that using interrupts is not possible due to miserable > performance, we then provided you a way with which you could poll. Why > are you using interrupts now? > Because mailbox framework does not support sync rx now, I think we do not need to wait for that feature done first as it's independent and separate features of framework. So for now, we're just using the common way in kernel as arm scpi and ti sci. When framework supports it, we can easily switch to it. I optimized the performance a bit by removing the unnecessary memcopy between tx/tx messages. The test result of booting time shows there's no obvious regressions. I'm not sure whether it's due to we're booting a minimum system or the extra cost is very minor to be noticed due to not too much cmds sent during booting. (Copy Peng to comments more as he tried and reported that performance drop with vendor tree) >From the time measurement of sc_call_rpc, we can see that most rpc command In polling mode can finish within 10us and very rare ones over 20us. If switched to irq mode, those 10us cmds will change to about 20us. But the overall booting time did not increase much. Maybe the irq mode also saves some CPU MIPS to execute other works in parallel? > We also suggested a way how the SCU mode could be integrated into the > generic MU support driver Oleksij posted and now you send a driver which > uses the same name as Oleksijs driver, but it only and exclusively works in > SCU mode. This doesn't bring us forward. > Can Oleksij's patch be implemented against this one? As I remember you said we've still not determined whether Oleksij's approach is the most suitable way and it's still under discussion. (Actually TI's approach looks better which is more simiar as SCU way?) Furthermore, from this patch, you will notice that Oleksij's patch almost did not work for SCU at all. I have to totally rewrite one for SCU. So I did not write against his patch as it does not help. And Oleksij's patch is quite simple while the SCU one is much complicated than his one. So we probably better get SCU done first. > We suggested a binding that allows coexisting of the SCU mode and the > generic mode of the MU by putting the mode information into the second > mbox-cell. Why don't you use this? > You mean this? +#define IMX_MU_CHANNEL00 +#define IMX_MU_CHANNEL11 +#define IMX_MU_CHANNEL22 +#define IMX_MU_CHANNEL33 +#define IMX_MU_CHANNEL_IMX8_SCU 4 It's hard for me to believe it's correct and it's over abstract to HW. So I thought using mbox-cells to distinguish seems to be better. > I don't think it's necessary to rewrite Oleksijs driver, instead it should > rather > be extended with the code I already provided as an example. With that we > could make both of us happy since we can both have a suitable driver and > even share most of the MU code. As I said above, I even can't reuse 90%+ code of Oleksijs driver. So I can't see the meaning to demo the code on top of this driver. We can review the SCU implementation directly with this driver which is more easy. Then we can decide how to merge them together. Regards Dong Aisheng > > Regards, > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fww > w.pengutronix.de%2F&data=02%7C01%7Caisheng.dong%40nxp.com%7 > Cb359a3eddee54bf1b40a08d5e6702f22%7C686ea1d3bc2b4c6fa92cd99c5c301 > 635%7C0%7C0%7C636668291863846639&sdata=hSucaLRfCB1j1McwlfO% > 2FL0921QXiHg68sl%2B23CvEp4Q%3D&reserved=0 | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
RE: [PATCH 1/3] mmc: sdhci-esdhc-imx: get rid of support_vsel
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Thursday, June 28, 2018 4:13 PM
> To: adrian.hun...@intel.com; ulf.hans...@linaro.org
> Cc: Fabio Estevam ; Bough Chen
> ; A.s. Dong ;
> mich...@amarulasolutions.com; rmk+ker...@armlinux.org.uk; linux-
> m...@vger.kernel.org; linux-kernel@vger.kernel.org; Stefan Agner
>
> Subject: [PATCH 1/3] mmc: sdhci-esdhc-imx: get rid of support_vsel
>
> The field support_vsel is currently only used in the device tree case. Get rid
> of it. No change in behavior.
>
I'm not sure if it's quite necessary to remove it as it's used to bypass
100Mhz above pad settings look up which is meaningless if user claims
no 1-8 v support.
If you remove it, probably you still need better check the quirk for
Pad state look up.
Regards
Dong Aisheng
> Signed-off-by: Stefan Agner
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++--
> include/linux/platform_data/mmc-esdhc-imx.h | 2 --
> 2 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-
> esdhc-imx.c
> index 6f444731754d..20a420b765b3 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -1145,18 +1145,14 @@ sdhci_esdhc_imx_probe_dt(struct
> platform_device *pdev,
>&boarddata->tuning_start_tap);
>
> if (of_find_property(np, "no-1-8-v", NULL))
> - boarddata->support_vsel = false;
> - else
> - boarddata->support_vsel = true;
> + host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
>
> if (of_property_read_u32(np, "fsl,delay-line", &boarddata-
> >delay_line))
> boarddata->delay_line = 0;
>
> mmc_of_parse_voltage(np, &host->ocr_mask);
>
> - /* sdr50 and sdr104 need work on 1.8v signal voltage */
> - if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
> - !IS_ERR(imx_data->pins_default)) {
> + if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default))
> {
> imx_data->pins_100mhz = pinctrl_lookup_state(imx_data-
> >pinctrl,
>
> ESDHC_PINCTRL_STATE_100MHZ);
> imx_data->pins_200mhz = pinctrl_lookup_state(imx_data-
> >pinctrl,
> diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
> b/include/linux/platform_data/mmc-esdhc-imx.h
> index 7daa78a2f342..640dec8b5b0c 100644
> --- a/include/linux/platform_data/mmc-esdhc-imx.h
> +++ b/include/linux/platform_data/mmc-esdhc-imx.h
> @@ -34,7 +34,6 @@ enum cd_types {
> * @cd_gpio: gpio for card_detect interrupt
> * @wp_type: type of write_protect method (see wp_types enum above)
> * @cd_type: type of card_detect method (see cd_types enum above)
> - * @support_vsel: indicate it supports 1.8v switching
> */
>
> struct esdhc_platform_data {
> @@ -43,7 +42,6 @@ struct esdhc_platform_data {
> enum wp_types wp_type;
> enum cd_types cd_type;
> int max_bus_width;
> - bool support_vsel;
> unsigned int delay_line;
> unsigned int tuning_step; /* The delay cell steps in tuning
> procedure */
> unsigned int tuning_start_tap; /* The start delay cell point in tuning
> procedure */
> --
> 2.18.0
RE: [PATCH v2] mmc: sdhci-esdhc-imx: allow 1.8V modes without 100/200MHz pinctrl states
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Wednesday, July 4, 2018 11:08 PM
> To: adrian.hun...@intel.com; ulf.hans...@linaro.org
> Cc: Fabio Estevam ; Bough Chen
> ; A.s. Dong ;
> mich...@amarulasolutions.com; rmk+ker...@armlinux.org.uk; linux-
> m...@vger.kernel.org; linux-kernel@vger.kernel.org; Stefan Agner
>
> Subject: [PATCH v2] mmc: sdhci-esdhc-imx: allow 1.8V modes without
> 100/200MHz pinctrl states
>
> If pinctrl nodes for 100/200MHz are missing, the controller should not select
> any mode which need signal frequencies 100MHz or higher.
> To prevent such speed modes the driver currently uses the quirk flag
> SDHCI_QUIRK2_NO_1_8_V. This works nicely for SD cards since 1.8V signaling
> is required for all faster modes and slower modes use 3.3V signaling only.
>
> However, there are eMMC modes which use 1.8V signaling and run below
> 100MHz, e.g. DDR52 at 1.8V. With using SDHCI_QUIRK2_NO_1_8_V this
> mode is prevented. When using a fixed 1.8V regulator as vqmmc-supply the
> stack has no valid mode to use. In this tenuous situation the kernel
> continuously prints voltage switching errors:
> mmc1: Switching to 3.3V signalling voltage failed
>
>From current code, the NO_1_8_V quirk seems like only affect sd card.
The 1.8v timing is still allowed for eMMC 1_8V DDR.
See below:
if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
(mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
host->flags |= SDHCI_SIGNALING_180;
Due to i have no board to try that case, can you please help detail more on how
the
eMMC DDR52 is blocked due to that quirk?
Regards
Dong Aisheng
> Avoid using SDHCI_QUIRK2_NO_1_8_V and prevent faster modes by altering
> the SDHCI capability register. With that the stack is able to select 1.8V
> modes
> even if no faster pinctrl states are available:
> # cat /sys/kernel/debug/mmc1/ios
> ...
> timing spec:8 (mmc DDR52)
> signal voltage: 1 (1.80 V)
> ...
>
> Link:
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flkml
> .kernel.org%2Fr%2F20180628081331.13051-1-
> stefan%40agner.ch&data=02%7C01%7Caisheng.dong%40nxp.com%7Ca
> 32bdbdb4e854ed1a49008d5e1bfeae2%7C686ea1d3bc2b4c6fa92cd99c5c30163
> 5%7C0%7C0%7C636663136759720275&sdata=%2F2gJ%2BA0fHCzzUehD7
> 9knsfy3WMj4Okp%2BcxXB70MI5y8%3D&reserved=0
> Signed-off-by: Stefan Agner
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 21 +
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-
> esdhc-imx.c
> index 20a420b765b3..e96d969ab2c3 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -312,6 +312,15 @@ static u32 esdhc_readl_le(struct sdhci_host *host,
> int reg)
>
> if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
> val |= SDHCI_SUPPORT_HS400;
> +
> + /*
> + * Do not advertise faster UHS modes if there are no
> + * pinctrl states for 100MHz/200MHz.
> + */
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> + IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50
> + | SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> }
> }
>
> @@ -1157,18 +1166,6 @@ sdhci_esdhc_imx_probe_dt(struct
> platform_device *pdev,
>
> ESDHC_PINCTRL_STATE_100MHZ);
> imx_data->pins_200mhz = pinctrl_lookup_state(imx_data-
> >pinctrl,
>
> ESDHC_PINCTRL_STATE_200MHZ);
> - if (IS_ERR(imx_data->pins_100mhz) ||
> - IS_ERR(imx_data->pins_200mhz)) {
> - dev_warn(mmc_dev(host->mmc),
> - "could not get ultra high speed state, work on
> normal mode\n");
> - /*
> - * fall back to not supporting uhs by specifying no
> - * 1.8v quirk
> - */
> - host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
> - }
> - } else {
> - host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
> }
>
> /* call to generic mmc_of_parse to support additional capabilities */
> --
> 2.18.0
RE: [RFC] Configure i.MX6 RGMII pad group control registers from device tree
Copy Andy & Frank, > -Original Message- > From: Michal Vokáč [mailto:michal.vo...@ysoft.com] > Sent: Tuesday, June 12, 2018 11:10 PM > To: linux-g...@vger.kernel.org > Cc: linux-arm-ker...@lists.infradead.org; Shawn Guo > ; Sascha Hauer ; Fabio > Estevam ; Rob Herring ; > devicet...@vger.kernel.org; A.s. Dong ; Fabio > Estevam ; Shawn Guo ; > Stefan Agner ; Pengutronix Kernel Team > ; Linus Walleij ; linux- > ker...@vger.kernel.org > Subject: Re: [RFC] Configure i.MX6 RGMII pad group control registers from > device tree > > On 11.6.2018 14:36, Michal Vokáč wrote: > > Ahoj, > > > > To configure individual pad's characteristics on i.MX6 SoC a fsl,pins > > = property can be used. Is there any convenient > > way to configure the pad group control registers? > > > > The issue is that some bits (DDR_SEL and ODT) in the individual RGMII > > pad control registers are read-only. To tweak those parameters (signal > > voltage and termination resistors) one need to write to the pad group > > control registers for the whole RGMII pad group. Namely > > IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII and > > IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM. The group registers in general > are not accessible from the list in arch/arm/boot/dts/imx6dl-pinfunc.h. > > > > I could not find any other way to change the group registers than > > hacking-in some lines into the imx6q_init_machine(void) function in > > arch/arm/mach-imx/mach-imx6q.c source. As I work towards upstreaming > > my board this should be done from my device tree or solved in some > universal way. > > > > Any hints will be much appreciated. > > Michal > > I figured out this is more "pinctrl-imx.c" than "device-tree" related so I am > kindly adding maintainers of that file in hope somebody will shed some light > to it. > > I am diving deeper into the code and it seems there really is no generic > option to set the i.MX6 pad group control registers from device tree. > Or am I looking at the problem from a wrong angle? > Yes, there's a few special pad group ctrl registers (e.g. DRAM and RGMII for mx6q) which are not added In the pinctrl driver support. > How should we deal with boards that need to configure some pad > characteristics available only through the pad group control registers? > Andy, How do we handle it internally? > I also raised this question at the NXP community forum [1] and get quite > unsatisfying answer so far. I would love to find/implement a proper and > universal solution. > There're probably two ways to do it: 1) handle it in fec driver by parsing a specific property 2) Add a new pad group into pinctrl driver support e.g. MX6Q_PAD_CTL_GRP_RGMII_TERM MX6Q_PAD_CTL_GRP_DDR_TYPE_RGMII I may prefer to 2). Regards Dong Aisheng > Thanks in advance for your time, > Michal > > [1] > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fco > mmunity.nxp.com%2Fthread%2F477464&data=02%7C01%7Caisheng.dong%4 > 0nxp.com%7Ca3e5463eb06a47f1121008d5d0768a04%7C686ea1d3bc2b4c6fa9 > 2cd99c5c301635%7C0%7C1%7C636644129914162495&sdata=xqtBS8uX%2BSzq > 5m6tbNaLzCkB7ezgHSnyu9GQ3K13cW8%3D&reserved=0
RE: [PATCH v4 1/2] dt-bindings: add binding for i.MX8MQ IOMUXC
> -Original Message-
> From: Abel Vesa
> Sent: Wednesday, June 20, 2018 8:24 PM
> To: Lucas Stach ; A.s. Dong
>
> Cc: linux-g...@vger.kernel.org; dl-linux-imx ; Shawn
> Guo ; Pengutronix Kernel Team
> ; Linus Walleij ; Rob
> Herring ; Mark Rutland ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Abel Vesa
> ; Abel Vesa
> Subject: [PATCH v4 1/2] dt-bindings: add binding for i.MX8MQ IOMUXC
>
> This adds the binding for the i.MX8MQ pin controller, in the same fashion as
> earlier i.MX SoCs.
>
> Signed-off-by: Abel Vesa
> ---
> .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt| 29
> ++
> 1 file changed, 29 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> new file mode 100644
> index 000..f11a3f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> @@ -0,0 +1,29 @@
> +* Freescale IMX8MQ IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this
> +directory for common binding part and usage.
> +
> +Required properties:
> +- compatible: "fsl,imx8mq-iomuxc"
> +- fsl,pins: each entry consists of 6 integers and represents the mux
> +and config
> + setting for one pin. The first 5 integers +input_reg mux_val
> + input_val> are specified using a PIN_FUNC_ID macro, which can be
> +found in
> + imx8mq-pinfunc.h under device tree source folder. The last integer
> +CONFIG is
> + the pad setting value like pull-up on this pin. Please refer to
> +i.MX8M Quad
> + Reference Manual for detailed CONFIG settings.
> +
> +Examples:
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> +};
> +
> +&iomuxc {
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x49
> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x49
> + >;
> + };
> +};
How about giving more detailed information in the example as it only shows
show the pinctrl group part.
e.g.
iomuxc: iomuxc@3033 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x0 0x3033 0x0 0x1>;
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
};
Other than that:
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> --
> 2.7.4
RE: [PATCH v4 2/2] pinctrl: imx: add driver for i.MX8MQ
Hi Abel,
The patch mostly looks good to me.
Only a few minor comments.
> -Original Message-
> From: Abel Vesa
> Sent: Wednesday, June 20, 2018 8:24 PM
> To: Lucas Stach ; A.s. Dong
>
> Cc: linux-g...@vger.kernel.org; dl-linux-imx ; Shawn
> Guo ; Pengutronix Kernel Team
> ; Linus Walleij ; Rob
> Herring ; Mark Rutland ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Abel Vesa
> ; Abel Vesa
> Subject: [PATCH v4 2/2] pinctrl: imx: add driver for i.MX8MQ
>
> From: Lucas Stach
>
> The i.MX8MQ pincontrol works in a similar way to the earlier i.MX SoCs.
> This driver builds on top of the generic pinconf handling introduced with the
> i.MX7ULP pinctrl driver.
The commit message needs update as it does not build on top
of the generic pinconf now.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Abel Vesa
> ---
> drivers/pinctrl/freescale/Kconfig | 7 +
> drivers/pinctrl/freescale/Makefile | 1 +
> drivers/pinctrl/freescale/pinctrl-imx8mq.c | 356
> +
> 3 files changed, 364 insertions(+)
> create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mq.c
>
> diff --git a/drivers/pinctrl/freescale/Kconfig
> b/drivers/pinctrl/freescale/Kconfig
> index 0d8ba1e..dccf64c 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -117,6 +117,13 @@ config PINCTRL_IMX7ULP
> help
> Say Y here to enable the imx7ulp pinctrl driver
>
> +config PINCTRL_IMX8MQ
> + bool "IMX8MQ pinctrl driver"
> + depends on SOC_IMX8MQ
> + select PINCTRL_IMX
> + help
> + Say Y here to enable the imx8mq pinctrl driver
> +
> config PINCTRL_VF610
> bool "Freescale Vybrid VF610 pinctrl driver"
> depends on SOC_VF610
> diff --git a/drivers/pinctrl/freescale/Makefile
> b/drivers/pinctrl/freescale/Makefile
> index 368be8c..73175b3 100644
> --- a/drivers/pinctrl/freescale/Makefile
> +++ b/drivers/pinctrl/freescale/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX)+= pinctrl-imx6sx.o
> obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
> obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
> obj-$(CONFIG_PINCTRL_IMX7ULP)+= pinctrl-imx7ulp.o
> +obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
> obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
> obj-$(CONFIG_PINCTRL_MXS)+= pinctrl-mxs.o
> obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c
> b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
> new file mode 100644
> index 000..be2c9c2
> --- /dev/null
> +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
> @@ -0,0 +1,356 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
2017-2018
> + * Copyright (C) 2018 Pengutronix, Lucas Stach
> +*/
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pinctrl-imx.h"
> +
> +enum imx8mq_pads {
> + MX8MQ_PAD_RESERVE0 = 0,
> + MX8MQ_PAD_RESERVE1 = 1,
> + MX8MQ_PAD_RESERVE2 = 2,
> + MX8MQ_PAD_RESERVE3 = 3,
> + MX8MQ_PAD_RESERVE4 = 4,
> + MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
> + MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,
> + MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,
> + MX8MQ_IOMUXC_POR_B_SNVSMIX = 8,
> + MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,
> + MX8MQ_IOMUXC_GPIO1_IO00 = 10,
> + MX8MQ_IOMUXC_GPIO1_IO01 = 11,
> + MX8MQ_IOMUXC_GPIO1_IO02 = 12,
> + MX8MQ_IOMUXC_GPIO1_IO03 = 13,
> + MX8MQ_IOMUXC_GPIO1_IO04 = 14,
> + MX8MQ_IOMUXC_GPIO1_IO05 = 15,
> + MX8MQ_IOMUXC_GPIO1_IO06 = 16,
> + MX8MQ_IOMUXC_GPIO1_IO07 = 17,
> + MX8MQ_IOMUXC_GPIO1_IO08 = 18,
> + MX8MQ_IOMUXC_GPIO1_IO09 = 19,
> + MX8MQ_IOMUXC_GPIO1_IO10 = 20,
> + MX8MQ_IOMUXC_GPIO1_IO11 = 21,
> + MX8MQ_IOMUXC_GPIO1_IO12 = 22,
> + MX8MQ_IOMUXC_GPIO1_IO13 = 23,
> + MX8MQ_IOMUXC_GPIO1_IO14 = 24,
> + MX8MQ_IOMUXC_GPIO1_IO15 = 25,
> + MX8MQ_IOMUXC_ENET_MDC = 26,
> + MX8MQ_IOMUXC_ENET_MDIO = 27,
> + MX8MQ_IOMUXC_ENET_TD3 = 28,
> + MX8MQ_IOMUXC_ENET_TD2 = 29,
> + MX8MQ_IOMUXC_ENET_TD1 = 30,
> + MX8MQ_IOMUXC_ENET_TD0 = 31,
> + MX8MQ_IOMUXC_ENET_TX_CTL = 32,
> + MX8MQ_IOMUXC_ENET_TXC = 33,
> + MX8MQ_IOMUXC_ENET_RX_CTL = 34,
> + MX8MQ_IOMUXC_ENET_RXC = 35,
> + MX8MQ_IOMUXC_ENET_RD0 = 36,
> + MX8MQ_IOMUXC_ENET_RD1 = 37,
> + MX8MQ_IOMUXC_ENET_RD2 = 38,
> + MX8MQ_IOMUXC_ENET_RD3 = 39,
> + MX8MQ_IOMUXC_SD1_CLK = 40,
> + MX8MQ_IOMUXC_SD1_CMD =
RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks
Ping
> -Original Message-
> From: A.s. Dong
> Sent: Friday, May 25, 2018 6:37 PM
> To: linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; dl-
> linux-imx ; A.s. Dong
> Subject: [PATCH V3 0/4] clk: new APIs to handle all available clocks
>
> This patch series is a continue of discussion from here,
> https://patchwork.kernel.org/patch/9986293/
> that some users may want to handle all available clocks from device tree
> without need to know the detailed clock information likes clock numbers and
> names. This is useful in writing some generic drivers to handle clock part.
>
> Note:
> This patch series is tested on MX6Q SDB cpufreq driver with a minor change
> to switch to use clk_bulk_get_all.
> But patch 4 only test compiling. Hopefully someone could help test the
> function.
>
> v2->v3:
> * address all comments from Stephen
> * fix build warnings on other architectures.
> v1->v2:
> * add clk_bulk_{get|put}_all() which only supports DT platform currently
> * remove _all variants and the wrapper struct clk_bulk
> * make of_clk_bulk_get and of_clk_bulk_get_all private until someone
>proves they need it because they don't have a struct device pointer.
>
> Dong Aisheng (4):
> clk: bulk: add of_clk_bulk_get()
> clk: add new APIs to operate on all available clocks
> clk: add managed version of clk_bulk_get_all
> video: simplefb: switch to use clk_bulk API to simplify clock
> operations
>
> drivers/clk/clk-bulk.c | 80
> ++
> drivers/clk/clk-devres.c | 24 +
> drivers/video/fbdev/simplefb.c | 66 +++---
> include/linux/clk.h| 65 +-
> 4 files changed, 180 insertions(+), 55 deletions(-)
>
> --
> 2.7.4
RE: [PATCH V2 3/4] clk: add managed version of clk_bulk_get_all
> -Original Message-
> From: kbuild test robot [mailto:l...@intel.com]
> Sent: Friday, March 23, 2018 2:49 PM
> To: A.s. Dong
> Cc: kbuild-...@01.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; hdego...@redhat.com;
> b.zolnier...@samsung.com; li...@armlinux.org.uk; linux-
> fb...@vger.kernel.org; dl-linux-imx ;
> sb...@kernel.org; A.s. Dong ; Stephen Boyd
>
> Subject: Re: [PATCH V2 3/4] clk: add managed version of clk_bulk_get_all
>
[...]
> All errors (new ones prefixed by >>):
>
>In file included from include/linux/cpufreq.h:14:0,
> from arch/powerpc/platforms/cell/cpufreq_spudemand.c:23:
>include/linux/clk.h:679:1: error: expected identifier or '(' before '{'
> token
> {
> ^
> >> include/linux/clk.h:677:32: error: 'devm_clk_bulk_get_all' declared
> >> 'static' but never defined [-Werror=unused-function]
> static inline int __must_check devm_clk_bulk_get_all(struct device *dev,
>^
>cc1: all warnings being treated as errors
>
> vim +677 include/linux/clk.h
>
>676
> > 677static inline int __must_check devm_clk_bulk_get_all(struct
> device
> *dev,
>678 struct
> clk_bulk_data **clks);
Thanks for the reporting.
Caused by the extra unneeded ';' at the end of the line.
Will fix.
Regards
Dong Aisheng
> > 679{
>680
>681return 0;
>682}
>683
>
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.01.org%2Fpipermail%2Fkbuild-
> all&data=02%7C01%7Caisheng.dong%40nxp.com%7Ce9e35f96c61a4c46d1790
> 8d5908a4d46%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6365738
> 46071200287&sdata=yIWEjcpE2tyJP%2BmsMPqn%2F83TCsxw64J%2Ba5ue73
> qGnN0%3D&reserved=0 Intel Corporation
RE: [PATCH V2 2/4] clk: add new APIs to operate on all available clocks
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Saturday, March 24, 2018 12:57 AM
> To: A.s. Dong ; linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; hdego...@redhat.com;
> b.zolnier...@samsung.com; li...@armlinux.org.uk; linux-
> fb...@vger.kernel.org; dl-linux-imx ; A.s. Dong
> ; Stephen Boyd ;
> Masahiro Yamada
> Subject: Re: [PATCH V2 2/4] clk: add new APIs to operate on all available
> clocks
>
> Quoting Dong Aisheng (2018-03-20 20:19:49)
> > @@ -50,6 +52,38 @@ static int __must_check of_clk_bulk_get(struct
> device_node *np, int num_clks,
> > return ret;
> > }
> > EXPORT_SYMBOL(of_clk_bulk_get);
> > +
> > +static int __must_check of_clk_bulk_get_all(struct device_node *np,
> > + struct clk_bulk_data
> > +**clks) {
> > + struct clk_bulk_data *clk_bulk;
> > + int num_clks;
> > + int ret;
> > +
> > + num_clks = of_clk_get_parent_count(np);
> > + if (!num_clks)
> > + return 0;
> > +
> > + clk_bulk = kcalloc(num_clks, sizeof(*clk_bulk), GFP_KERNEL);
>
> Can be kmalloc_array? of_clk_bulk_get() already clears things out
> appropriately.
Yes, indeed. Will use kmalloc_array instead.
>
> > + if (!clk_bulk)
> > + return -ENOMEM;
> > +
> > + ret = of_clk_bulk_get(np, num_clks, clk_bulk);
> > + if (ret) {
> > + kfree(clk_bulk);
> > + return ret;
> > + }
> > +
> > + *clks = clk_bulk;
> > +
> > + return num_clks;
> > +}
> > +#else
> > +static int __must_check of_clk_bulk_get_all(struct device_node *np,
> > + struct clk_bulk_data
> > +**clks) {
> > + return -ENOENT;
> > +}
> > #endif
>
> This else can probably be dropped too.
>
Right.
> >
> > void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) @@ -90,6
> > +124,29 @@ int __must_check clk_bulk_get(struct device *dev, int
> > num_clks, } EXPORT_SYMBOL(clk_bulk_get);
> >
> > +void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) {
> > + if (IS_ERR_OR_NULL(clks))
> > + return;
> > +
> > + clk_bulk_put(num_clks, clks);
> > +
> > + kfree(clks);
> > +}
> > +EXPORT_SYMBOL(clk_bulk_put_all);
> > +
> > +int __must_check clk_bulk_get_all(struct device *dev,
> > + struct clk_bulk_data **clks) {
> > + struct device_node *np = dev_of_node(dev);
> > +
> > + if (!np)
> > + return 0;
> > +
> > + return of_clk_bulk_get_all(np, clks); }
> > +EXPORT_SYMBOL(clk_bulk_get_all);
>
> Looks better!
Thanks
Regards
Dong Aisheng
RE: [PATCH V2 1/4] clk: bulk: add of_clk_bulk_get()
Hi Stephen,
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Saturday, March 24, 2018 12:53 AM
> To: A.s. Dong ; linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; hdego...@redhat.com;
> b.zolnier...@samsung.com; li...@armlinux.org.uk; linux-
> fb...@vger.kernel.org; dl-linux-imx ; A.s. Dong
> ; Stephen Boyd ; Russell
> King
> Subject: Re: [PATCH V2 1/4] clk: bulk: add of_clk_bulk_get()
>
> Quoting Dong Aisheng (2018-03-20 20:19:48)
> > diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c index
> > 4c10456..4b357b2 100644
> > --- a/drivers/clk/clk-bulk.c
> > +++ b/drivers/clk/clk-bulk.c
> > @@ -19,6 +19,38 @@
> > #include
> > #include
> > #include
> > +#include
> > +
> > +#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
>
> Do we need these defines? of_clk_get() is a stub function when these
> configs are false.
>
You're right. Will drop it.
> > +static int __must_check of_clk_bulk_get(struct device_node *np, int
> num_clks,
> > + struct clk_bulk_data *clks) {
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < num_clks; i++)
> > + clks[i].clk = NULL;
> > +
> > + for (i = 0; i < num_clks; i++) {
> > + clks[i].clk = of_clk_get(np, i);
> > + if (IS_ERR(clks[i].clk)) {
> > + ret = PTR_ERR(clks[i].clk);
> > + pr_err("%pOF: Failed to get clk index: %d ret:
> > %d\n",
> > + np, i, ret);
> > + clks[i].clk = NULL;
> > + goto err;
> > + }
> > + }
> > +
> > + return 0;
> > +
> > +err:
> > + clk_bulk_put(i, clks);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL(of_clk_bulk_get);
>
> It's static, so don't export it.
Got it.
Sorry for such mistake.
Will fix and sent V3.
Regards
Dong Aisheng
RE: [PATCH] clocksource: imx-tpm: correct -ETIME return condition check
> -Original Message- > From: Anson Huang > Sent: Thursday, April 19, 2018 2:05 PM > To: daniel.lezc...@linaro.org; t...@linutronix.de; linux- > ker...@vger.kernel.org > Cc: dl-linux-imx > Subject: [PATCH] clocksource: imx-tpm: correct -ETIME return condition > check > > The additional brakets added to tpm_set_next_event's return value > computation causes (int) forced type conversion NOT taking effect, and the > incorrect value return will cause various system timer issue, like RCU stall > etc.. > > This patch removes the additional brakets to make sure > tpm_set_next_event always returns correct value. > > Signed-off-by: Anson Huang It's my mistake. Thanks for spotting it out. Acked-by: Dong Aisheng Regards Dong Aisheng > --- > resend, since I got failure message of sending mail to linux- > ker...@vger.kernel.org. > drivers/clocksource/timer-imx-tpm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer- > imx-tpm.c > index 05d97a6..6c83184 100644 > --- a/drivers/clocksource/timer-imx-tpm.c > +++ b/drivers/clocksource/timer-imx-tpm.c > @@ -114,7 +114,7 @@ static int tpm_set_next_event(unsigned long delta, >* of writing CNT registers which may cause the min_delta event got >* missed, so we need add a ETIME check here in case it happened. >*/ > - return (int)((next - now) <= 0) ? -ETIME : 0; > + return (int)(next - now) <= 0 ? -ETIME : 0; > } > > static int tpm_set_state_oneshot(struct clock_event_device *evt) > -- > 2.7.4
RE: [RFC PATCH 1/2] clk: add new APIs to operate on all available clocks
> -Original Message-
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Tuesday, March 20, 2018 12:22 AM
> To: A.s. Dong ; linux-...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; dl-
> linux-imx ; aisheng.d...@codeaurora.org; linux-
> fb...@vger.kernel.org; yamada.masah...@socionext.com;
> sb...@codeaurora.org; hdego...@redhat.com;
> b.zolnier...@samsung.com; A.s. Dong
> Subject: Re: [RFC PATCH 1/2] clk: add new APIs to operate on all available
> clocks
>
> Quoting Dong Aisheng (2018-01-23 04:50:40)
> > This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs to
> > users who just want to handle all available clocks from device tree
> > without need to know the detailed clock information likes clock
> > numbers and names. This is useful in writing some generic drivers to
> > handle clock part.
> >
> > Cc: Stephen Boyd
> > Cc: Masahiro Yamada
> > Signed-off-by: Dong Aisheng
> >
> > ---
> > A few question may need discuss:
> > 1) This patch is written based on of_clk_bulk_get.
> > [V4,1/1] clk: bulk: add of_clk_bulk_get()
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> >
> chwork.kernel.org%2Fpatch%2F9971527%2F&data=02%7C01%7Caisheng.don
> g%40n
> >
> xp.com%7C449209dd3e19491afb9908d58db5966d%7C686ea1d3bc2b4c6fa92c
> d99c5c
> >
> 301635%7C0%7C0%7C636570733411754127&sdata=4m5emXOR%2Bui3Mqw
> MbAJQDQxJcE
> > %2BxLcB51hEi2q3V2O8%3D&reserved=0 Stepen once said we may not
> need it,
> > but i guess as we already have clk_bulk_get, there may be guys who
> > want of_clk_bulk_get as well if they need specify the clock count
> > information, becaues of_clk_bulk_get_all will not check the count.
> > And of_clk_bulk_get is also helpful when implementing
> > of_clk_bulk_get_all.
>
> Hmm ok. It's ok to implement it on top of of_clk_bulk_get I suppose, but
> maybe that API can be kept private until someone can prove they need it
> because they don't have a struct device pointer. Can you pick that patch from
> the list and resend in the series?
>
Of course. I will do that.
> >
> > 2) It only implements the DT type clk_get_all as i see Stephen said we
> > probably may not need to implement non-dt type as there're still no
> > users.
>
> Good.
>
> >
> > If we do want to implement non-dt type as well, we could revise the
> > patch to add it too.
> > ---
> > drivers/clk/clk-bulk.c | 64
> ++
> > include/linux/clk.h| 61
> ++-
> > 2 files changed, 124 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c index
> > 1c1a79d..bac2aae 100644
> > --- a/drivers/clk/clk-bulk.c
> > +++ b/drivers/clk/clk-bulk.c
> > @@ -17,9 +17,11 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > +#include
> >
> > #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) int
> > __must_check of_clk_bulk_get(struct device_node *np, int num_clks, @@
> > -50,6 +52,45 @@ int __must_check of_clk_bulk_get(struct device_node
> *np, int num_clks,
> > return ret;
> > }
> > EXPORT_SYMBOL(of_clk_bulk_get);
> > +
> > +struct clk_bulk __must_check *of_clk_bulk_get_all(struct device_node
> > +*np) {
> > + struct clk_bulk *clk_bulk;
> > + int num_clks;
> > + int ret;
> > +
> > + num_clks = of_clk_get_parent_count(np);
> > + if (!num_clks)
> > + return NULL;
> > +
> > + clk_bulk = kzalloc(sizeof(*clk_bulk) +
> > + num_clks * sizeof(struct clk_bulk_data),
> > + GFP_KERNEL);
> > + if (!clk_bulk)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + clk_bulk->num_clks = num_clks;
> > + ret = of_clk_bulk_get(np, clk_bulk->num_clks, clk_bulk->clks);
> > + if (ret) {
> > + kfree(clk_bulk);
> > + return ERR_PTR(ret);
> > + }
>
> Has this been tested? clk_bulk->clks probably points to junk?
>
You're right. Will fix in a formal patch.
> > +
> > + return clk_bulk;
> > +}
> > +EXPORT_SYMBOL(of_clk_bulk_get_all);
> > +
> > +void of_clk_bulk_put_all(struct clk_bulk *clk_bulk) {
> > + if (IS_ERR_OR_NULL(clk_bulk))
> > +
RE: [PATCH RESEND V3 0/9] clk: add imx7ulp clk support
Hi Shawn & Stephen, Would you help review this series? It's pending for a long time. Regards Dong Aisheng > -Original Message- > From: Dong Aisheng [mailto:aisheng.d...@nxp.com] > Sent: Tuesday, February 13, 2018 9:28 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@codeaurora.org; mturque...@baylibre.com; shawn...@kernel.org; > Anson Huang ; Jacky Bai ; A.s. > Dong > Subject: [PATCH RESEND V3 0/9] clk: add imx7ulp clk support > > This is a resend patch series. > See the original one from here: > [PATCH V3 00/10] clk: add imx7ulp clk support > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flk > ml.org%2Flkml%2F2018%2F1%2F19%2F351&data=02%7C01%7Caisheng.dong > %40nxp.com%7C2158b9d83b9442c6fa8208d572e5b5f5%7C686ea1d3bc2b4c6f > a92cd99c5c301635%7C0%7C0%7C636541253280073434&sdata=VQ7%2Fx08X5 > 9AQ8SoYna%2Bw4HnErty3vR5Zwh2dp7FzJqU%3D&reserved=0 > No function changes but remove the last one which is used for the test. > Rebased against clk-next branch. > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > Core Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such > as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock > (FIRCLK), clock sources and clock management are separated and contained > within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain will > be handled by M4 seperately. > > Change Log: > v2->v3: > * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy >Others no changes. > > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for possible >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for >the left normal peripheral clocks registered by a platform driver. > > > Dong Aisheng (9): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 62 ++ > drivers/clk/clk-divider.c | 152 ++ > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c| 90 > drivers/clk/imx/clk-fixup-mux.c| 2 +- > drivers/clk/imx/clk-imx7ulp.c | 232 > + > drivers/clk/imx/clk-pfdv2.c| 207 ++ > drivers/clk/imx/clk-pllv4.c| 188 + > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 ++ > include/linux/clk-provider.h | 17 ++ > 14 files changed, 1180 insertions(+), 10 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 > include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4
RE: [PATCH] ARM: dts: imx7d-sdb: add gpio key support
> -Original Message-
> From: Anson Huang [mailto:anson.hu...@nxp.com]
> Sent: Friday, March 16, 2018 4:55 PM
> To: shawn...@kernel.org; ker...@pengutronix.de; Fabio Estevam
> ; robh...@kernel.org; mark.rutl...@arm.com;
> li...@armlinux.org.uk
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] ARM: dts: imx7d-sdb: add gpio key support
>
> Add support for imx7d-sdb board's gpio keys:
>
> S1(FUNC1): KEY_VOLUMEUP
> S3(FUNC2): KEY_VOLUMEDOWN
>
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> Signed-off-by: Anson Huang
> ---
> arch/arm/boot/dts/imx7d-sdb.dts | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-
> sdb.dts index 7f241af..e47b5b2 100644
> --- a/arch/arm/boot/dts/imx7d-sdb.dts
> +++ b/arch/arm/boot/dts/imx7d-sdb.dts
> @@ -52,6 +52,24 @@
> reg = <0x8000 0x8000>;
> };
>
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + volume-up {
> + label = "Volume Up";
> + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
> + linux,code = ;
> + };
> +
> + volume-down {
> + label = "Volume Down";
> + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
> + linux,code = ;
> + };
> + };
> +
> spi4 {
> compatible = "spi-gpio";
> pinctrl-names = "default";
> @@ -519,6 +537,12 @@
> >;
> };
>
> + pinctrl_gpio_keys: gpio_keysgrp {
> + fsl,pins = <
> + MX7D_PAD_SD2_RESET_B__GPIO5_IO11
> 0x59
> + MX7D_PAD_SD2_WP__GPIO5_IO10
> 0x59
> + >;
> + };
>
> pinctrl_hog: hoggrp {
> fsl,pins = <
> --
> 2.7.4
RE: [PATCH V4 2/2] thermal: imx: add i.MX7 thermal sensor support
> -Original Message- > From: Anson Huang [mailto:anson.hu...@nxp.com] > Sent: Saturday, February 24, 2018 4:03 PM > To: rui.zh...@intel.com; edubez...@gmail.com; robh...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; ker...@pengutronix.de; > Fabio Estevam ; li...@armlinux.org.uk > Cc: dl-linux-imx ; linux...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > ker...@lists.infradead.org > Subject: [PATCH V4 2/2] thermal: imx: add i.MX7 thermal sensor support > > This patch adds i.MX7 thermal sensor support, most of the i.MX7 thermal > sensor functions are same with > i.MX6 except the registers offset/layout, so we move those registers > offset/layout definitions to soc data structure. > > i.MX7 uses single calibration data @25C, the calibration data is located at > OCOTP offset 0x4F0, bit[17:9], the formula is as below: > > Tmeas = (Nmeas - n1) + 25; n1 is the fuse value for 25C. > > Signed-off-by: Anson Huang > Signed-off-by: Bai Ping Acked-by: Dong Aisheng Regards Dong Aisheng
RE: [PATCH] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero
> -Original Message-
> From: Colin King [mailto:colin.k...@canonical.com]
> Sent: Monday, February 26, 2018 8:04 PM
> To: A.s. Dong ; Fabio Estevam
> ; Shawn Guo ; Stefan
> Agner ; inus Walleij ; linux-
> g...@vger.kernel.org
> Cc: kernel-janit...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] pinctrl: imx: fix unsigned check if nfuncs with less than or
> equal zero
>
> From: Colin Ian King
>
> The unsigned integer nfuncs is being error checked with a value less or equal
> to zero; this is always false if of_get_child_count returns a -ve for an error
> condition since nfuncs is not signed. Fix this by making variables nfuncs and
> i
> signed integers.
>
> Detected with Coccinelle:
> drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
> expression compared with zero: nfuncs <= 0
>
> Fixes: ae75ff814538 ("pinctrl: pinctrl-imx: add imx pinctrl core driver")
> Signed-off-by: Colin Ian King
> ---
> drivers/pinctrl/freescale/pinctrl-imx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
> b/drivers/pinctrl/freescale/pinctrl-imx.c
> index 24aaddd760a0..1e8ca83352d0 100644
> --- a/drivers/pinctrl/freescale/pinctrl-imx.c
> +++ b/drivers/pinctrl/freescale/pinctrl-imx.c
> @@ -605,8 +605,8 @@ static int imx_pinctrl_probe_dt(struct
> platform_device *pdev,
> struct device_node *np = pdev->dev.of_node;
> struct device_node *child;
> struct pinctrl_dev *pctl = ipctl->pctl;
> - u32 nfuncs = 0;
> - u32 i = 0;
> + int nfuncs = 0;
> + int i = 0;
> bool flat_funcs;
>
I saw 'i', later used, is converted to u32 unconditionally. (GCC did not
complain)
e.g.
radix_tree_insert
imx_pinctrl_parse_functions
And of_get_child_count seems can't return a minor value.
So does something like below look better?
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c
b/drivers/pinctrl/freescale/pinctrl-imx.c
index c976ffe..4259209 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -612,7 +612,7 @@ static int imx_pinctrl_probe_dt(struct platform_device
*pdev,
nfuncs = 1;
} else {
nfuncs = of_get_child_count(np);
- if (nfuncs <= 0) {
+ if (nfuncs == 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
Regards
Dong Aisheng
> if (!np)
> --
> 2.15.1
RE: [PATCH v2] MAINTAINERS: add Freescale pin controllers
Hi Stefan, > -Original Message- > From: Stefan Agner [mailto:ste...@agner.ch] > Sent: Monday, February 12, 2018 11:06 PM > To: linus.wall...@linaro.org; A.s. Dong ; Fabio > Estevam ; shawn...@kernel.org; > ker...@pengutronix.de > Cc: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > Stefan Agner > Subject: [PATCH v2] MAINTAINERS: add Freescale pin controllers > > Add Dong Aisheng, Fabio Estevam, Shawn Guo and myself as maintainer and > the Pengutronix kernel team as reviewer. > > Signed-off-by: Stefan Agner > Reviewed-by: Fabio Estevam Thanks for sending this. Besides Joe's comments, I'm fine with it. So: Acked-by: Dong Aisheng Regards Dong Aisheng > --- > MAINTAINERS | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 82ad0eabce4f..df60ca7c3355 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10768,6 +10768,17 @@ L: linux-g...@vger.kernel.org > S: Supported > F: drivers/pinctrl/pinctrl-at91-pio4.* > > +PIN CONTROLLER - FREESCALE > +M: Dong Aisheng > +M: Fabio Estevam > +M: Shawn Guo > +M: Stefan Agner > +R: Pengutronix Kernel Team > +L: linux-g...@vger.kernel.org > +S: Maintained > +F: drivers/pinctrl/freescale/* > +F: Documentation/devicetree/bindings/pinctrl/fsl,* > + > PIN CONTROLLER - INTEL > M: Mika Westerberg > M: Heikki Krogerus > -- > 2.16.1
RE: [PATCH V3 10/10] add imx7ulp support
Hi Fabio,
This patch (Patch 10) is used for test and was sent out by accidently, not
formal one.
I also explained in another email. Guess you may not see it.
Really sorry for the inconvenience.
Regards
Dong Aisheng
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Thursday, January 25, 2018 9:22 PM
> To: A.s. Dong
> Cc: linux-clk ; Jacky Bai ;
> Anson Huang ; Michael Turquette
> ; Stephen Boyd ; linux-
> kernel ; dl-linux-imx ;
> Fabio Estevam ; Shawn Guo
> ; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE
> Subject: Re: [PATCH V3 10/10] add imx7ulp support
>
> On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng
> wrote:
>
> Please always add a commit log.
>
> > Signed-off-by: Dong Aisheng
>
> > ---
> > arch/arm/boot/dts/Makefile | 2 +
> > arch/arm/boot/dts/imx7ulp-evk.dts| 87 +++
> > arch/arm/boot/dts/imx7ulp.dtsi | 202
> +++
> > arch/arm/configs/imx_v6_v7_defconfig | 16 ++-
> > arch/arm/mach-imx/Kconfig| 9 ++
> > arch/arm/mach-imx/Makefile | 1 +
> > arch/arm/mach-imx/common.h | 1 +
> > arch/arm/mach-imx/cpu.c | 3 +
> > arch/arm/mach-imx/mach-imx7ulp.c | 37 +++
> > arch/arm/mach-imx/mxc.h | 1 +
> > arch/arm/mach-imx/pm-imx7ulp.c | 32 ++
> > 11 files changed, 381 insertions(+), 10 deletions(-) create mode
> > 100644 arch/arm/boot/dts/imx7ulp-evk.dts create mode 100644
> > arch/arm/boot/dts/imx7ulp.dtsi create mode 100644
> > arch/arm/mach-imx/mach-imx7ulp.c create mode 100644
> > arch/arm/mach-imx/pm-imx7ulp.c
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index d0381e9..3257e71 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> > imx7d-sdb-sht11.dtb \
> > imx7s-colibri-eval-v3.dtb \
> > imx7s-warp.dtb
> > +dtb-$(CONFIG_SOC_IMX7ULP) += \
> > + imx7ulp-evk.dtb
> > dtb-$(CONFIG_SOC_LS1021A) += \
> > ls1021a-qds.dtb \
> > ls1021a-twr.dtb
> > diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts
> > b/arch/arm/boot/dts/imx7ulp-evk.dts
> > new file mode 100644
> > index 000..cc4e6ef
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp-evk.dts
> > @@ -0,0 +1,87 @@
> > +/*
> > + * Copyright 2017 NXP
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
>
> Please use SPDX identifier.
>
>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx7ulp.dtsi"
> > +
> > +/ {
> > + model = "NXP i.MX7ULP EVK";
> > + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
>
> Please remove the '"Generic DT based system" entry.
>
>
> > +
> > + chosen {
> > + bootargs = "console=ttyLP0,115200
> earlycon=lpuart32,0x402D0010,115200";
> > + stdout-path = &lpuart4;
>
> Better remove bootargs.
>
>
> > + };
> > +
> > + memory {
>
> memory@6000 , otherwise building with W=1 will give you warning.
>
> Please make sure that you don't get dtc warnings with W=1.
>
> > + device_type = "memory";
> > + reg = <0x6000 0x4000>;
> > + };
> > +};
> > +
> > +&lpuart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_lpuart4>;
> > + status = "okay";
> > +};
> > +
> > +&usdhc0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <>;
> > + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>;
> > +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>;
>
> Just remove the line instead of commenting it.
>
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 000..05410ba
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,202 @@
> > +/*
> > + * Copyright NXP
>
> No year
RE: [PATCH V3 10/10] add imx7ulp support
Hi Stephen, > -Original Message- > From: Dong Aisheng [mailto:aisheng.d...@nxp.com] > Sent: Friday, January 19, 2018 9:11 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@codeaurora.org; mturque...@baylibre.com; shawn...@kernel.org; > Anson Huang ; Jacky Bai ; dl- > linux-imx ; Fabio Estevam ; > A.s. Dong > Subject: [PATCH V3 10/10] add imx7ulp support > > Signed-off-by: Dong Aisheng > I'm sorry that this one is for test and was sent out by accidently and should not belong to the clk series. So you can ignore this one. Others, patch 1~9, are fine. Regards Dong Aisheng
RE: [PATCH v2 5/5] pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
Hi Linus, > -Original Message- > From: Linus Walleij [mailto:linus.wall...@linaro.org] > Sent: Tuesday, January 09, 2018 10:08 PM > > Stefan, would you consider making a patch adding you, Dong Aisheng and > Shawn Guo as maintainers in MAINTAINERS for > drivers/pinctrl/freescale/* > Documentation/devicetree/bindings/pinctrl/fsl,* > ? I'm okay to take that MAINTAINER work. Thanks for the nomination. Regards Dong Aisheng
RE: [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
> -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: Wednesday, December 27, 2017 10:32 AM > To: Peng Fan > Cc: A.s. Dong ; linux-kernel@vger.kernel.org; Russell > King ; Fabio Estevam ; > Sascha Hauer ; van.free...@gmail.com; linux-arm- > ker...@lists.infradead.org > Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use > outer_disable/resume > > On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote: > > Use outer_disable/resume for suspend/resume. > > With the two APIs used, code could be simplified and easy to extend to > > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel > > runs in non-secure world. > > > > Signed-off-by: Peng Fan > > Cc: Shawn Guo > > Cc: Sascha Hauer > > Cc: Fabio Estevam > > Cc: Russell King > > Cc: Dong Aisheng > > @Aisheng, can you please give it a test? > Yes, of course. Regards Dong Aisheng > Shawn
RE: [PATCH 1/7] PM / OPP: Add platform specific set_clk function
> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Thursday, September 21, 2017 4:31 AM
> To: Dong Aisheng
> Cc: A.s. Dong; linux...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; sb...@codeaurora.org;
> vire...@kernel.org; n...@ti.com; r...@rjwysocki.net; shawn...@kernel.org;
> Anson Huang; Jacky Bai
> Subject: Re: [PATCH 1/7] PM / OPP: Add platform specific set_clk function
>
> On 20-09-17, 15:03, Dong Aisheng wrote:
> > I've been thinking of that before.
> > Actually IMX already does some similar thing for MX5 (no for MX6).
> > See: clk_cpu_set_rate() in drivers/clk/imx/clk-cpu.c.
> >
> > After some diggings, it seems MX7ULP is a bit more complicated than
> > before mainly due to two reasons:
> > 1) It requires to switch to different CPU mode accordingly when
> > setting clocks rate. That means we need handle this in clock driver as
> > well which looks not quite suitable although we could do if really want.
> >
> > 2) It uses different clocks for different CPU mode (RUN 416M or HSRUN
> > 528M), and those clocks have some dependency.
> > e.g. when setting HSRUN clock, we need change RUN clock parent to make
> > sure the SPLL_PFD is got disabled before changing rate, as both CPU
> > mode using the same parent SPLL_PFD clock. Doing this in clock driver
> > also make things a bit more complicated.
> >
> > The whole follow would be something like below:
> > static int imx7ulp_set_clk(struct device *dev, struct clk *clk,
> >unsigned long old_freq, unsigned long
> > new_freq) {
> > u32 val;
> >
> > /*
> > * Before changing the ARM core PLL, change the ARM clock soure
> > * to FIRC first.
> > */
> > if (new_freq >= HSRUN_FREQ) {
> > clk_set_parent(clks[RUN_SCS_SEL].clk, clks[FIRC].clk);
> >
> > /* switch to HSRUN mode */
> > val = readl_relaxed(smc_base + SMC_PMCTRL);
> > val |= (0x3 << 8);
> > writel_relaxed(val, smc_base + SMC_PMCTRL);
> >
> > /* change the clock rate in HSRUN */
> > clk_set_rate(clks[SPLL_PFD0].clk, new_freq);
> > clk_set_parent(clks[HSRUN_SCS_SEL].clk,
> clks[SPLL_SEL].clk);
> > } else {
> > /* change the HSRUN clock to firc */
> > clk_set_parent(clks[HSRUN_SCS_SEL].clk,
> > clks[FIRC].clk);
> >
> > /* switch to RUN mode */
> > val = readl_relaxed(smc_base + SMC_PMCTRL);
> > val &= ~(0x3 << 8);
> > writel_relaxed(val, smc_base + SMC_PMCTRL);
> >
> > clk_set_rate(clks[SPLL_PFD0].clk, new_freq);
> > clk_set_parent(clks[RUN_SCS_SEL].clk,
> clks[SPLL_SEL].clk);
> > }
> >
> > return 0;
> > }
>
> Right and we have the same thing in the cpufreq driver now. It will stay
> at some place and we need to find the best one, keeping in mind that we
> may or may not want to solve this problem in a generic way.
>
> > That's why i thought if we can make OPP core provide a way to handle
> > such complicated things in platform specific cpufreq driver.
> >
> > How would you suggest for this issue?
>
> I wouldn't add an API into the OPP framework if I were you. There is just
> too much code to add to the core to handle such platform specific stuff,
> which you are anyway going to keep somewhere as it is. IMHO, keeping that
> in the clock driver is a better thing to do than this.
>
Okay, I will give a try in CLK driver.
Thanks for the suggestion.
Regards
Dong Aisheng
> --
> viresh
RE: [PATCH] cpufreq: imx6q: Fix imx6sx low frequency support
> -Original Message-
> From: Leonard Crestez [mailto:leonard.cres...@nxp.com]
> Sent: Monday, August 28, 2017 7:05 PM
> To: Shawn Guo; Viresh Kumar; Rafael J. Wysocki
> Cc: Anson Huang; Fabio Estevam; A.s. Dong; Lucas Stach; Jacky Bai;
> ker...@pengutronix.de; linux...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] cpufreq: imx6q: Fix imx6sx low frequency support
>
> This patch contains the minimal changes required to support imx6sx OPP of
> 198 Mhz. Without this patch cpufreq still reports success but the
> frequency is not changed, the "arm" clock will still be at 39600 in
> clk_summary.
>
> In order to do this PLL1 needs to be still kept enabled while changing the
> ARM clock. This is a hardware requirement: when ARM_PODF is changed in CCM
> we need to check the busy bit of CCM_CDHIPR bit 16 arm_podf_busy, and this
> bit is sync with PLL1 clock, so if PLL1 NOT enabled, this bit will never
> get clear.
>
> Keep pll1_sys explicitly enabled until after the rate is change to deal
> with this. Otherwise from the clk framework perspective pll1_sys is unused
> and gets turned off.
>
Seems like a clever method to me.
So:
Acked-by: Dong Aisheng
Regards
Dong Aisheng
> Signed-off-by: Leonard Crestez
> ---
> Changes since v1:
> - Link: https://lkml.org/lkml/2017/7/19/302
> - Only keep pll1_sys enabled until after ARM rate is changed.
> - Incorporate more elaborate explanation from Anson
> - Do not add new clocks or bypass PLL1. Just let it get disabled.
>
> drivers/cpufreq/imx6q-cpufreq.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-
> cpufreq.c index b6edd3c..14466a9 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -47,6 +47,7 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> struct dev_pm_opp *opp;
> unsigned long freq_hz, volt, volt_old;
> unsigned int old_freq, new_freq;
> + bool pll1_sys_temp_enabled = false;
> int ret;
>
> new_freq = freq_table[index].frequency; @@ -124,6 +125,10 @@ static
> int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
> clk_set_rate(pll1_sys_clk, new_freq * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> + } else {
> + /* pll1_sys needs to be enabled for divider rate change
> to work. */
> + pll1_sys_temp_enabled = true;
> + clk_prepare_enable(pll1_sys_clk);
> }
> }
>
> @@ -135,6 +140,10 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> return ret;
> }
>
> + /* PLL1 is only needed until after ARM-PODF is set. */
> + if (pll1_sys_temp_enabled)
> + clk_disable_unprepare(pll1_sys_clk);
> +
> /* scaling down? scale voltage after frequency */
> if (new_freq < old_freq) {
> ret = regulator_set_voltage_tol(arm_reg, volt, 0);
> --
> 2.7.4
RE: [PATCH V2 00/10] clk: add imx7ulp clk support
> -Original Message- > From: A.s. Dong > Sent: Wednesday, July 26, 2017 10:57 AM > To: A.s. Dong; linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@codeaurora.org; mturque...@baylibre.com; donga...@gmail.com; > shawn...@kernel.org; Anson Huang; Jacky Bai > Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support > > Ping... > Gently ping again... Hi Stephen, This has been more there without comments for more than one month. Would you help review when you're available later? Regards Dong Aisheng > > -Original Message- > > From: Dong Aisheng [mailto:aisheng.d...@nxp.com] > > Sent: Thursday, July 13, 2017 7:47 PM > > To: linux-...@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org; > > linux-arm-ker...@lists.infradead.org; > > sb...@codeaurora.org; mturque...@baylibre.com; A.s. Dong; > > donga...@gmail.com; shawn...@kernel.org; Anson Huang; Jacky Bai > > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support > > > > This patch series intends to add imx7ulp clk support. > > > > i.MX7ULP Clock functions are under joint control of the System Clock > > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and > > Core Mode Controller (CMC)1 blocks > > > > The clocking scheme provides clear separation between M4 domain and A7 > > domain. Except for a few clock sources shared between two domains, > > such as the System Oscillator clock, the Slow IRC (SIRC), and and the > > Fast IRC clock (FIRCLK), clock sources and clock management are > > separated and contained within each domain. > > > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > > > Note: this series only adds A7 clock domain support as M4 clock domain > > will be handled by M4 seperately. > > > > Change Log: > > v1->v2: > > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > > * use clk_hw apis to register clocks > > * use of_clk_add_hw_provider > > * split the clocks register process into two parts: early part for > > possible > >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later > > part for > >the left normal peripheral clocks registered by a platform driver. > > > > Dong Aisheng (10): > > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > > clk: reparent orphans after critical clocks enabled > > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > > clk: imx: add pllv4 support > > clk: imx: add pfdv2 support > > clk: imx: add composite clk support > > dt-bindings: clock: add imx7ulp clock binding doc > > clk: imx: make mux parent strings const > > clk: imx: implement new clk_hw based APIs > > clk: imx: add imx7ulp clk driver > > > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 62 ++ > > drivers/clk/clk-divider.c | 100 - > > drivers/clk/clk-fractional-divider.c | 10 + > > drivers/clk/clk.c | 39 ++-- > > drivers/clk/imx/Makefile | 6 +- > > drivers/clk/imx/clk-busy.c | 2 +- > > drivers/clk/imx/clk-composite.c| 90 > > drivers/clk/imx/clk-fixup-mux.c| 2 +- > > drivers/clk/imx/clk-imx7ulp.c | 245 > > + > > drivers/clk/imx/clk-pfdv2.c| 207 > > + > > drivers/clk/imx/clk-pllv4.c| 188 > > > drivers/clk/imx/clk.c | 22 ++ > > drivers/clk/imx/clk.h | 92 +++- > > include/dt-bindings/clock/imx7ulp-clock.h | 108 + > > include/linux/clk-provider.h | 17 ++ > > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode > > 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > create mode 100644 drivers/clk/imx/clk-composite.c create mode > > 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 > > drivers/clk/imx/clk- pfdv2.c create mode 100644 > > drivers/clk/imx/clk-pllv4.c create mode > > 100644 include/dt-bindings/clock/imx7ulp-clock.h > > > > -- > > 2.7.4
RE: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support
Hi Daniel,
> -Original Message-
> From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org]
> Sent: Monday, July 31, 2017 10:29 PM
> To: A.s. Dong; linux-kernel@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org; t...@linutronix.de;
> shawn...@kernel.org; Jacky Bai; Anson Huang; donga...@gmail.com;
> ker...@pengutronix.de; Arnd Bergmann
> Subject: Re: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support
>
> On 05/07/2017 04:35, Dong Aisheng wrote:
> > IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> > this patch only adds the timer support. PWM would be added later.
> >
> > The TPM counter, compare and capture registers are clocked by an
> > asynchronous clock that can remain enabled in low power modes.
> >
> > NOTE: We observed in a very small probability, the bus fabric
> > contention between GPU and A7 may results a few cycles delay of
> > writing CNT registers which may cause the min_delta event got missed,
> > so we need add a ETIME check here in case it happened.
> >
> > Cc: Daniel Lezcano
> > Cc: Arnd Bergmann
> > Cc: Thomas Gleixner
> > Cc: Shawn Guo
> > Cc: Anson Huang
> > Cc: Bai Ping
> > Signed-off-by: Dong Aisheng
> >
> > ---
> > ChangeLog:
> > v3->v4:
> > * also add ETIME explanation in function
> > v2->v3:
> > * address all comments from Daniel Lezcano
> > * add more explaination on ETIME check in commit message
> > v1->v2:
> > * change to readl/writel from __raw_readl/writel according to Arnd's
> >suggestion to avoid endian issue
> > * add help information in Kconfig
> > * add more error checking
> > ---
> > drivers/clocksource/Kconfig | 8 ++
> > drivers/clocksource/Makefile| 1 +
> > drivers/clocksource/timer-imx-tpm.c | 239
> >
> > 3 files changed, 248 insertions(+)
> > create mode 100644 drivers/clocksource/timer-imx-tpm.c
>
> [ ... ]
>
> > +static struct irqaction tpm_timer_irq = {
> > + .name = "i.MX7ULP TPM Timer",
> > + .flags = IRQF_TIMER | IRQF_IRQPOLL,
> > + .handler= tpm_timer_interrupt,
> > + .dev_id = &clockevent_tpm,
> > +};
> >
>
> Please remove the structure above and use request_irq instead of setup_irq
> below + return code checking.
>
Okay, will switch to it.
> > +static int __init tpm_clockevent_init(unsigned long rate, int irq) {
> > + setup_irq(irq, &tpm_timer_irq);
> > +
> > + clockevent_tpm.cpumask = cpumask_of(0);
> > + clockevent_tpm.irq = irq;
> > + clockevents_config_and_register(&clockevent_tpm,
> > + rate, 300, 0xfffe);
> > +
> > + return 0;
> > +}
> > +
> > +static int __init tpm_timer_init(struct device_node *np) {
>
> [ ... ]
>
> > + rate = clk_get_rate(per) >> 3;
>
> Why ?
>
Because TPM internally is configured to divide 8.
The full context is:
/* increase per cnt, div 8 by default */
writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
timer_base + TPM_SC);
/* set MOD register to maximum for free running mode */
writel(0x, timer_base + TPM_MOD);
rate = clk_get_rate(per) >> 3;
> > + tpm_clocksource_init(rate);
> > + tpm_clockevent_init(rate, irq);
>
> Check.
>
Currently non of them return error code, do I still need to check?
> > + return 0;
> > +
> > +err_per_clk_enable:
> > + clk_disable_unprepare(ipg);
> > +err_ipg_clk_enable:
>
> No need to add an extra label.
>
Okay, will remove one.
> > +err_clk_get:
> > + clk_put(per);
> > + clk_put(ipg);
> > +err_iomap:
> > + iounmap(timer_base);
> > + return ret;
> > +}
> > +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
>
> CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE.
>
Looks new, will change to it.
Thanks!
Regards
Dong Aisheng
> Thanks!
>
> -- Daniel
>
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-
> blog/> Blog
RE: [PATCH V2 00/10] clk: add imx7ulp clk support
Ping... > -Original Message- > From: Dong Aisheng [mailto:aisheng.d...@nxp.com] > Sent: Thursday, July 13, 2017 7:47 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@codeaurora.org; mturque...@baylibre.com; A.s. Dong; > donga...@gmail.com; shawn...@kernel.org; Anson Huang; Jacky Bai > Subject: [PATCH V2 00/10] clk: add imx7ulp clk support > > This patch series intends to add imx7ulp clk support. > > i.MX7ULP Clock functions are under joint control of the System Clock > Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core > Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain and A7 > domain. Except for a few clock sources shared between two domains, such as > the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC > clock (FIRCLK), clock sources and clock management are separated and > contained within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > Note: this series only adds A7 clock domain support as M4 clock domain > will be handled by M4 seperately. > > Change Log: > v1->v2: > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers > * use clk_hw apis to register clocks > * use of_clk_add_hw_provider > * split the clocks register process into two parts: early part for > possible >timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part > for >the left normal peripheral clocks registered by a platform driver. > > Dong Aisheng (10): > clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support > clk: reparent orphans after critical clocks enabled > clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support > clk: imx: add pllv4 support > clk: imx: add pfdv2 support > clk: imx: add composite clk support > dt-bindings: clock: add imx7ulp clock binding doc > clk: imx: make mux parent strings const > clk: imx: implement new clk_hw based APIs > clk: imx: add imx7ulp clk driver > > .../devicetree/bindings/clock/imx7ulp-clock.txt| 62 ++ > drivers/clk/clk-divider.c | 100 - > drivers/clk/clk-fractional-divider.c | 10 + > drivers/clk/clk.c | 39 ++-- > drivers/clk/imx/Makefile | 6 +- > drivers/clk/imx/clk-busy.c | 2 +- > drivers/clk/imx/clk-composite.c| 90 > drivers/clk/imx/clk-fixup-mux.c| 2 +- > drivers/clk/imx/clk-imx7ulp.c | 245 > + > drivers/clk/imx/clk-pfdv2.c| 207 > + > drivers/clk/imx/clk-pllv4.c| 188 > drivers/clk/imx/clk.c | 22 ++ > drivers/clk/imx/clk.h | 92 +++- > include/dt-bindings/clock/imx7ulp-clock.h | 108 + > include/linux/clk-provider.h | 17 ++ > 15 files changed, 1159 insertions(+), 31 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 > drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk- > pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode > 100644 include/dt-bindings/clock/imx7ulp-clock.h > > -- > 2.7.4
RE: [PATCH V4 0/2] timer: add imx tpm timer support
Gently Ping... It's been two weeks. > -Original Message- > From: Dong Aisheng [mailto:aisheng.d...@nxp.com] > Sent: Wednesday, July 05, 2017 10:35 AM > To: linux-kernel@vger.kernel.org > Cc: linux-arm-ker...@lists.infradead.org; daniel.lezc...@linaro.org; > t...@linutronix.de; shawn...@kernel.org; Jacky Bai; Anson Huang; > donga...@gmail.com; ker...@pengutronix.de; A.s. Dong > Subject: [PATCH V4 0/2] timer: add imx tpm timer support > > The Timer/PWM Module (TPM) supports input capture, output compare, and the > generation of PWM signals to control electric motor and power management > applications. The counter, compare and capture registers are clocked by an > asynchronous clock that can remain enabled in low power modes. TPM can > support global counter bus where one TPM drives the counter bus for the > others, provided bit width is the same. > > This patch only adds the timer support. PWM would be added later. > > ChangeLog: > v3->v4: > * also add ETIME explanation in function > v2->v3: > * address a few minor comments from Daniel Lezcano > * add more explaination on ETIME check in commit message > v1->v2: > * change to readl/writel from __raw_readl/writel according to Arnd's >suggestion to avoid endian issue > * add help information in Kconfig > * add more error checking > > Dong Aisheng (2): > dt-bindings: timer: add nxp tpm timer binding doc > timer: imx-tpm: add imx tpm timer support > > .../devicetree/bindings/timer/nxp,tpm-timer.txt| 28 +++ > drivers/clocksource/Kconfig| 8 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-imx-tpm.c| 239 > + > 4 files changed, 276 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm- > timer.txt > create mode 100644 drivers/clocksource/timer-imx-tpm.c > > -- > 2.7.4
RE: [PATCH V4 0/2] timer: add imx tpm timer support
> -Original Message- > From: Jonathan Cameron [mailto:jonathan.came...@huawei.com] > Sent: Wednesday, July 05, 2017 4:24 PM > To: A.s. Dong > Cc: linux-kernel@vger.kernel.org; Jacky Bai; Anson Huang; > daniel.lezc...@linaro.org; ker...@pengutronix.de; t...@linutronix.de; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > donga...@gmail.com > Subject: Re: [PATCH V4 0/2] timer: add imx tpm timer support > > On Wed, 5 Jul 2017 10:35:10 +0800 > Dong Aisheng wrote: > > > The Timer/PWM Module (TPM) supports input capture, output compare, and > > the generation of PWM signals to control electric motor and power > > management applications. The counter, compare and capture registers > > are clocked by an asynchronous clock that can remain enabled in low > > power modes. TPM can support global counter bus where one TPM drives > > the counter bus for the others, provided bit width is the same. > > > > This patch only adds the timer support. PWM would be added later. > Hi Dong, > > Not relevant to this patch - just an observation! > > Just came across this thread and took a look at the hardware. I see some > of the timers (particularly the flextimers) support quadrature encoder > modes. Just thought I'd point you at some on going discussions on the > IIO list (linux-...@vger.kernel.org) trying to improve the interface for > such devices. Might be of interest (or not depending on whether support > for that functionality is of interest!) > > http://marc.info/?l=linux-iio&m=149904379731556&w=2 > Hi Jonathan, Thanks for the info. I will find time to check it later. Regards Dong Aisheng
RE: [PATCH V3 2/2] timer: imx-tpm: add imx tpm timer support
> -Original Message- > From: Thomas Gleixner [mailto:t...@linutronix.de] > Sent: Tuesday, July 04, 2017 10:43 PM > To: A.s. Dong > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > daniel.lezc...@linaro.org; shawn...@kernel.org; Jacky Bai; Anson Huang; > donga...@gmail.com; ker...@pengutronix.de; Arnd Bergmann; Anson Huang > Subject: RE: [PATCH V3 2/2] timer: imx-tpm: add imx tpm timer support > > On Tue, 4 Jul 2017, A.s. Dong wrote: > > > From: Thomas Gleixner [mailto:t...@linutronix.de] I'm really > > > impressed, that 10 years after we discovered the HPET disaster (See > > > comment in arch/x86/kernel/hpet.c::hpet_next_event) the same > > > hardware idiocy comes around again > > > > > > > Not quite sure but seems a bit different issue. > > The issue is still uncertain but the test shows it's related to fabric > > priority Configuration, if increase the A7 core priority higher than > > GPU, the issue is very hard to be seen. But we don't want to change > > the default priority, we use ETIME check to fix it. > > Well, whether it's hard to be observed or not is not the question. The > point is, that with match equal registers you always have: > > now = read_counter(); > match = now + delta; > write_match(match); > > If the counter advanced past match before the write hits the match > register, then the next interrupt will come after the wrap around of the > counter, which might be close to eternity depending on the counter > frequency and bit width. > Yes we did observe that. TPM CNT is 32 bit width and working at 3Mhz, it takes about 23 seconds to wrap around to trigger the next event. And due to it's single core, RCU stall can't trap it. The kernel Seems have no idea about the wrap around and just resume and keep run. > This advancement can be caused by a gazillion of reasons: > > - Fabric delays > - TLB/cache misses > - . > > The probability might be low, but this can and will happen. And there is > nothing you can do about it. No FIXME in the world will change that > behaviour except that the FIXME actually changes the hardware. > That's Right. > Match equal registers are simply crap in such a context and should never > be used for timers. That's not a new finding, that's well known since 40+ > years. But sure, hardware folks are always smarter. > Thanks for the detailed explanation. I planned to add the following explanation in function for this issue. diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index 4716746..c13a8de 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -99,6 +99,12 @@ static int tpm_set_next_event(unsigned long delta, writel(next, timer_base + TPM_C0V); now = tpm_read_counter(); + /* +* NOTE: We observed in a very small probability, the bus fabric +* contention between GPU and A7 may results a few cycles delay +* of writing CNT registers which may cause the min_delta event got +* missed, so we need add a ETIME check here in case it happened. +*/ return (int)((next - now) <= 0) ? -ETIME : 0; } Do you think it's ok? Regards Dong Aisheng > Thanks, > > tglx >
RE: [PATCH V3 2/2] timer: imx-tpm: add imx tpm timer support
> -Original Message- > From: Thomas Gleixner [mailto:t...@linutronix.de] > Sent: Tuesday, July 04, 2017 10:10 PM > To: A.s. Dong > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > daniel.lezc...@linaro.org; shawn...@kernel.org; Jacky Bai; Anson Huang; > donga...@gmail.com; ker...@pengutronix.de; Arnd Bergmann; Anson Huang > Subject: Re: [PATCH V3 2/2] timer: imx-tpm: add imx tpm timer support > > On Tue, 4 Jul 2017, Dong Aisheng wrote: > > > IMX Timer/PWM Module (TPM) supports both timer and pwm function while > > this patch only adds the timer support. PWM would be added later. > > > > The TPM counter, compare and capture registers are clocked by an > > asynchronous clock that can remain enabled in low power modes. > > > > Due to the possible bus fabric contention, the CNT write may take a > > few more cycles and we need add ETIME check in case current delta > > event program gets missed. > > > > Cc: Daniel Lezcano > > Cc: Arnd Bergmann > > Cc: Thomas Gleixner > > Cc: Shawn Guo > > Cc: Anson Huang > > Cc: Bai Ping > > Signed-off-by: Dong Aisheng > > > > --- > > ChangeLog: > > v2->v3: > > * address all comments from Daniel Lezcano > > * add more explaination on ETIME check in commit message > > Actually the logic wants to be explained in a comment inside the function > as well. > Good suggestion, will add them inside function as well. > I'm really impressed, that 10 years after we discovered the HPET disaster > (See comment in arch/x86/kernel/hpet.c::hpet_next_event) the same > hardware idiocy comes around again > Not quite sure but seems a bit different issue. The issue is still uncertain but the test shows it's related to fabric priority Configuration, if increase the A7 core priority higher than GPU, the issue is very hard to be seen. But we don't want to change the default priority, we use ETIME check to fix it. Probably I would be better add a FIXME prefix before the comments in code as well because it's still uncertain. Regards Dong Aisheng > Thanks, > > tglx >
RE: [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
> -Original Message-
> From: Stephen Boyd [mailto:sb...@codeaurora.org]
> Sent: Saturday, July 01, 2017 8:56 AM
> To: Dong Aisheng
> Cc: A.s. Dong; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com;
> shawn...@kernel.org; Anson Huang; Jacky Bai
> Subject: Re: [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk
> support
>
> On 06/20, Dong Aisheng wrote:
> > Hi Stephen,
> >
> > On Mon, Jun 19, 2017 at 06:45:12PM -0700, Stephen Boyd wrote:
> > > On 05/15, Dong Aisheng wrote:
> > > > ---
> > > > drivers/clk/clk-divider.c| 2 ++
> > > > include/linux/clk-provider.h | 4
> > > > 2 files changed, 6 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > > > index 96386ff..f78ba7a 100644
> > > > --- a/drivers/clk/clk-divider.c
> > > > +++ b/drivers/clk/clk-divider.c
> > > > @@ -125,6 +125,8 @@ unsigned long divider_recalc_rate(struct
> > > > clk_hw *hw, unsigned long parent_rate,
> > > >
> > > > div = _get_div(table, val, flags, divider->width);
> > > > if (!div) {
> > > > + if (flags & CLK_DIVIDER_ZERO_GATE)
> > > > + return 0;
> > > > WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> > >
> > > Why not use the CLK_DIVIDER_ALLOW_ZERO flag? A clk being off doesn't
> > > mean the rate is 0. The divider is just disabled, so we would
> > > consider the rate as whatever the parent is, which is what this code
> > > does before this patch. Similarly, we don't do anything about gate
> > > clocks and return a rate of 0 when they're disabled.
> > >
> >
> > The semantic of CLK_DIVIDER_ALLOW_ZERO seems a bit different.
> >
> > See below definition:
> > * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which
> have
> > * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero
> divisor.
> > * Some hardware implementations gracefully handle this case and
> allow a
> > * zero divisor by not modifying their input clock
> > * (divide by one / bypass).
> >
> > zero divisor is simply as divide by one or bypass which is supported
> > by hardware.
> >
> > But it's not true for this hardware.
> >
> > If we consider the rate as whatever the parent is if divider is zero,
> > we may got an issue like below:
> > e.g.
> > Assuming spll_bus_clk divider is 0x0 and it may be enabled by users
> > directly without setting a rate first.
> >
> > Then the clock tree looks like:
> > ...
> > spll_pfd011 500210526 0 0
> > spll_pfd_sel 11 500210526 0 0
> > spll_sel 11 500210526 0 0
> > spll_bus_clk 11 500210526 0 0
> >
> > But the spll_bus_clk clock rate actually is wrong and it's even not
> > enabled, not like CLK_DIVIDER_ALLOW_ZERO which zero divider means
> simply bypass.
> >
> > So for this case, we probably can't simply assume zero divider rate as
> > its parent, it is actually set to 0 in hw, although it's something
> > like gate, but a bit different from gate as the normal gate does not
> > affect divider where you can keep the rate.
> >
> > How would you suggest for this?
> >
>
> It seems that set_rate() and enable/disable are conflated here.
> From what you describe, it sounds like the clk is considered off when the
> divider value is zero, and it's on when the divider value is non-zero.
>
> I'd suggest you make it so this clk supports enable/disable and set_rate
> with the same register. Something like, set rate when the clk is disabled
> will cache the rate request and only when the clk is enabled will the
> driver actually program the hardware to have the requested divider value.
> Similarly, when the clk is disabled we'll write a 0 there, but when the
> clk is enabled we'll restore whatever rate (divider) was chosen last.
>
> It does mean that recalc rate will be sort of odd, because when the clk
> is off it will return 0, and when the clk is on it will return the right
> rate. So to make things work, we'll need to return the cached rate in
> recalc rate when the clk is off and read the hardware when the clk is on.
> Probably an if register ==
> 0 the
RE: [PATCH 4/9] clk: imx: add pllv4 support
> -Original Message-
> From: Stephen Boyd [mailto:sb...@codeaurora.org]
> Sent: Saturday, July 01, 2017 8:37 AM
> To: Dong Aisheng
> Cc: A.s. Dong; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com;
> shawn...@kernel.org; Anson Huang; Jacky Bai
> Subject: Re: [PATCH 4/9] clk: imx: add pllv4 support
>
> On 06/20, Dong Aisheng wrote:
> > On Mon, Jun 19, 2017 at 06:59:17PM -0700, Stephen Boyd wrote:
> > > On 05/15, Dong Aisheng wrote:
> > > > +
> > > > + if (clk_pllv4_is_enabled(hw)) {
> > > > + WARN(1, "clk_pllv4: can't change rate when pll is
> enabled");
> > > > + return -EINVAL;
> > >
> > > Sad, CLK_SET_RATE_GATE isn't working for you I suppose?
> > >
> >
> > CLK_SET_RATE_GATE can't work in early stage before running
> clk_disable_unused.
> > At that point, the clock tree state is still not consistent with HW.
> > e.g. prepare/enable count is still zero but it's actually enabled due
> > to reset state or bootloader.
> >
> > The code here is adding a double check in case user sets rate in early
> stage.
> >
> > However, probably it could also be moved into clock core as it's not
> > platform dependant behavior?
> >
>
> Ok. It would be good to fix the core framework to synchronize the
> prepared/enabled state at registration time so we don't need this check
> in the driver.
>
I will prepare a core fix later and remove these checks first.
Regards
Dong Aisheng
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> Linux Foundation Collaborative Project
RE: [PATCH 9/9] clk: imx: add imx7ulp clk driver
> -Original Message- > From: Stephen Boyd [mailto:sb...@codeaurora.org] > Sent: Saturday, July 01, 2017 8:35 AM > To: A.s. Dong > Cc: Dong Aisheng; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com; > shawn...@kernel.org; Anson Huang; Jacky Bai > Subject: Re: [PATCH 9/9] clk: imx: add imx7ulp clk driver > > On 06/21, A.s. Dong wrote: > > > -Original Message- > > > From: Stephen Boyd [mailto:sb...@codeaurora.org] > > > Sent: Wednesday, June 21, 2017 4:42 AM > > > To: Dong Aisheng > > > Cc: A.s. Dong; linux-...@vger.kernel.org; > > > linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang; Jacky Bai > > > Subject: Re: [PATCH 9/9] clk: imx: add imx7ulp clk driver > > > > > > On 06/20, Dong Aisheng wrote: > > > > On Mon, Jun 19, 2017 at 07:01:19PM -0700, Stephen Boyd wrote: > > > > > > > > > > Any reason why it can't be a platform driver? If not, please add > > > > > some comment explaining why. > > > > > > > > > > > > > Timer is using it at early stage. GIC seems not although standard > > > > binding claim possible clock requirement. > > > > Others still not sure. > > > > > > > > What your suggestion? > > > > Convert timer to platform driver and make clock as platform driver > > > > as > > > well? > > > > > > > > > > The timer can't be a platform driver because it would be too late. > > > The clock driver could register whatever clks are required for the > > > timer/GIC in a CLK_OF_DECLARE_DRIVER hook, and then leave the rest > > > to a platform driver. This way we get some of the device driver > framework in this code. > > > > > > > Okay, I could try it. Thanks. > > > > One thing is that TPM clock has a lot parents and parents having > > parents, as well as PIT timer. So I may need enable more than half > > clocks in CLK_OF_DECLARE_DRIVER hook. > > That's fine. > > > > > BTW, What's benefit to convert into two parts of probe? > > I'm not quite if I already get it all, can you help clarify it? > > > > The benefit is that we still get a platform driver and we can associate a > device pointer with the clock controller eventually. > Here's a reply I sent yesterday on the same topic: > > Reasons (in no particular order): > > 1. We get a dev pointer to use with clk_hw_register() > > 2. We can handle probe defer if some resource is not available > > 3. Using device model gets us a hook into power management frameworks > like runtime PM and system PM for things like suspend and hibernate > > 4. It encourages a single DT node clk controller style binding > instead of a single node per clk style binding > > 5. We can use non-DT specific functions like devm_ioremap_resource() to > map > registers and acquire other resources, leading to more portable and > generic code > > 6. We may be able to make the device driver a module, which will > make distros happy if we don't have to compile in all > these clk drivers to the resulting vmlinux (this one doesn't > apply here) > Very clear. Thanks for the great explanation. Regards Dong Aisheng > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a > Linux Foundation Collaborative Project
RE: [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
Hi Stephen,
> -Original Message-
> From: Dong Aisheng [mailto:donga...@gmail.com]
> Sent: Tuesday, June 20, 2017 5:08 PM
> To: Stephen Boyd
> Cc: A.s. Dong; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com;
> shawn...@kernel.org; Anson Huang; Jacky Bai
> Subject: Re: [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk
> support
>
> Hi Stephen,
>
> On Mon, Jun 19, 2017 at 06:45:12PM -0700, Stephen Boyd wrote:
> > On 05/15, Dong Aisheng wrote:
> > > ---
> > > drivers/clk/clk-divider.c| 2 ++
> > > include/linux/clk-provider.h | 4
> > > 2 files changed, 6 insertions(+)
> > >
> > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > > index 96386ff..f78ba7a 100644
> > > --- a/drivers/clk/clk-divider.c
> > > +++ b/drivers/clk/clk-divider.c
> > > @@ -125,6 +125,8 @@ unsigned long divider_recalc_rate(struct clk_hw
> > > *hw, unsigned long parent_rate,
> > >
> > > div = _get_div(table, val, flags, divider->width);
> > > if (!div) {
> > > + if (flags & CLK_DIVIDER_ZERO_GATE)
> > > + return 0;
> > > WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> >
> > Why not use the CLK_DIVIDER_ALLOW_ZERO flag? A clk being off doesn't
> > mean the rate is 0. The divider is just disabled, so we would consider
> > the rate as whatever the parent is, which is what this code does
> > before this patch. Similarly, we don't do anything about gate clocks
> > and return a rate of 0 when they're disabled.
> >
>
> The semantic of CLK_DIVIDER_ALLOW_ZERO seems a bit different.
>
> See below definition:
> * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
> * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero
> divisor.
> * Some hardware implementations gracefully handle this case and allow
> a
> * zero divisor by not modifying their input clock
> * (divide by one / bypass).
>
> zero divisor is simply as divide by one or bypass which is supported by
> hardware.
>
> But it's not true for this hardware.
>
> If we consider the rate as whatever the parent is if divider is zero, we
> may got an issue like below:
> e.g.
> Assuming spll_bus_clk divider is 0x0 and it may be enabled by users
> directly without setting a rate first.
>
> Then the clock tree looks like:
> ...
> spll_pfd011 500210526 0 0
> spll_pfd_sel 11 500210526 0 0
> spll_sel 11 500210526 0 0
> spll_bus_clk 11 500210526 0 0
>
> But the spll_bus_clk clock rate actually is wrong and it's even not
> enabled, not like CLK_DIVIDER_ALLOW_ZERO which zero divider means simply
> bypass.
>
> So for this case, we probably can't simply assume zero divider rate as its
> parent, it is actually set to 0 in hw, although it's something like gate,
> but a bit different from gate as the normal gate does not affect divider
> where you can keep the rate.
>
> How would you suggest for this?
>
Any suggestions?
Regards
Dong Aisheng
> Regards
> Dong Aisheng
>
> > > "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
> > > clk_hw_get_name(hw));
> >
> > --
> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> > Linux Foundation Collaborative Project
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-clk"
> > in the body of a message to majord...@vger.kernel.org More majordomo
> > info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH V4 0/7] tty: serial: lpuart: add imx7ulp support
Ping...
> -Original Message-
> From: Dong Aisheng [mailto:aisheng.d...@nxp.com]
> Sent: Tuesday, June 13, 2017 10:56 AM
> To: linux-ser...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> gre...@linuxfoundation.org; jsl...@suse.com; Andy Duan; ste...@agner.ch;
> Mingkai Hu; Y.b. Lu; nikita.yo...@cogentembedded.com;
> andy.shevche...@gmail.com; donga...@gmail.com; A.s. Dong
> Subject: [PATCH V4 0/7] tty: serial: lpuart: add imx7ulp support
>
> The lpuart in imx7ulp is basically the same as ls1021a. It's also
> 32 bit width register, but unlike ls1021a, it's little endian.
> Besides that, imx7ulp lpuart has a minor different register layout from
> ls1021a that it has four extra registers (verid, param, global,
> pincfg) located at the beginning of register map, which are currently not
> used by the driver and less to be used later.
>
> Furthermore, this patch serial also add a new more accurate baud rate
> calculation method as MX7ULP can't divide a suitable baud rate with the
> default setting.
>
> Currently the new baud rate calculation is only enabled on MX7ULP.
> However, i guess the Layerscape may also be able to use it as there seems
> to be no difference in baud rate setting register after checking the
> Layerscape Reference Manual.
>
> As i don't have Layerscape boards, i can't test it, so i only enable it
> for MX7ULP by default to avoid a potential break.
>
> I copied LayerScape guys in this series and hope they can help test later.
> If it works on Layerscape as well, then they can switch to the new setting
> too and totally remove the old stuff.
>
> ChangeLog:
> v3->v4:
> * Minor changes.
>1) Remove one duplicated blank line
>2) Removed on unneeded semicolon in switch catched by 0day Robot
> v2->v3:
> * Remove global lpuart_is_be.
>Instead use struct uart_port's iotype member.
>lpuart32_read/write API prototype is also updated to use the iotype to
>distingush the endians. And most importantly, this way also works with
>earlycon.
>
> v1->v2:
> * Patch 2/4/5 chagned, other no changes.
>See individuals for details.
>
> Dong Aisheng (7):
> tty: serial: lpuart: introduce lpuart_soc_data to represent SoC
> property
> tty: serial: lpuart: refactor lpuart32_{read|write} prototype
> tty: serial: lpuart: add little endian 32 bit register support
> dt-bindings: serial: fsl-lpuart: add i.MX7ULP support
> tty: serial: lpuart: add imx7ulp support
> tty: serial: lpuart: add earlycon support for imx7ulp
> tty: serial: lpuart: add a more accurate baud rate calculation method
>
> .../devicetree/bindings/serial/fsl-lpuart.txt | 2 +
> drivers/tty/serial/fsl_lpuart.c| 286 ++--
> -
> 2 files changed, 201 insertions(+), 87 deletions(-)
>
> --
> 2.7.4
RE: [PATCH 9/9] clk: imx: add imx7ulp clk driver
> -Original Message- > From: Stephen Boyd [mailto:sb...@codeaurora.org] > Sent: Wednesday, June 21, 2017 4:42 AM > To: Dong Aisheng > Cc: A.s. Dong; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; mturque...@baylibre.com; > shawn...@kernel.org; Anson Huang; Jacky Bai > Subject: Re: [PATCH 9/9] clk: imx: add imx7ulp clk driver > > On 06/20, Dong Aisheng wrote: > > On Mon, Jun 19, 2017 at 07:01:19PM -0700, Stephen Boyd wrote: > > > > > > Any reason why it can't be a platform driver? If not, please add > > > some comment explaining why. > > > > > > > Timer is using it at early stage. GIC seems not although standard > > binding claim possible clock requirement. > > Others still not sure. > > > > What your suggestion? > > Convert timer to platform driver and make clock as platform driver as > well? > > > > The timer can't be a platform driver because it would be too late. The > clock driver could register whatever clks are required for the timer/GIC > in a CLK_OF_DECLARE_DRIVER hook, and then leave the rest to a platform > driver. This way we get some of the device driver framework in this code. > Okay, I could try it. Thanks. One thing is that TPM clock has a lot parents and parents having parents, as well as PIT timer. So I may need enable more than half clocks in CLK_OF_DECLARE_DRIVER hook. BTW, What's benefit to convert into two parts of probe? I'm not quite if I already get it all, can you help clarify it? Regards Dong Aisheng > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux > Foundation Collaborative Project
RE: [PATCH V3 5/7] tty: serial: lpuart: add imx7ulp support
> -Original Message-
> From: Andy Duan
> Sent: Tuesday, June 13, 2017 11:02 AM
> To: A.s. Dong; linux-ser...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> gre...@linuxfoundation.org; jsl...@suse.com; ste...@agner.ch; Mingkai Hu;
> Y.b. Lu; nikita.yo...@cogentembedded.com; andy.shevche...@gmail.com;
> donga...@gmail.com; A.s. Dong
> Subject: RE: [PATCH V3 5/7] tty: serial: lpuart: add imx7ulp support
>
> From: Dong Aisheng Sent: Monday, June 12, 2017
> 11:37 PM
> >The lpuart of imx7ulp is basically the same as ls1021a. It's also
> >32 bit width register, but unlike ls1021a, it's little endian.
> >Besides that, imx7ulp lpuart has a minor different register layout from
> >ls1021a that it has four extra registers (verid, param, global,
> >pincfg) located at the beginning of register map, which are currently
> >not used by the driver and less to be used later.
> >
> >To ease the register difference handling, we add a reg_off member in
> >lpuart_soc_data structure to represent if the normal
> >lpuart32_{read|write} requires plus a offset to hide the issue.
> >
> >Cc: Greg Kroah-Hartman
> >Cc: Jiri Slaby
> >Cc: Stefan Agner
> >Cc: Mingkai Hu
> >Cc: Yangbo Lu
> >Cc: Fugang Duan
> >Signed-off-by: Dong Aisheng
> >
> >---
> >ChangeLog:
> >v2->v3:
> > * use standard port->iotype to represent the endians.
> >v1->v2:
> > * remove lpuart_reg_off according to Stefan's suggestion
> >---
> > drivers/tty/serial/fsl_lpuart.c | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> >diff --git a/drivers/tty/serial/fsl_lpuart.c
> >b/drivers/tty/serial/fsl_lpuart.c index
> >bbf47a0..9d05e53 100644
> >--- a/drivers/tty/serial/fsl_lpuart.c
> >+++ b/drivers/tty/serial/fsl_lpuart.c
> >@@ -231,6 +231,9 @@
> > #define DEV_NAME"ttyLP"
> > #define UART_NR 6
> >
> >+/* IMX lpuart has four extra unused regs located at the beginning */
> >+#define IMX_REG_OFF 0x10
> >+
> > struct lpuart_port {
> > struct uart_portport;
> > struct clk *clk;
> >@@ -259,6 +262,7 @@ struct lpuart_port {
> >
> > struct lpuart_soc_data {
> > chariotype;
> >+u8 reg_off;
> > };
> >
> > static const struct lpuart_soc_data vf_data = { @@ -267,12 +271,17 @@
> >static const struct lpuart_soc_data vf_data = {
> >
> > static const struct lpuart_soc_data ls_data = {
> > .iotype = UPIO_MEM32BE,
> >+};
> >
> >+static struct lpuart_soc_data imx_data = {
> >+.iotype = UPIO_MEM32,
> >+.reg_off = IMX_REG_OFF,
> > };
> >
> > static const struct of_device_id lpuart_dt_ids[] = {
> > { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
> > { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
> >+{ .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
> > { /* sentinel */ }
> > };
> > MODULE_DEVICE_TABLE(of, lpuart_dt_ids); @@ -2020,6 +2029,7 @@ static
> >int lpuart_probe(struct platform_device *pdev)
> > if (IS_ERR(sport->port.membase))
> > return PTR_ERR(sport->port.membase);
> >
> >+sport->port.membase += sdata->reg_off;
> > sport->port.mapbase = res->start;
>
> Also update the mapbase.
>
The idea behind is only do the quirk for io remapped address.
Mapbase(physical address) is not needed for lpuart32 currently.
Probably it could be changed when lpuart32 DMA function is added.
Regards
Dong Aisheng
> > sport->port.dev = &pdev->dev;
> > sport->port.type = PORT_LPUART;
> >--
> >2.7.4
RE: [PATCH V3 3/7] tty: serial: lpuart: add little endian 32 bit register support
> -Original Message-
> From: Andy Duan
> Sent: Tuesday, June 13, 2017 11:09 AM
> To: A.s. Dong; linux-ser...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> gre...@linuxfoundation.org; jsl...@suse.com; ste...@agner.ch; Mingkai Hu;
> Y.b. Lu; nikita.yo...@cogentembedded.com; andy.shevche...@gmail.com;
> donga...@gmail.com; A.s. Dong
> Subject: RE: [PATCH V3 3/7] tty: serial: lpuart: add little endian 32 bit
> register support
>
> From: Dong Aisheng Sent: Monday, June 12, 2017
> 11:37 PM
> >To: linux-ser...@vger.kernel.org
> >Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> >gre...@linuxfoundation.org; jsl...@suse.com; Andy Duan
> >; ste...@agner.ch; Mingkai Hu
> >; Y.b. Lu ;
> >nikita.yo...@cogentembedded.com; andy.shevche...@gmail.com;
> >donga...@gmail.com; A.S. Dong
> >Subject: [PATCH V3 3/7] tty: serial: lpuart: add little endian 32 bit
> >register support
> >
> >Use standard port->iotype to distinguish endian difference. Note as we
> >read/write register by checking iotype dynamically, we need to
> >initialize the iotype correctly for earlycon as well to avoid a break.
> >
> >Cc: Greg Kroah-Hartman
> >Cc: Jiri Slaby (supporter:TTY LAYER)
> >Cc: Stefan Agner
> >Cc: Mingkai Hu
> >Cc: Yangbo Lu
> >Cc: Fugang Duan
> >Signed-off-by: Dong Aisheng
> >
> >ChangeLog:
> >v2->v3:
> > * Instead of using global var, use standard port->iotype to distinguish
> > endian difference.
> >v1->v2:
> > * No changes
> >---
> > drivers/tty/serial/fsl_lpuart.c | 43
> >+++--
> >
> > 1 file changed, 29 insertions(+), 14 deletions(-)
> >
> >diff --git a/drivers/tty/serial/fsl_lpuart.c
> >b/drivers/tty/serial/fsl_lpuart.c index
> >ed9db2f..bbf47a0 100644
> >--- a/drivers/tty/serial/fsl_lpuart.c
> >+++ b/drivers/tty/serial/fsl_lpuart.c
> >@@ -280,15 +280,29 @@ MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
> > /* Forward declare this for the dma callbacks*/ static void
> >lpuart_dma_tx_complete(void *arg);
> >
> >-static inline u32 lpuart32_read(struct uart_port *port, u32 reg_off) -{
> >-return ioread32be(port->membase + reg_off);
> >+static inline u32 lpuart32_read(struct uart_port *port, u32 off) {
> >+switch (port->iotype) {
> >+case UPIO_MEM32:
> >+return readl(port->membase + off);
> >+case UPIO_MEM32BE:
> >+return ioread32be(port->membase + off);
> >+default:
> >+return 0;
> >+};
> > }
> >
> > static inline void lpuart32_write(struct uart_port *port, u32 val,
> >- u32 reg_off)
> >+ u32 off)
> > {
> >-iowrite32be(val, port->membase + reg_off);
> >+switch (port->iotype) {
> >+case UPIO_MEM32:
> >+writel(val, port->membase + off);
> >+break;
> >+case UPIO_MEM32BE:
> >+iowrite32be(val, port->membase + off);
> >+break;
> >+};
> > }
> >
> > static void lpuart_stop_tx(struct uart_port *port) @@ -602,7 +616,7 @@
> >static irqreturn_t lpuart_txint(int irq, void *dev_id)
> >
> > spin_lock_irqsave(&sport->port.lock, flags);
> > if (sport->port.x_char) {
> >-if (sport->port.iotype & UPIO_MEM32BE)
> >+if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
> > lpuart32_write(&sport->port, sport->port.x_char,
> UARTDATA);
> > else
> > writeb(sport->port.x_char, sport->port.membase +
> > UARTDR);
> @@
> >-610,14 +624,14 @@ static irqreturn_t lpuart_txint(int irq, void
> >*dev_id)
> > }
> >
> > if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
> >-if (sport->port.iotype & UPIO_MEM32BE)
> >+if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE))
>
> Can use one macro instead of sport->port.iotype & (UPIO_MEM32 |
> UPIO_MEM32BE ?
>
UPIO_MEM32 and UPIO_MEM32BE are serial core definitions.
If we use one macro for it, then the macro seems be better in serial core.
But I don't think it's quite necessary.
Explicit using also make the code look clearer.
Regards
Dong Aisheng
> > lpuart32_stop_tx(&sport->port);
> > else
> > lp
