[tip: timers/core] clocksource/drivers/dw_apb_timer_of: Add handling for potential memory leak
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 397dc6f7ca3c858dc95800f299357311ccf679e6
Gitweb:
https://git.kernel.org/tip/397dc6f7ca3c858dc95800f299357311ccf679e6
Author:Dinh Nguyen
AuthorDate:Mon, 22 Mar 2021 07:18:44 -05:00
Committer: Daniel Lezcano
CommitterDate: Thu, 08 Apr 2021 13:24:53 +02:00
clocksource/drivers/dw_apb_timer_of: Add handling for potential memory leak
Add calls to disable the clock and unmap the timer base address in case
of any failures.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20210322121844.2271041-1-dingu...@kernel.org
---
drivers/clocksource/dw_apb_timer_of.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index 2b2c3b5..3819ef5 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -52,18 +52,34 @@ static int __init timer_get_base_and_rate(struct
device_node *np,
return 0;
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- return PTR_ERR(timer_clk);
+ if (IS_ERR(timer_clk)) {
+ ret = PTR_ERR(timer_clk);
+ goto out_pclk_disable;
+ }
ret = clk_prepare_enable(timer_clk);
if (ret)
- return ret;
+ goto out_timer_clk_put;
*rate = clk_get_rate(timer_clk);
- if (!(*rate))
- return -EINVAL;
+ if (!(*rate)) {
+ ret = -EINVAL;
+ goto out_timer_clk_disable;
+ }
return 0;
+
+out_timer_clk_disable:
+ clk_disable_unprepare(timer_clk);
+out_timer_clk_put:
+ clk_put(timer_clk);
+out_pclk_disable:
+ if (!IS_ERR(pclk)) {
+ clk_disable_unprepare(pclk);
+ clk_put(pclk);
+ }
+ iounmap(*base);
+ return ret;
}
static int __init add_clockevent(struct device_node *event_timer)
Re: [PATCH][next] clk: socfpga: remove redundant initialization of variable div
On 4/6/21 1:27 PM, Colin King wrote:
From: Colin Ian King
The variable div is being initialized with a value that is
never read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/clk/socfpga/clk-gate-s10.c | 2 +-
drivers/clk/socfpga/clk-pll-s10.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/socfpga/clk-gate-s10.c
b/drivers/clk/socfpga/clk-gate-s10.c
index f9f403d7bb58..b84f2627551e 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -31,7 +31,7 @@ static unsigned long socfpga_dbg_clk_recalc_rate(struct
clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
- u32 div = 1, val;
+ u32 div, val;
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= GENMASK(socfpgaclk->width - 1, 0);
diff --git a/drivers/clk/socfpga/clk-pll-s10.c
b/drivers/clk/socfpga/clk-pll-s10.c
index bc37461d43c0..70076a80149d 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -107,7 +107,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw
*hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
- u32 div = 1;
+ u32 div;
div = ((readl(socfpgaclk->hw.reg) &
SWCTRLBTCLKSEL_MASK) >>
Acked-by: Dinh Nguyen
Re: [PATCH] clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
On 4/6/21 12:01 PM, Colin King wrote:
From: Colin Ian King
There is an error return path that is not kfree'ing socfpga_clk leading
to a memory leak. Fix this by adding in the missing kfree call.
Addresses-Coverity: ("Resource leak")
Signed-off-by: Colin Ian King
---
drivers/clk/socfpga/clk-gate-a10.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/socfpga/clk-gate-a10.c
b/drivers/clk/socfpga/clk-gate-a10.c
index f5cba8298712..738c53391e39 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -146,6 +146,7 @@ static void __init __socfpga_gate_init(struct device_node
*node,
if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
pr_err("%s: failed to find altr,sys-mgr regmap!\n",
__func__);
+ kfree(socfpga_clk);
return;
}
}
Acked-by: Dinh Nguyen
Re: [PATCHv2 RESEND] firmware: stratix10-svc: build only on 64-bit ARM
On 4/5/21 5:30 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 10:20:26AM -0500, Dinh Nguyen wrote:
On 4/4/21 9:08 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 07:46:09AM -0500, Dinh Nguyen wrote:
From: Krzysztof Kozlowski
The Stratix10 service layer and RCU drivers are useful only on
Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM
fails:
drivers/firmware/stratix10-rsu.c: In function 'rsu_status_callback':
include/linux/compiler_types.h:320:38: error: call to
'__compiletime_assert_179'
declared with attribute error: FIELD_GET: type of reg too small for mask
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
...
drivers/firmware/stratix10-rsu.c:96:26: note: in expansion of macro
'FIELD_GET'
priv->status.version = FIELD_GET(RSU_VERSION_MASK,
Fixes: 4483397b0353 ("ARM: socfpga: drop ARCH_SOCFPGA")
Where is this commit id? I don't see it in Linus's tree, is it
somewhere else?
It's in the for-next branch in the soc tree. This patch fixes a patch that
was just recently submitted by Krzysztof.
Then it needs to go through that tree, while you sent it "To:" me, and I
can't do anything with it at the moment :(
Ah okay, got it, thanks!
Dinh
Re: [PATCHv2 RESEND] firmware: stratix10-svc: build only on 64-bit ARM
On 4/4/21 9:08 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 07:46:09AM -0500, Dinh Nguyen wrote:
From: Krzysztof Kozlowski
The Stratix10 service layer and RCU drivers are useful only on
Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM
fails:
drivers/firmware/stratix10-rsu.c: In function 'rsu_status_callback':
include/linux/compiler_types.h:320:38: error: call to
'__compiletime_assert_179'
declared with attribute error: FIELD_GET: type of reg too small for mask
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
...
drivers/firmware/stratix10-rsu.c:96:26: note: in expansion of macro
'FIELD_GET'
priv->status.version = FIELD_GET(RSU_VERSION_MASK,
Fixes: 4483397b0353 ("ARM: socfpga: drop ARCH_SOCFPGA")
Where is this commit id? I don't see it in Linus's tree, is it
somewhere else?
It's in the for-next branch in the soc tree. This patch fixes a patch
that was just recently submitted by Krzysztof.
Dinh
[PATCHv2 RESEND] firmware: stratix10-svc: build only on 64-bit ARM
From: Krzysztof Kozlowski
The Stratix10 service layer and RCU drivers are useful only on
Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM
fails:
drivers/firmware/stratix10-rsu.c: In function 'rsu_status_callback':
include/linux/compiler_types.h:320:38: error: call to
'__compiletime_assert_179'
declared with attribute error: FIELD_GET: type of reg too small for mask
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
...
drivers/firmware/stratix10-rsu.c:96:26: note: in expansion of macro
'FIELD_GET'
priv->status.version = FIELD_GET(RSU_VERSION_MASK,
Fixes: 4483397b0353 ("ARM: socfpga: drop ARCH_SOCFPGA")
Signed-off-by: Krzysztof Kozlowski
Reported-by: kernel test robot
Acked-by: Richard Gong
Signed-off-by: Dinh Nguyen
---
v2: add Fixes tag
---
drivers/firmware/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 6a4e882e448d..08bd4d01fb04 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE
config INTEL_STRATIX10_SERVICE
tristate "Intel Stratix10 Service Layer"
- depends on ARCH_INTEL_SOCFPGA && HAVE_ARM_SMCCC
+ depends on ARCH_INTEL_SOCFPGA && ARM64 && HAVE_ARM_SMCCC
default n
help
Intel Stratix10 service layer runs at privileged exception level,
--
2.25.1
[PATCH] firmware: stratix10-svc: build only on 64-bit ARM
From: Krzysztof Kozlowski The Stratix10 service layer and RCU drivers are useful only on Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM fails: drivers/firmware/stratix10-rsu.c: In function 'rsu_status_callback': include/linux/compiler_types.h:320:38: error: call to '__compiletime_assert_179' declared with attribute error: FIELD_GET: type of reg too small for mask _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ... drivers/firmware/stratix10-rsu.c:96:26: note: in expansion of macro 'FIELD_GET' priv->status.version = FIELD_GET(RSU_VERSION_MASK, Signed-off-by: Krzysztof Kozlowski Reported-by: kernel test robot Acked-by: Richard Gong Signed-off-by: Dinh Nguyen --- drivers/firmware/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 6a4e882e448d..08bd4d01fb04 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE config INTEL_STRATIX10_SERVICE tristate "Intel Stratix10 Service Layer" - depends on ARCH_INTEL_SOCFPGA && HAVE_ARM_SMCCC + depends on ARCH_INTEL_SOCFPGA && ARM64 && HAVE_ARM_SMCCC default n help Intel Stratix10 service layer runs at privileged exception level, -- 2.25.1
[PATCH] dt-bindings: net: micrel-ksz90x1.txt: correct documentation
Correct the Micrel phy documentation for the ksz9021 and ksz9031 phys
for how the phy skews are set.
Signed-off-by: Dinh Nguyen
---
.../bindings/net/micrel-ksz90x1.txt | 96 ++-
1 file changed, 94 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
index b921731cd970..df9e844dd6bc 100644
--- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
+++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt
@@ -65,6 +65,71 @@ KSZ9031:
step is 60ps. The default value is the neutral setting, so setting
rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
+ The KSZ9031 hardware supports a range of skew values from negative to
+ positive, where the specific range is property dependent. All values
+ specified in the devicetree are offset by the minimum value so they
+ can be represented as positive integers in the devicetree since it's
+ difficult to represent a negative number in the devictree.
+
+ The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
+
+ Pad Skew Value Delay (ps) Devicetree Value
+ --
+ 0_ -900ps 0
+ 0_0001 -840ps 60
+ 0_0010 -780ps 120
+ 0_0011 -720ps 180
+ 0_0100 -660ps 240
+ 0_0101 -600ps 300
+ 0_0110 -540ps 360
+ 0_0111 -480ps 420
+ 0_1000 -420ps 480
+ 0_1001 -360ps 540
+ 0_1010 -300ps 600
+ 0_1011 -240ps 660
+ 0_1100 -180ps 720
+ 0_1101 -120ps 780
+ 0_1110 -60ps 840
+ 0_ 0ps 900
+ 1_ 60ps960
+ 1_0001 120ps 1020
+ 1_0010 180ps 1080
+ 1_0011 240ps 1140
+ 1_0100 300ps 1200
+ 1_0101 360ps 1260
+ 1_0110 420ps 1320
+ 1_0111 480ps 1380
+ 1_1000 540ps 1440
+ 1_1001 600ps 1500
+ 1_1010 660ps 1560
+ 1_1011 720ps 1620
+ 1_1100 780ps 1680
+ 1_1101 840ps 1740
+ 1_1110 900ps 1800
+ 1_ 960ps 1860
+
+ The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
+ data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
+
+ Pad Skew Value Delay (ps) Devicetree Value
+ --
+ -420ps 0
+ 0001 -360ps 60
+ 0010 -300ps 120
+ 0011 -240ps 180
+ 0100 -180ps 240
+ 0101 -120ps 300
+ 0110 -60ps 360
+ 0111 0ps 420
+ 1000 60ps480
+ 1001 120ps 540
+ 1010 180ps 600
+ 1011 240ps 660
+ 1100 300ps 720
+ 1101 360ps 780
+ 1110 420ps 840
+ 480ps 900
+
Optional properties:
Maximum value of 1860, default value 900:
@@ -120,11 +185,21 @@ KSZ9131:
Examples:
+ /* Attach to an Ethernet device with autodetected PHY */
+{
+ rxc-skew-ps = <1800>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <1800>;
+ txen-skew-ps = <0>;
+ status = "okay";
+ };
+
+ /* Attach to an explicitly-specified PHY */
mdio {
phy0: ethernet-phy@0 {
- rxc-skew-ps = <3000>;
+ rxc-skew-ps = <1800>;
rxdv-skew-ps = <0>;
- txc-skew-ps = <3000>;
+ txc-skew-ps = <1800>;
txen-skew-ps = <0>;
reg = <0>;
};
@@ -133,3 +208,20 @@ Examples:
phy = <>;
phy-mode = "rgmii-id";
};
+
+References
+
+ Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
+ http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
+
+ Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
+ http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
+
+Notes:
+
+ Note that a previous ver
Re: drivers/clocksource/dw_apb_timer_of.c:66 timer_get_base_and_rate() warn: 'timer_clk' not released on lines: 64.
Hi Daniel,
2/21 4:58 AM, Daniel Lezcano wrote:
Dinh,
is it possible to have a look at this issue?
Thanks
Sorry, but somehow I missed cc'ing you when I first sent the patch.
I've resent it just now.
Dinh
On 22/02/2021 07:21, Dan Carpenter wrote:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 55f62bc873477dae2c45bbbc30b86cf3e0982f3b
commit: 5d9814df0aec56a638bbf20795abb4cfaf3cd331
clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available
config: arm64-randconfig-m031-20210221 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
Reported-by: Dan Carpenter
New smatch warnings:
drivers/clocksource/dw_apb_timer_of.c:66 timer_get_base_and_rate() warn:
'timer_clk' not released on lines: 64.
Old smatch warnings:
drivers/clocksource/dw_apb_timer_of.c:66 timer_get_base_and_rate() warn:
'*base' not released on lines: 56,64.
vim +/timer_clk +66 drivers/clocksource/dw_apb_timer_of.c
5d9814df0aec56 drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2020-12-05
17 static int __init timer_get_base_and_rate(struct device_node *np,
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
18 void __iomem **base, u32 *rate)
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
19 {
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
20 struct clk *timer_clk;
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
21 struct clk *pclk;
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
22 struct reset_control *rstc;
5d9814df0aec56 drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2020-12-05
23 int ret;
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
24
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
25 *base = of_iomap(np, 0);
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
26
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
27 if (!*base)
2a4849d2674b96 drivers/clocksource/dw_apb_timer_of.c Rob Herring2018-08-27 28
panic("Unable to map regs for %pOFn", np);
af75655c066621 arch/arm/mach-picoxcell/time.cJamie Iles 2011-07-25
29
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
30 /*
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
31 * Reset the timer if the reset control is available, wiping
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
32 * out the state the firmware may have left it
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
33 */
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
34 rstc = of_reset_control_get(np, NULL);
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
35 if (!IS_ERR(rstc)) {
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
36 reset_control_assert(rstc);
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
37 reset_control_deassert(rstc);
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
38 }
1f174a1a2cdebc drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2018-09-17
39
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
40 /*
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
41 * Not all implementations use a periphal clock, so don't panic
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
42 * if it's not present
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
43 */
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04 44
pclk = of_clk_get_by_name(np, "pclk");
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
45 if (!IS_ERR(pclk))
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
46 if (clk_prepare_enable(pclk))
2a4849d2674b96 drivers/clocksource/dw_apb_timer_of.c Rob Herring2018-08-27 47
pr_warn("pclk for %pOFn is present, but could not be activated\n",
2a4849d2674b96 drivers/clocksource/dw_apb_timer_of.c Rob Herring2018-08-27
48 np);
a8b447f2a7 drivers/clocksource/dw_apb_timer_of.c Heiko Stuebner 2013-06-04
49
5d9814df0aec56 drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2020-12-05 50 if
(!of_property_read_u32(np, "clock-fre
[PATCH RESEND] clocksource: dw_apb_timer_of: add handling for potential memory leak
Add calls to disable the clock and unmap the timer base address in case
of any failures.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index 42e7e43b8fcd..b1e2b697b21b 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -52,18 +52,34 @@ static int __init timer_get_base_and_rate(struct
device_node *np,
return 0;
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- return PTR_ERR(timer_clk);
+ if (IS_ERR(timer_clk)) {
+ ret = PTR_ERR(timer_clk);
+ goto out_pclk_disable;
+ }
ret = clk_prepare_enable(timer_clk);
if (ret)
- return ret;
+ goto out_timer_clk_put;
*rate = clk_get_rate(timer_clk);
- if (!(*rate))
- return -EINVAL;
+ if (!(*rate)) {
+ ret = -EINVAL;
+ goto out_timer_clk_disable;
+ }
return 0;
+
+out_timer_clk_disable:
+ clk_disable_unprepare(timer_clk);
+out_timer_clk_put:
+ clk_put(timer_clk);
+out_pclk_disable:
+ if (!IS_ERR(pclk)) {
+ clk_disable_unprepare(pclk);
+ clk_put(pclk);
+ }
+ iounmap(*base);
+ return ret;
}
static int __init add_clockevent(struct device_node *event_timer)
--
2.25.1
Re: [PATCH] clk: socfpga: fix iomem pointer cast on 64-bit
On 3/11/21 8:48 AM, Krzysztof Kozlowski wrote:
Pointers should be cast to unsigned long instead of integer. This fixes
warning when compile testing on ARM64:
drivers/clk/socfpga/clk-gate.c: In function ‘socfpga_clk_recalc_rate’:
drivers/clk/socfpga/clk-gate.c:102:7: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/socfpga/clk-gate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 43ecd507bf83..c876523d5d51 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -99,7 +99,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw
*hwclk,
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= GENMASK(socfpgaclk->width - 1, 0);
/* Check for GPIO_DB_CLK by its offset */
- if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
+ if ((unsigned long) socfpgaclk->div_reg &
SOCFPGA_GPIO_DB_CLK_OFFSET)
div = val + 1;
else
div = (1 << val);
Acked-by: Dinh Nguyen
[PATCH] arm64: defconfig: add support for Intel's eASIC N5X
Add support for Intel's eASIC N5X platform in the arm64 defconfig. Signed-off-by: Dinh Nguyen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f633b771..f1fffade222e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -45,6 +45,7 @@ CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_MXC=y +CONFIG_ARCH_N5X=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y -- 2.30.0
[PATCH 3/3] clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock
driver to use the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-agilex.c | 114 ++-
drivers/clk/socfpga/clk-gate-s10.c | 15 ++--
drivers/clk/socfpga/clk-periph-s10.c | 42 +-
drivers/clk/socfpga/clk-pll-s10.c| 43 +-
drivers/clk/socfpga/clk-s10.c| 68 +++-
drivers/clk/socfpga/stratix10-clk.h | 24 +++---
6 files changed, 159 insertions(+), 147 deletions(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 7689bdd0a914..319c69112bcf 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -303,18 +303,18 @@ static const struct stratix10_gate_clock
agilex_gate_clks[] = {
static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
int nums, struct stratix10_clock_data
*data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = n5x_register_periph([i], base);
- if (IS_ERR(clk)) {
+ hw_clk = n5x_register_periph([i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
@@ -322,18 +322,18 @@ static int n5x_clk_register_c_perip(const struct
n5x_perip_c_clock *clks,
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock
*clks,
int nums, struct stratix10_clock_data
*data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_periph([i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_periph([i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
@@ -341,18 +341,18 @@ static int agilex_clk_register_c_perip(const struct
stratix10_perip_c_clock *clk
static int agilex_clk_register_cnt_perip(const struct
stratix10_perip_cnt_clock *clks,
int nums, struct stratix10_clock_data
*data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_cnt_periph([i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_cnt_periph([i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
@@ -360,18 +360,18 @@ static int agilex_clk_register_cnt_perip(const struct
stratix10_perip_cnt_clock
static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_gate([i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_gate([i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
@@ -380,18 +380,18 @@ static int agilex_clk_register_gate(const struct
stratix10_gate_clock *clks,
static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- c
[PATCH 1/3] clk: socfpga: use clk_hw_register for a5/c5
As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver
to use the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-gate.c | 11 +++
drivers/clk/socfpga/clk-periph.c | 8
drivers/clk/socfpga/clk-pll.c| 18 +++---
3 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 43ecd507bf83..b17aba5799d2 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -174,13 +174,14 @@ void __init socfpga_gate_init(struct device_node *node)
u32 div_reg[3];
u32 clk_phase[2];
u32 fixed_div;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_ops *ops;
int rc;
+ int err;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
@@ -238,12 +239,14 @@ void __init socfpga_gate_init(struct device_node *node)
init.parent_names = parent_name;
socfpga_clk->hw.hw.init =
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ hw_clk = _clk->hw.hw;
+
+ err = clk_hw_register(NULL, hw_clk);
+ if (err) {
kfree(socfpga_clk);
return;
}
- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
if (WARN_ON(rc))
return;
}
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 5e0c4b45f77f..43707e2d7248 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -51,7 +51,7 @@ static __init void __socfpga_periph_init(struct device_node
*node,
const struct clk_ops *ops)
{
u32 reg;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -94,13 +94,13 @@ static __init void __socfpga_periph_init(struct device_node
*node,
init.parent_names = parent_name;
periph_clk->hw.hw.init =
+ hw_clk = _clk->hw.hw;
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ if (clk_hw_register(NULL, hw_clk)) {
kfree(periph_clk);
return;
}
- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
}
void __init socfpga_periph_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 3cf99df7d005..dcb573d44034 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -70,16 +70,18 @@ static const struct clk_ops clk_pll_ops = {
.get_parent = clk_pll_get_parent,
};
-static __init struct clk *__socfpga_pll_init(struct device_node *node,
+static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
+ int rc;
+ int err;
of_property_read_u32(node, "reg", );
@@ -105,13 +107,15 @@ static __init struct clk *__socfpga_pll_init(struct
device_node *node,
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ hw_clk = _clk->hw.hw;
+
+ err = clk_hw_register(NULL, hw_clk);
+ if (err) {
kfree(pll_clk);
- return NULL;
+ return ERR_PTR(err);
}
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- return clk;
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
+ return hw_clk;
}
void __init socfpga_pll_init(struct device_node *node)
--
2.30.0
[PATCH 2/3] clk: socfpga: arria10: convert to use clk_hw
As recommended by Stephen Boyd, convert the Arria10 clock driver to use
the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-gate-a10.c | 8
drivers/clk/socfpga/clk-periph-a10.c | 11 ++-
drivers/clk/socfpga/clk-pll-a10.c| 12 ++--
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/socfpga/clk-gate-a10.c
b/drivers/clk/socfpga/clk-gate-a10.c
index cd5df9103614..f5cba8298712 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -98,7 +98,7 @@ static void __init __socfpga_gate_init(struct device_node
*node,
u32 div_reg[3];
u32 clk_phase[2];
u32 fixed_div;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -159,13 +159,13 @@ static void __init __socfpga_gate_init(struct device_node
*node,
init.num_parents = of_clk_parent_fill(node, parent_name,
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
socfpga_clk->hw.hw.init =
+ hw_clk = _clk->hw.hw;
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ if (clk_hw_register(NULL, hw_clk)) {
kfree(socfpga_clk);
return;
}
- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
if (WARN_ON(rc))
return;
}
diff --git a/drivers/clk/socfpga/clk-periph-a10.c
b/drivers/clk/socfpga/clk-periph-a10.c
index 3e0c55727b89..b9cdde4b8441 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -61,7 +61,7 @@ static __init void __socfpga_periph_init(struct device_node
*node,
const struct clk_ops *ops)
{
u32 reg;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -104,12 +104,13 @@ static __init void __socfpga_periph_init(struct
device_node *node,
periph_clk->hw.hw.init =
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ hw_clk = _clk->hw.hw;
+
+ if (clk_hw_register(NULL, hw_clk)) {
kfree(periph_clk);
return;
}
- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
if (rc < 0) {
pr_err("Could not register clock provider for node:%s\n",
clk_name);
@@ -119,7 +120,7 @@ static __init void __socfpga_periph_init(struct device_node
*node,
return;
err_clk:
- clk_unregister(clk);
+ clk_hw_unregister(hw_clk);
}
void __init socfpga_a10_periph_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c
b/drivers/clk/socfpga/clk-pll-a10.c
index 3338f054fe98..bee0f7da5b6e 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -63,11 +63,11 @@ static const struct clk_ops clk_pll_ops = {
.get_parent = clk_pll_get_parent,
};
-static struct clk * __init __socfpga_pll_init(struct device_node *node,
+static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFGPA_MAX_PARENTS];
@@ -101,14 +101,14 @@ static struct clk * __init __socfpga_pll_init(struct
device_node *node,
pll_clk->hw.hw.init =
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
+ hw_clk = _clk->hw.hw;
- clk = clk_register(NULL, _clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ if (clk_hw_register(NULL, hw_clk)) {
kfree(pll_clk);
return NULL;
}
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- return clk;
+ of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
+ return hw_clk;
}
void __init socfpga_a10_pll_init(struct device_node *node)
--
2.30.0
[PATCH] clocksource: dw_apb_timer_of: add handling for potential memory leak
Add calls to disable the clock and unmap the timer base address in case
of any failures.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index 42e7e43b8fcd..b1e2b697b21b 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -52,18 +52,34 @@ static int __init timer_get_base_and_rate(struct
device_node *np,
return 0;
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- return PTR_ERR(timer_clk);
+ if (IS_ERR(timer_clk)) {
+ ret = PTR_ERR(timer_clk);
+ goto out_pclk_disable;
+ }
ret = clk_prepare_enable(timer_clk);
if (ret)
- return ret;
+ goto out_timer_clk_put;
*rate = clk_get_rate(timer_clk);
- if (!(*rate))
- return -EINVAL;
+ if (!(*rate)) {
+ ret = -EINVAL;
+ goto out_timer_clk_disable;
+ }
return 0;
+
+out_timer_clk_disable:
+ clk_disable_unprepare(timer_clk);
+out_timer_clk_put:
+ clk_put(timer_clk);
+out_pclk_disable:
+ if (!IS_ERR(pclk)) {
+ clk_disable_unprepare(pclk);
+ clk_put(pclk);
+ }
+ iounmap(*base);
+ return ret;
}
static int __init add_clockevent(struct device_node *event_timer)
--
2.30.0
Re: [PATCH] clk: socfpga: agilex: add clock driver for eASIC N5X platform
On 2/10/21 9:05 PM, Stephen Boyd wrote:
Quoting Dinh Nguyen (2021-01-05 11:29:56)
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen
---
Sorry this patch fell off my radar.
I ran checkpatch
WARNING: function definition argument 'struct platform_device *' should also
have an identifier name
#135: FILE: drivers/clk/socfpga/clk-agilex.c:500:
+ int (*probe_func)(struct platform_device *);
WARNING: Statements terminations use 1 semicolon
#140: FILE: drivers/clk/socfpga/clk-agilex.c:505:
+ return probe_func(pdev);;
WARNING: DT compatible string "intel,n5x-clkmgr" appears un-documented -- check
./Documentation/devicetree/bindings/
#147: FILE: drivers/clk/socfpga/clk-agilex.c:511:
+ { .compatible = "intel,n5x-clkmgr",
WARNING: struct clk_ops should normally be const
#290: FILE: drivers/clk/socfpga/clk-pll-s10.c:166:
+static struct clk_ops n5x_clk_pll_ops = {
WARNING: struct clk_ops should normally be const
#296: FILE: drivers/clk/socfpga/clk-pll-s10.c:172:
+static struct clk_ops agilex_clk_pll_ops = {
WARNING: function definition argument 'const struct stratix10_pll_clock *'
should also have an identifier name
#367: FILE: drivers/clk/socfpga/stratix10-clk.h:78:
+struct clk *n5x_register_pll(const struct stratix10_pll_clock *,
WARNING: function definition argument 'void __iomem *' should also have an
identifier name
#367: FILE: drivers/clk/socfpga/stratix10-clk.h:78:
+struct clk *n5x_register_pll(const struct stratix10_pll_clock *,
WARNING: function definition argument 'const struct n5x_perip_c_clock *' should
also have an identifier name
#371: FILE: drivers/clk/socfpga/stratix10-clk.h:82:
+struct clk *n5x_register_periph(const struct n5x_perip_c_clock *,
WARNING: function definition argument 'void __iomem *' should also have an
identifier name
#371: FILE: drivers/clk/socfpga/stratix10-clk.h:82:
+struct clk *n5x_register_periph(const struct n5x_perip_c_clock *,
Can you fix these up and resend?
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-s10.c | 53 +
drivers/clk/socfpga/clk-pll-s10.c| 85 ++-
drivers/clk/socfpga/stratix10-clk.h | 15 +
4 files changed, 238 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/socfpga/clk-periph-s10.c
b/drivers/clk/socfpga/clk-periph-s10.c
index 397b77b89b16..135581c41c05 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -15,6 +15,21 @@
#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
+static unsigned long n5x_clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
+unsigned long parent_rate)
+{
+ struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
+ unsigned long div;
+ unsigned long shift = socfpgaclk->shift;
+ u32 val;
+
+ val = readl(socfpgaclk->hw.reg);
+ val &= (0x1F << shift);
Prefer lowercase hex.
+ div = (val >> shift) + 1;
+
+ return parent_rate / div;
+}
+
static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
@@ -63,6 +78,11 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
return parent;
}
+static const struct clk_ops n5x_peri_c_clk_ops = {
+ .recalc_rate = n5x_clk_peri_c_clk_recalc_rate,
+ .get_parent = clk_periclk_get_parent,
+};
+
static const struct clk_ops peri_c_clk_ops = {
.recalc_rate = clk_peri_c_clk_recalc_rate,
.get_parent = clk_periclk_get_parent,
@@ -107,6 +127,39 @@ struct clk *s10_register_periph(const struct
stratix10_perip_c_clock *clks,
return clk;
}
+struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
+ void __iomem *regbase)
+{
+ struct clk *clk;
+ struct socfpga_periph_clk *periph_clk;
+ struct clk_init_data init;
+ const char *name = clks->name;
+ const char *parent_name = clks->parent_name;
+
+ periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
+ if (WARN_ON(!periph_clk))
+ return NULL;
+
+ periph_clk->hw.reg = regbase + clks->offset;
+ periph_clk->shift = clks->shift;
+
+ init.name = name;
+ init.ops = _peri_c_clk_ops;
+ init.flags = clks->flags;
+
+ init.num_parents = clks->num_parents;
+ init.parent_names = parent_name ? _name : NULL;
+
+ periph_clk->hw.hw.init =
+
+ clk = clk_register(NULL, _clk->hw.hw);
Can you use clk_hw_register?
Thanks for the re
[PATCHv1 1/2] dt-bindings: documentation: add clock bindings information for eASIC N5X
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the eASIC
N5X platform.
Signed-off-by: Dinh Nguyen
---
.../bindings/clock/intel,easic-n5x.yaml | 46 +++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
diff --git a/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
b/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
new file mode 100644
index ..8f45976e946e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA eASIC N5X platform clock controller binding
+
+maintainers:
+ - Dinh Nguyen
+
+description:
+ The Intel eASIC N5X Clock controller is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+const: intel,easic-n5x-clkmgr
+
+ '#clock-cells':
+const: 1
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock controller node:
+ - |
+clkmgr: clock-controller@ffd1 {
+ compatible = "intel,easic-n5x-clkmgr";
+ reg = <0xffd1 0x1000>;
+ clocks = <>;
+ #clock-cells = <1>;
+};
+...
--
2.30.0
[PATCHv2 2/2] clk: socfpga: agilex: add clock driver for eASIC N5X platform
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen
---
v2: use "intel,easic-n5x-clkmgr" binding
correct the pll prepare function
Address Stephen's comments
Add a binding documentation
---
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-s10.c | 53 +
drivers/clk/socfpga/clk-pll-s10.c| 83 ++
drivers/clk/socfpga/stratix10-clk.h | 17 +-
4 files changed, 238 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index bb3e80928ebe..7689bdd0a914 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -196,6 +196,17 @@ static const struct stratix10_pll_clock agilex_pll_clks[]
= {
0, 0x9c},
};
+static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
+ { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54,
0},
+ { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54,
8},
+ { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54,
16},
+ { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54,
24},
+ { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
0xA8, 0},
+ { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
0xA8, 8},
+ { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
0xA8, 16},
+ { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
0xA8, 24},
+};
+
static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
@@ -289,6 +300,25 @@ static const struct stratix10_gate_clock
agilex_gate_clks[] = {
10, 0, 0, 0, 0, 0, 4},
};
+static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
+ int nums, struct stratix10_clock_data
*data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_periph([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+ return 0;
+}
+
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock
*clks,
int nums, struct stratix10_clock_data
*data)
{
@@ -367,6 +397,26 @@ static int agilex_clk_register_pll(const struct
stratix10_pll_clock *clks,
return 0;
}
+static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
+int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_pll([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct
platform_device *pdev,
int nr_clks)
{
@@ -401,7 +451,7 @@ static struct stratix10_clock_data
*__socfpga_agilex_clk_init(struct platform_de
return clk_data;
}
-static int agilex_clkmgr_probe(struct platform_device *pdev)
+static int agilex_clkmgr_init(struct platform_device *pdev)
{
struct stratix10_clock_data *clk_data;
@@ -423,9 +473,43 @@ static int agilex_clkmgr_probe(struct platform_device
*pdev)
return 0;
}
+static int n5x_clkmgr_init(struct platform_device *pdev)
+{
+ struct stratix10_clock_data *clk_data;
+
+ clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
+ if (IS_ERR(clk_data))
+ return PTR_ERR(clk_data);
+
+ n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
clk_data);
+
+ n5x_clk_register_c_perip(n5x_main_perip_c_clks,
+
Re: [PATCH 08/20] clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'
On 1/20/21 3:30 AM, Lee Jones wrote: Fixes the following W=1 kernel build warning(s): drivers/clk/socfpga/clk-pll-a10.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll-a10.c:76:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Cc: Dinh Nguyen Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-...@vger.kernel.org Signed-off-by: Lee Jones --- drivers/clk/socfpga/clk-pll-a10.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index db54f7d806a09..3338f054fe98c 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -73,7 +73,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, const char *parent_name[SOCFGPA_MAX_PARENTS]; struct clk_init_data init; struct device_node *clkmgr_np; - int rc; int i = 0; of_property_read_u32(node, "reg", ); @@ -108,7 +107,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, kfree(pll_clk); return NULL; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + of_clk_add_provider(node, of_clk_src_simple_get, clk); return clk; } Acked-by: Dinh Nguyen
Re: [PATCH 07/20] clk: socfpga: clk-pll: Remove unused variable 'rc'
On 1/20/21 3:30 AM, Lee Jones wrote: Fixes the following W=1 kernel build warning(s): drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Cc: Dinh Nguyen Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-...@vger.kernel.org Signed-off-by: Lee Jones --- drivers/clk/socfpga/clk-pll.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index e5fb786843f39..3cf99df7d0056 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -80,7 +80,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, const char *parent_name[SOCFPGA_MAX_PARENTS]; struct clk_init_data init; struct device_node *clkmgr_np; - int rc; of_property_read_u32(node, "reg", ); @@ -111,7 +110,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, kfree(pll_clk); return NULL; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); + of_clk_add_provider(node, of_clk_src_simple_get, clk); return clk; } Acked-by: Dinh Nguyen
Re: [PATCH] clk: socfpga: agilex: add clock driver for eASIC N5X platform
Hi Stephen/Mike,
Was wondering if you had a chance to review this patch?
Thanks,
Dinh
On 1/5/21 1:29 PM, Dinh Nguyen wrote:
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-s10.c | 53 +
drivers/clk/socfpga/clk-pll-s10.c| 85 ++-
drivers/clk/socfpga/stratix10-clk.h | 15 +
4 files changed, 238 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index bb3e80928ebe..f9394ed8a41d 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -196,6 +196,17 @@ static const struct stratix10_pll_clock agilex_pll_clks[]
= {
0, 0x9c},
};
+static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
+ { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54,
0},
+ { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54,
8},
+ { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54,
16},
+ { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54,
24},
+ { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
0xA8, 0},
+ { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
0xA8, 8},
+ { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
0xA8, 16},
+ { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
0xA8, 24},
+};
+
static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
@@ -289,6 +300,25 @@ static const struct stratix10_gate_clock
agilex_gate_clks[] = {
10, 0, 0, 0, 0, 0, 4},
};
+static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
+ int nums, struct stratix10_clock_data
*data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_periph([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+ return 0;
+}
+
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock
*clks,
int nums, struct stratix10_clock_data
*data)
{
@@ -367,6 +397,26 @@ static int agilex_clk_register_pll(const struct
stratix10_pll_clock *clks,
return 0;
}
+static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
+int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_pll([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct
platform_device *pdev,
int nr_clks)
{
@@ -401,7 +451,7 @@ static struct stratix10_clock_data
*__socfpga_agilex_clk_init(struct platform_de
return clk_data;
}
-static int agilex_clkmgr_probe(struct platform_device *pdev)
+static int agilex_clkmgr_init(struct platform_device *pdev)
{
struct stratix10_clock_data *clk_data;
@@ -423,9 +473,43 @@ static int agilex_clkmgr_probe(struct platform_device *pdev)
return 0;
}
+static int n5x_clkmgr_init(struct platform_device *pdev)
+{
+ struct stratix10_clock_data *clk_data;
+
+ clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
+ if (IS_ERR(clk_data))
+ return PTR_ERR(clk_data);
+
+ n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
clk_data);
+
+ n5x_clk_register_c_perip(n5x_
Re: commit ("1e860048c53ee gcc-plugins: simplify GCC plugin-dev capability test")
On 1/6/21 5:14 PM, Kees Cook wrote:
On Wed, Jan 06, 2021 at 08:44:58AM -0600, Dinh Nguyen wrote:
Hi Masahiro,
With v5.11-rc1 and commit("1e860048c53ee gcc-plugins: simplify GCC
plugin-dev capability test"), I get this error for my arm socfpga_defconfig
build. I have been building the kernel the same way for many years now. Do
you know what I might be doing wrong?
$ make ARCH=arm CROSS_COMPILE=${CROSS_COMPILE}
SYNCinclude/config/auto.conf.cmd
SYSHDR arch/arm/include/generated/uapi/asm/unistd-common.h
SYSHDR arch/arm/include/generated/uapi/asm/unistd-oabi.h
SYSHDR arch/arm/include/generated/uapi/asm/unistd-eabi.h
REMOVE arch/arm/include/generated/asm/mm-arch-hooks.h
HOSTCXX scripts/gcc-plugins/arm_ssp_per_task_plugin.so
In file included from scripts/gcc-plugins/gcc-common.h:103:0,
from scripts/gcc-plugins/arm_ssp_per_task_plugin.c:3:
/home/dinguyen/linux_dev/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/bin/../lib/gcc/arm-none-linux-gnueabihf/10.2.1/plugin/include/builtins.h:23:10:
fatal error: mpc.h: No such file or directory
#include
^~~
compilation terminated.
scripts/gcc-plugins/Makefile:47: recipe for target
'scripts/gcc-plugins/arm_ssp_per_task_plugin.so' failed
make[2]: *** [scripts/gcc-plugins/arm_ssp_per_task_plugin.so] Error 1
scripts/Makefile.build:496: recipe for target 'scripts/gcc-plugins' failed
make[1]: *** [scripts/gcc-plugins] Error 2
Makefile:1190: recipe for target 'scripts' failed
make: *** [scripts] Error 2
make: *** Waiting for unfinished jobs
UPD include/config/kernel.release
Thanks,
Dinh
Hi! Thanks for the report. Other folks have also encountered this,
and it appears to be a problem with distro packaging of the gcc plugin
development packages. You'll need to install the GNU multiprecision
libraries ("gmp-devel" on most rpm-based systems, "libgmp-dev" on most
debian systems)[1].
Hopefully that'll work!
Thanks, that worked! I also had to install libmpc-dev as well.
Dinh
commit ("1e860048c53ee gcc-plugins: simplify GCC plugin-dev capability test")
Hi Masahiro,
With v5.11-rc1 and commit("1e860048c53ee gcc-plugins: simplify GCC
plugin-dev capability test"), I get this error for my arm
socfpga_defconfig build. I have been building the kernel the same way
for many years now. Do you know what I might be doing wrong?
$ make ARCH=arm CROSS_COMPILE=${CROSS_COMPILE}
SYNCinclude/config/auto.conf.cmd
SYSHDR arch/arm/include/generated/uapi/asm/unistd-common.h
SYSHDR arch/arm/include/generated/uapi/asm/unistd-oabi.h
SYSHDR arch/arm/include/generated/uapi/asm/unistd-eabi.h
REMOVE arch/arm/include/generated/asm/mm-arch-hooks.h
HOSTCXX scripts/gcc-plugins/arm_ssp_per_task_plugin.so
In file included from scripts/gcc-plugins/gcc-common.h:103:0,
from scripts/gcc-plugins/arm_ssp_per_task_plugin.c:3:
/home/dinguyen/linux_dev/gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/bin/../lib/gcc/arm-none-linux-gnueabihf/10.2.1/plugin/include/builtins.h:23:10:
fatal error: mpc.h: No such file or directory
#include
^~~
compilation terminated.
scripts/gcc-plugins/Makefile:47: recipe for target
'scripts/gcc-plugins/arm_ssp_per_task_plugin.so' failed
make[2]: *** [scripts/gcc-plugins/arm_ssp_per_task_plugin.so] Error 1
scripts/Makefile.build:496: recipe for target 'scripts/gcc-plugins' failed
make[1]: *** [scripts/gcc-plugins] Error 2
Makefile:1190: recipe for target 'scripts' failed
make: *** [scripts] Error 2
make: *** Waiting for unfinished jobs
UPD include/config/kernel.release
Thanks,
Dinh
[PATCH] clk: socfpga: agilex: add clock driver for eASIC N5X platform
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-s10.c | 53 +
drivers/clk/socfpga/clk-pll-s10.c| 85 ++-
drivers/clk/socfpga/stratix10-clk.h | 15 +
4 files changed, 238 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index bb3e80928ebe..f9394ed8a41d 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -196,6 +196,17 @@ static const struct stratix10_pll_clock agilex_pll_clks[]
= {
0, 0x9c},
};
+static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
+ { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54,
0},
+ { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54,
8},
+ { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54,
16},
+ { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54,
24},
+ { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0,
0xA8, 0},
+ { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0,
0xA8, 8},
+ { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0,
0xA8, 16},
+ { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0,
0xA8, 24},
+};
+
static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
@@ -289,6 +300,25 @@ static const struct stratix10_gate_clock
agilex_gate_clks[] = {
10, 0, 0, 0, 0, 0, 4},
};
+static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
+ int nums, struct stratix10_clock_data
*data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_periph([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+ return 0;
+}
+
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock
*clks,
int nums, struct stratix10_clock_data
*data)
{
@@ -367,6 +397,26 @@ static int agilex_clk_register_pll(const struct
stratix10_pll_clock *clks,
return 0;
}
+static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
+int nums, struct stratix10_clock_data *data)
+{
+ struct clk *clk;
+ void __iomem *base = data->base;
+ int i;
+
+ for (i = 0; i < nums; i++) {
+ clk = n5x_register_pll([i], base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s\n",
+ __func__, clks[i].name);
+ continue;
+ }
+ data->clk_data.clks[clks[i].id] = clk;
+ }
+
+ return 0;
+}
+
static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct
platform_device *pdev,
int nr_clks)
{
@@ -401,7 +451,7 @@ static struct stratix10_clock_data
*__socfpga_agilex_clk_init(struct platform_de
return clk_data;
}
-static int agilex_clkmgr_probe(struct platform_device *pdev)
+static int agilex_clkmgr_init(struct platform_device *pdev)
{
struct stratix10_clock_data *clk_data;
@@ -423,9 +473,43 @@ static int agilex_clkmgr_probe(struct platform_device
*pdev)
return 0;
}
+static int n5x_clkmgr_init(struct platform_device *pdev)
+{
+ struct stratix10_clock_data *clk_data;
+
+ clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
+ if (IS_ERR(clk_data))
+ return PTR_ERR(clk_data);
+
+ n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks),
clk_data);
+
+ n5x_clk_register_c_perip(n5x_main_perip_c_clks,
+ARRAY_SIZE(n5x_main_perip_c_clks), clk_data);
+
+ agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
+
[PATCH] arm64: dts: n5x: Add support for Intel's eASIC N5X platform
The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.
Signed-off-by: Dinh Nguyen
---
arch/arm64/Kconfig.platforms | 5 ++
arch/arm64/boot/dts/intel/Makefile| 1 +
.../boot/dts/intel/socfpga_n5x_socdk.dts | 53 +++
3 files changed, 59 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6eecdef538bd..c20eacd9a931 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -13,6 +13,11 @@ config ARCH_AGILEX
help
This enables support for Intel's Agilex SoCFPGA Family.
+config ARCH_N5X
+ bool "Intel's eASIC N5X SoCFPGA Family"
+ help
+ This enables support for Intel's eASIC N5X SoCFPGA Family.
+
config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/arch/arm64/boot/dts/intel/Makefile
b/arch/arm64/boot/dts/intel/Makefile
index 296eceec4276..3a052540605b 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -2,3 +2,4 @@
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
+dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
new file mode 100644
index ..5f56e2697fee
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "eASIC N5X SoCDK";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ ethernet1 =
+ ethernet2 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <2500>;
+ };
+ };
+ };
+};
+
+ {
+ compatible = "intel,easic-n5x-clkmgr";
+};
+
+ {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
--
2.30.0
Re: [PATCH 8/8] ARM: dts: socfgpa: Use generic "ngpios" rather than "snps,nr-gpios"
On 11/9/20 3:07 AM, Jisheng Zhang wrote:
This is to remove similar errors as below:
OF: /.../gpio-port@0: could not find phandle
Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use it.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/socfpga.dtsi | 6 +++---
arch/arm/boot/dts/socfpga_arria10.dtsi | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0b021eef0b53..32b7ad814ec6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -612,7 +612,7 @@ porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <29>;
+ ngpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -633,7 +633,7 @@ portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <29>;
+ ngpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -654,7 +654,7 @@ portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <27>;
+ ngpios = <27>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 0013ec3463c4..34e23e0582fb 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -491,7 +491,7 @@ porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <29>;
+ ngpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -511,7 +511,7 @@ portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <29>;
+ ngpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -531,7 +531,7 @@ portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
- snps,nr-gpios = <27>;
+ ngpios = <27>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
Applied to socfpga dts tree.
Thanks,
Dinh
[tip: timers/core] clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 5d9814df0aec56a638bbf20795abb4cfaf3cd331
Gitweb:
https://git.kernel.org/tip/5d9814df0aec56a638bbf20795abb4cfaf3cd331
Author:Dinh Nguyen
AuthorDate:Sat, 05 Dec 2020 04:52:23 -06:00
Committer: Daniel Lezcano
CommitterDate: Sat, 05 Dec 2020 19:33:55 +01:00
clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get loaded until after the timer driver get loaded. Thus, the driver hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
Signed-off-by: Daniel Lezcano
Link: https://lore.kernel.org/r/20201205105223.208604-1-dingu...@kernel.org
---
drivers/clocksource/dw_apb_timer_of.c | 57 +-
1 file changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index ab3ddeb..42e7e43 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -14,12 +14,13 @@
#include
#include
-static void __init timer_get_base_and_rate(struct device_node *np,
+static int __init timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
struct clk *timer_clk;
struct clk *pclk;
struct reset_control *rstc;
+ int ret;
*base = of_iomap(np, 0);
@@ -46,55 +47,67 @@ static void __init timer_get_base_and_rate(struct
device_node *np,
pr_warn("pclk for %pOFn is present, but could not be
activated\n",
np);
+ if (!of_property_read_u32(np, "clock-freq", rate) &&
+ !of_property_read_u32(np, "clock-frequency", rate))
+ return 0;
+
timer_clk = of_clk_get_by_name(np, "timer");
if (IS_ERR(timer_clk))
- goto try_clock_freq;
+ return PTR_ERR(timer_clk);
- if (!clk_prepare_enable(timer_clk)) {
- *rate = clk_get_rate(timer_clk);
- return;
- }
+ ret = clk_prepare_enable(timer_clk);
+ if (ret)
+ return ret;
+
+ *rate = clk_get_rate(timer_clk);
+ if (!(*rate))
+ return -EINVAL;
-try_clock_freq:
- if (of_property_read_u32(np, "clock-freq", rate) &&
- of_property_read_u32(np, "clock-frequency", rate))
- panic("No clock nor clock-frequency property for %pOFn", np);
+ return 0;
}
-static void __init add_clockevent(struct device_node *event_timer)
+static int __init add_clockevent(struct device_node *event_timer)
{
void __iomem *iobase;
struct dw_apb_clock_event_device *ced;
u32 irq, rate;
+ int ret = 0;
irq = irq_of_parse_and_map(event_timer, 0);
if (irq == 0)
panic("No IRQ for clock event timer");
- timer_get_base_and_rate(event_timer, , );
+ ret = timer_get_base_and_rate(event_timer, , );
+ if (ret)
+ return ret;
ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
rate);
if (!ced)
- panic("Unable to initialise clockevent device");
+ return -EINVAL;
dw_apb_clockevent_register(ced);
+
+ return 0;
}
static void __iomem *sched_io_base;
static u32 sched_rate;
-static void __init add_clocksource(struct device_node *source_timer)
+static int __init add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
struct dw_apb_clocksource *cs;
u32 rate;
+ int ret;
- timer_get_base_and_rate(source_timer, , );
+ ret = timer_get_base_and_rate(source_timer, , );
+ if (ret)
+ return ret;
cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
if (!cs)
- panic("Unable to initialise clocksource device");
+ return -EINVAL;
dw_apb_clocksource_start(cs);
dw_apb_clocksource_register(cs);
@@ -106,6 +119,8 @@ static void __init add_clocksource(struct device_node
*source_timer)
*/
sched_io_base = iobase + 0x04;
sched_rate = rate;
+
+ return 0;
}
static u64 notrace read_sched_clock(void)
@@ -146,10 +161,14 @@ static struct delay_timer dw_apb_delay_timer = {
static int num_
[PATCHv3] clocksource: dw_apb_timer_of: add error handling if no clock available
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get loaded until after the timer driver get loaded. Thus, the driver hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
---
v3: check for IS_ERR(timer_clk) in timer_get_base_and_rate
v2: address comments from Daniel Lezcano
update commit message
---
drivers/clocksource/dw_apb_timer_of.c | 57 ++-
1 file changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index ab3ddebe8344..42e7e43b8fcd 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -14,12 +14,13 @@
#include
#include
-static void __init timer_get_base_and_rate(struct device_node *np,
+static int __init timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
struct clk *timer_clk;
struct clk *pclk;
struct reset_control *rstc;
+ int ret;
*base = of_iomap(np, 0);
@@ -46,55 +47,67 @@ static void __init timer_get_base_and_rate(struct
device_node *np,
pr_warn("pclk for %pOFn is present, but could not be
activated\n",
np);
+ if (!of_property_read_u32(np, "clock-freq", rate) &&
+ !of_property_read_u32(np, "clock-frequency", rate))
+ return 0;
+
timer_clk = of_clk_get_by_name(np, "timer");
if (IS_ERR(timer_clk))
- goto try_clock_freq;
+ return PTR_ERR(timer_clk);
- if (!clk_prepare_enable(timer_clk)) {
- *rate = clk_get_rate(timer_clk);
- return;
- }
+ ret = clk_prepare_enable(timer_clk);
+ if (ret)
+ return ret;
+
+ *rate = clk_get_rate(timer_clk);
+ if (!(*rate))
+ return -EINVAL;
-try_clock_freq:
- if (of_property_read_u32(np, "clock-freq", rate) &&
- of_property_read_u32(np, "clock-frequency", rate))
- panic("No clock nor clock-frequency property for %pOFn", np);
+ return 0;
}
-static void __init add_clockevent(struct device_node *event_timer)
+static int __init add_clockevent(struct device_node *event_timer)
{
void __iomem *iobase;
struct dw_apb_clock_event_device *ced;
u32 irq, rate;
+ int ret = 0;
irq = irq_of_parse_and_map(event_timer, 0);
if (irq == 0)
panic("No IRQ for clock event timer");
- timer_get_base_and_rate(event_timer, , );
+ ret = timer_get_base_and_rate(event_timer, , );
+ if (ret)
+ return ret;
ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
rate);
if (!ced)
- panic("Unable to initialise clockevent device");
+ return -EINVAL;
dw_apb_clockevent_register(ced);
+
+ return 0;
}
static void __iomem *sched_io_base;
static u32 sched_rate;
-static void __init add_clocksource(struct device_node *source_timer)
+static int __init add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
struct dw_apb_clocksource *cs;
u32 rate;
+ int ret;
- timer_get_base_and_rate(source_timer, , );
+ ret = timer_get_base_and_rate(source_timer, , );
+ if (ret)
+ return ret;
cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
if (!cs)
- panic("Unable to initialise clocksource device");
+ return -EINVAL;
dw_apb_clocksource_start(cs);
dw_apb_clocksource_register(cs);
@@ -106,6 +119,8 @@ static void __init add_clocksource(struct device_node
*source_timer)
*/
sched_io_base = iobase + 0x04;
sched_rate = rate;
+
+ return 0;
}
static u64 notrace read_sched_clock(void)
@@ -146,10 +161,14 @@ static struct delay_timer dw_apb_delay_timer = {
static int num_called;
static int __init dw_apb_timer_init(struct device_node *timer)
{
+ int ret = 0;
+
switch (num_called) {
case 1:
pr_debug("%s: found clocksource timer\n", __func__);
- add_clocksource(timer);
+ ret = add_clocksource(timer);
+ if (ret)
+ return ret;
init_sched_clock();
#i
Re: [PATCHv2] clocksource: dw_apb_timer_of: add error handling if no clock available
Hi Daniel,
On 12/5/20 2:50 AM, Daniel Lezcano wrote:
On 04/12/2020 23:39, Dinh Nguyen wrote:
On 12/4/20 2:00 PM, Daniel Lezcano wrote:
On 04/12/2020 16:36, Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get loaded until after the timer driver get loaded. Thus, the driver
hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
Did you have time to test the different combinations ?
I did test both versions and did not see any difference between the two.
On both versions, the kernel was able to continue to boot after trying
to probe the timer driver.
Great, thanks!
I forgot to test this on ARM 32-bit system that actually uses one of
these timers as a clocksource. The v2 patch would fail. The return of
PTR_ERR(timer_clk) needs an IS_ERR(timer_clk) check.
I have sent a v3.
Sorry about that.
Dinh
Re: [PATCHv2] clocksource: dw_apb_timer_of: add error handling if no clock available
On 12/4/20 2:00 PM, Daniel Lezcano wrote:
On 04/12/2020 16:36, Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get loaded until after the timer driver get loaded. Thus, the driver hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
Did you have time to test the different combinations ?
I did test both versions and did not see any difference between the two.
On both versions, the kernel was able to continue to boot after trying
to probe the timer driver.
Dinh
[PATCHv2] clocksource: dw_apb_timer_of: add error handling if no clock available
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get loaded until after the timer driver get loaded. Thus, the driver hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
---
v2: address comments from Daniel Lezcano
update commit message
---
drivers/clocksource/dw_apb_timer_of.c | 60 ++-
1 file changed, 41 insertions(+), 19 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index ab3ddebe8344..809f4c9327f9 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -14,12 +14,13 @@
#include
#include
-static void __init timer_get_base_and_rate(struct device_node *np,
+static int __init timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
struct clk *timer_clk;
struct clk *pclk;
struct reset_control *rstc;
+ int ret;
*base = of_iomap(np, 0);
@@ -46,55 +47,68 @@ static void __init timer_get_base_and_rate(struct
device_node *np,
pr_warn("pclk for %pOFn is present, but could not be
activated\n",
np);
+ if (!of_property_read_u32(np, "clock-freq", rate) &&
+ !of_property_read_u32(np, "clock-frequency", rate))
+ return 0;
+
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- goto try_clock_freq;
+ ret = PTR_ERR(timer_clk);
+ if (ret)
+ return ret;
- if (!clk_prepare_enable(timer_clk)) {
- *rate = clk_get_rate(timer_clk);
- return;
- }
+ ret = clk_prepare_enable(timer_clk);
+ if (ret)
+ return ret;
+
+ *rate = clk_get_rate(timer_clk);
+ if (!(*rate))
+ return -EINVAL;
-try_clock_freq:
- if (of_property_read_u32(np, "clock-freq", rate) &&
- of_property_read_u32(np, "clock-frequency", rate))
- panic("No clock nor clock-frequency property for %pOFn", np);
+ return 0;
}
-static void __init add_clockevent(struct device_node *event_timer)
+static int __init add_clockevent(struct device_node *event_timer)
{
void __iomem *iobase;
struct dw_apb_clock_event_device *ced;
u32 irq, rate;
+ int ret = 0;
irq = irq_of_parse_and_map(event_timer, 0);
if (irq == 0)
panic("No IRQ for clock event timer");
- timer_get_base_and_rate(event_timer, , );
+ ret = timer_get_base_and_rate(event_timer, , );
+ if (ret)
+ return ret;
ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
rate);
if (!ced)
- panic("Unable to initialise clockevent device");
+ return -EINVAL;
dw_apb_clockevent_register(ced);
+
+ return 0;
}
static void __iomem *sched_io_base;
static u32 sched_rate;
-static void __init add_clocksource(struct device_node *source_timer)
+static int __init add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
struct dw_apb_clocksource *cs;
u32 rate;
+ int ret;
- timer_get_base_and_rate(source_timer, , );
+ ret = timer_get_base_and_rate(source_timer, , );
+ if (ret)
+ return ret;
cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
if (!cs)
- panic("Unable to initialise clocksource device");
+ return -EINVAL;
dw_apb_clocksource_start(cs);
dw_apb_clocksource_register(cs);
@@ -106,6 +120,8 @@ static void __init add_clocksource(struct device_node
*source_timer)
*/
sched_io_base = iobase + 0x04;
sched_rate = rate;
+
+ return 0;
}
static u64 notrace read_sched_clock(void)
@@ -146,10 +162,14 @@ static struct delay_timer dw_apb_delay_timer = {
static int num_called;
static int __init dw_apb_timer_init(struct device_node *timer)
{
+ int ret = 0;
+
switch (num_called) {
case 1:
pr_debug("%s: found clocksource timer\n", __func__);
- add_clocksource(timer);
+ ret = add_clocksource(timer);
+ if (ret)
+ return ret;
init_sched_clock();
#ifdef CONFIG_ARM
Re: [PATCH] clocksource: dw_apb_timer_of: return EPROBE_DEFER if no clock available
Gentle ping?
On 11/20/20 4:02 AM, Jisheng Zhang wrote:
On Thu, 19 Nov 2020 06:12:25 -0600
Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get probed until after the timer driver is probed. Thus, the driver hits
the panic "No clock nor clock-frequency property for %" because it cannot
properly get the clock.
This patch adds support for EPROBE_DEFER so the kernel can come back to
finish probing this timer driver after the clock driver is probed.
Signed-off-by: Dinh Nguyen
Reviewed-by: Jisheng Zhang
---
drivers/clocksource/dw_apb_timer_of.c | 86 ---
1 file changed, 51 insertions(+), 35 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index ab3ddebe8344..a8ce980c5146 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -14,7 +14,7 @@
#include
#include
-static void __init timer_get_base_and_rate(struct device_node *np,
+static int __init timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
struct clk *timer_clk;
@@ -47,65 +47,77 @@ static void __init timer_get_base_and_rate(struct
device_node *np,
np);
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- goto try_clock_freq;
+ if (IS_ERR(timer_clk)) {
+ if (PTR_ERR(timer_clk) != -EPROBE_DEFER) {
+ pr_err("Failed to get clock for %pOF\n", np);
+ goto try_clock_freq;
+ }
+ return PTR_ERR(timer_clk);
+ }
if (!clk_prepare_enable(timer_clk)) {
*rate = clk_get_rate(timer_clk);
- return;
+ return 0;
}
try_clock_freq:
if (of_property_read_u32(np, "clock-freq", rate) &&
of_property_read_u32(np, "clock-frequency", rate))
panic("No clock nor clock-frequency property for %pOFn", np);
+ return 0;
}
-static void __init add_clockevent(struct device_node *event_timer)
+static int __init add_clockevent(struct device_node *event_timer)
{
void __iomem *iobase;
struct dw_apb_clock_event_device *ced;
u32 irq, rate;
+ int ret = 0;
irq = irq_of_parse_and_map(event_timer, 0);
if (irq == 0)
panic("No IRQ for clock event timer");
- timer_get_base_and_rate(event_timer, , );
-
- ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
+ ret = timer_get_base_and_rate(event_timer, , );
+ if (ret == 0) {
+ ced = dw_apb_clockevent_init(-1, event_timer->name, 300,
iobase, irq,
rate);
- if (!ced)
- panic("Unable to initialise clockevent device");
+ if (!ced)
+ panic("Unable to initialise clockevent device");
- dw_apb_clockevent_register(ced);
+ dw_apb_clockevent_register(ced);
+ }
+ return ret;
}
static void __iomem *sched_io_base;
static u32 sched_rate;
-static void __init add_clocksource(struct device_node *source_timer)
+static int __init add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
struct dw_apb_clocksource *cs;
u32 rate;
-
- timer_get_base_and_rate(source_timer, , );
-
- cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
- if (!cs)
- panic("Unable to initialise clocksource device");
-
- dw_apb_clocksource_start(cs);
- dw_apb_clocksource_register(cs);
-
- /*
-* Fallback to use the clocksource as sched_clock if no separate
-* timer is found. sched_io_base then points to the current_value
-* register of the clocksource timer.
-*/
- sched_io_base = iobase + 0x04;
- sched_rate = rate;
+ int ret;
+
+ ret = timer_get_base_and_rate(source_timer, , );
+ if (ret == 0) {
+ cs = dw_apb_clocksource_init(300, source_timer->name, iobase,
rate);
+ if (!cs)
+ panic("Unable to initialise clocksource device");
+
+ dw_apb_clocksource_start(cs);
+ dw_apb_clocksource_register(cs);
+
+ /*
+* Fallback to use the clocksource as sched_clock if no separate
+* timer is found. sched_io_base then points to the
current_value
+* register of the clocksource timer.
+*/
+ sch
[PATCH] clocksource: dw_apb_timer_of: return EPROBE_DEFER if no clock available
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clock manager doesn't
get probed until after the timer driver is probed. Thus, the driver hits
the panic "No clock nor clock-frequency property for %" because it cannot
properly get the clock.
This patch adds support for EPROBE_DEFER so the kernel can come back to
finish probing this timer driver after the clock driver is probed.
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 86 ---
1 file changed, 51 insertions(+), 35 deletions(-)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource/dw_apb_timer_of.c
index ab3ddebe8344..a8ce980c5146 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -14,7 +14,7 @@
#include
#include
-static void __init timer_get_base_and_rate(struct device_node *np,
+static int __init timer_get_base_and_rate(struct device_node *np,
void __iomem **base, u32 *rate)
{
struct clk *timer_clk;
@@ -47,65 +47,77 @@ static void __init timer_get_base_and_rate(struct
device_node *np,
np);
timer_clk = of_clk_get_by_name(np, "timer");
- if (IS_ERR(timer_clk))
- goto try_clock_freq;
+ if (IS_ERR(timer_clk)) {
+ if (PTR_ERR(timer_clk) != -EPROBE_DEFER) {
+ pr_err("Failed to get clock for %pOF\n", np);
+ goto try_clock_freq;
+ }
+ return PTR_ERR(timer_clk);
+ }
if (!clk_prepare_enable(timer_clk)) {
*rate = clk_get_rate(timer_clk);
- return;
+ return 0;
}
try_clock_freq:
if (of_property_read_u32(np, "clock-freq", rate) &&
of_property_read_u32(np, "clock-frequency", rate))
panic("No clock nor clock-frequency property for %pOFn", np);
+ return 0;
}
-static void __init add_clockevent(struct device_node *event_timer)
+static int __init add_clockevent(struct device_node *event_timer)
{
void __iomem *iobase;
struct dw_apb_clock_event_device *ced;
u32 irq, rate;
+ int ret = 0;
irq = irq_of_parse_and_map(event_timer, 0);
if (irq == 0)
panic("No IRQ for clock event timer");
- timer_get_base_and_rate(event_timer, , );
-
- ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
+ ret = timer_get_base_and_rate(event_timer, , );
+ if (ret == 0) {
+ ced = dw_apb_clockevent_init(-1, event_timer->name, 300,
iobase, irq,
rate);
- if (!ced)
- panic("Unable to initialise clockevent device");
+ if (!ced)
+ panic("Unable to initialise clockevent device");
- dw_apb_clockevent_register(ced);
+ dw_apb_clockevent_register(ced);
+ }
+ return ret;
}
static void __iomem *sched_io_base;
static u32 sched_rate;
-static void __init add_clocksource(struct device_node *source_timer)
+static int __init add_clocksource(struct device_node *source_timer)
{
void __iomem *iobase;
struct dw_apb_clocksource *cs;
u32 rate;
-
- timer_get_base_and_rate(source_timer, , );
-
- cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
- if (!cs)
- panic("Unable to initialise clocksource device");
-
- dw_apb_clocksource_start(cs);
- dw_apb_clocksource_register(cs);
-
- /*
-* Fallback to use the clocksource as sched_clock if no separate
-* timer is found. sched_io_base then points to the current_value
-* register of the clocksource timer.
-*/
- sched_io_base = iobase + 0x04;
- sched_rate = rate;
+ int ret;
+
+ ret = timer_get_base_and_rate(source_timer, , );
+ if (ret == 0) {
+ cs = dw_apb_clocksource_init(300, source_timer->name, iobase,
rate);
+ if (!cs)
+ panic("Unable to initialise clocksource device");
+
+ dw_apb_clocksource_start(cs);
+ dw_apb_clocksource_register(cs);
+
+ /*
+* Fallback to use the clocksource as sched_clock if no separate
+* timer is found. sched_io_base then points to the
current_value
+* register of the clocksource timer.
+*/
+ sched_io_base = iobase + 0x04;
+ sched_rate = rate;
+ }
+ return ret;
}
static u64 notrace read_sched_clock(void)
@@ -146,25 +158,2
Re: [PATCH 5/8] arm64: dts: agilex: Use generic "ngpios" rather than "snps,nr-gpios"
On 11/9/20 3:05 AM, Jisheng Zhang wrote:
> This is to remove similar errors as below:
>
> OF: /.../gpio-port@0: could not find phandle
>
> Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
> explained the reason of above errors well and added the generic
> "ngpios" property, let's use it.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index e1c0fcba5c20..2f731e3a7cd7 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -202,7 +202,7 @@ porta: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -222,7 +222,7 @@ portb: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
Re: [PATCH 8/8] ARM: dts: socfgpa: Use generic "ngpios" rather than "snps,nr-gpios"
On 11/9/20 3:07 AM, Jisheng Zhang wrote:
> This is to remove similar errors as below:
>
> OF: /.../gpio-port@0: could not find phandle
>
> Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
> explained the reason of above errors well and added the generic
> "ngpios" property, let's use it.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm/boot/dts/socfpga.dtsi | 6 +++---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 0b021eef0b53..32b7ad814ec6 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -612,7 +612,7 @@ porta: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <29>;
> + ngpios = <29>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -633,7 +633,7 @@ portb: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <29>;
> + ngpios = <29>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -654,7 +654,7 @@ portc: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <27>;
> + ngpios = <27>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
> b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 0013ec3463c4..34e23e0582fb 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -491,7 +491,7 @@ porta: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <29>;
> + ngpios = <29>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -511,7 +511,7 @@ portb: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <29>;
> + ngpios = <29>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -531,7 +531,7 @@ portc: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <27>;
> + ngpios = <27>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
Re: [PATCH 5/8] arm64: dts: agilex: Use generic "ngpios" rather than "snps,nr-gpios"
On 11/9/20 3:05 AM, Jisheng Zhang wrote:
> This is to remove similar errors as below:
>
> OF: /.../gpio-port@0: could not find phandle
>
> Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
> explained the reason of above errors well and added the generic
> "ngpios" property, let's use it.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index e1c0fcba5c20..2f731e3a7cd7 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -202,7 +202,7 @@ porta: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -222,7 +222,7 @@ portb: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
Re: [PATCH 1/8] arm64: dts: socfpga: Use generic "ngpios" rather than "snps,nr-gpios"
On 11/9/20 3:03 AM, Jisheng Zhang wrote:
> This is to remove similar errors as below:
>
> OF: /.../gpio-port@0: could not find phandle
>
> Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
> explained the reason of above errors well and added the generic
> "ngpios" property, let's use it.
>
> Signed-off-by: Jisheng Zhang
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 0f893984c256..d301ac0d406b 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -203,7 +203,7 @@ porta: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -223,7 +223,7 @@ portb: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
[PATCHv2] reset: socfpga: add error handling and release mem-region
In case of an error, call release_mem_region when an error happens
during allocation of resources. Also add error handling for the case
that reset_controller_register fails.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
v2: return ret value
---
drivers/reset/reset-socfpga.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index bdd984296196..2a72f861f798 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -44,7 +44,7 @@ static int a10_reset_init(struct device_node *np)
data->membase = ioremap(res.start, size);
if (!data->membase) {
ret = -ENOMEM;
- goto err_alloc;
+ goto release_region;
}
if (of_property_read_u32(np, "altr,modrst-offset", _offset))
@@ -59,7 +59,14 @@ static int a10_reset_init(struct device_node *np)
data->rcdev.of_node = np;
data->status_active_low = true;
- return reset_controller_register(>rcdev);
+ ret = reset_controller_register(>rcdev);
+ if (ret)
+ pr_err("unable to register device\n");
+
+ return ret;
+
+release_region:
+ release_mem_region(res.start, size);
err_alloc:
kfree(data);
--
2.17.1
[PATCH] reset: socfpga: add error handling and release mem-region
In case of an error, call release_mem_region when an error happens
during allocation of resources. Also add error handling for the case
that reset_controller_register fails.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/reset/reset-socfpga.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index bdd984296196..af9041ec37c6 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -44,7 +44,7 @@ static int a10_reset_init(struct device_node *np)
data->membase = ioremap(res.start, size);
if (!data->membase) {
ret = -ENOMEM;
- goto err_alloc;
+ goto release_region;
}
if (of_property_read_u32(np, "altr,modrst-offset", _offset))
@@ -59,7 +59,14 @@ static int a10_reset_init(struct device_node *np)
data->rcdev.of_node = np;
data->status_active_low = true;
- return reset_controller_register(>rcdev);
+ ret = reset_controller_register(>rcdev);
+ if (ret)
+ pr_err("unable to register device\n");
+
+ return 0;
+
+release_region:
+ release_mem_region(res.start, size);
err_alloc:
kfree(data);
--
2.17.1
Re: Build error caused by "arm64: dts: agilex: add nand clocks"
Hi Markus, Thanks for catching this. There's a commit that is going through the clock tree that will fix this: commit c2710fdf935bb1286e8eb6a6b44991bab1fe87af Author: Dinh Nguyen Date: Tue Jun 16 15:24:15 2020 -0500 dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Add the NAND_X_CLK and NAND_ECC_CLK clocks. Signed-off-by: Dinh Nguyen Link: https://lore.kernel.org/r/20200616202417.14376-1-dingu...@kernel.org Signed-off-by: Stephen Boyd Once the clock updates get merged, this should get fixed. I'll be more mindful of this in the future. Dinh On 8/4/20 1:48 PM, Markus Mayer wrote: > Hi, > > I don't know if anybody else is seeing this, but for me the commit > "arm64: dts: agilex: add nand clocks"[1] is causing a build error > while generating DTS files for ARM64. > > The error goes away when I drop the commit. > > $ ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make defconfig dtbs > HOSTCC scripts/basic/fixdep > HOSTCC scripts/kconfig/conf.o > HOSTCC scripts/kconfig/confdata.o > HOSTCC scripts/kconfig/expr.o > LEX scripts/kconfig/lexer.lex.c > YACCscripts/kconfig/parser.tab.[ch] > HOSTCC scripts/kconfig/lexer.lex.o > HOSTCC scripts/kconfig/parser.tab.o > HOSTCC scripts/kconfig/preprocess.o > HOSTCC scripts/kconfig/symbol.o > HOSTCC scripts/kconfig/util.o > HOSTLD scripts/kconfig/conf > *** Default configuration is based on 'defconfig' > [...] > DTC arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dtb > DTC arch/arm64/boot/dts/freescale/imx8mq-thor96.dtb > DTC arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb > DTC arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb > DTC arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dtb > DTC arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtb > DTC arch/arm64/boot/dts/freescale/imx8qxp-mek.dtb > DTC arch/arm64/boot/dts/freescale/s32v234-evb.dtb > DTC arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dtb > DTC arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dtb > DTC arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dtb > DTC arch/arm64/boot/dts/hisilicon/hi6220-hikey.dtb > DTC arch/arm64/boot/dts/hisilicon/hip05-d02.dtb > DTC arch/arm64/boot/dts/hisilicon/hip06-d03.dtb > DTC arch/arm64/boot/dts/hisilicon/hip07-d05.dtb > DTC arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb > Error: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:313.15-16 syntax error > FATAL ERROR: Unable to parse input tree > make[3]: *** [scripts/Makefile.lib:309: > arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtb] Error 1 > make[2]: *** [scripts/Makefile.build:497: arch/arm64/boot/dts/intel] Error 2 > make[1]: *** [Makefile:1306: dtbs] Error 2 > make: *** [Makefile:336: __build_one_by_one] Error 2 > > Regards, > -Markus > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d4ae4dd346cd49302d157b129ead2f60d3a82534 >
Re: clocksource: dw_apb_timer: commit 6d2e16a3181b broke Arria10 platform
Hi Serge, On 7/31/20 1:48 AM, Serge Semin wrote: > Hello Dinh, > It must be something wrong with your timer2 and timer3 declared in the Arria10 > dts because the patch didn't change anything for the first two timers (timer0 > and > timer1). It just permits to register all DW APB Timers found in dts. > > If those timers are broken, then you should have disabled them in the dts in > the > first place. If they are normal, then you need to investigate further why do > they cause the kernel panic. > Indeed, the dts reg entry for timer3 was broken. Thanks alot for exposing the issue. Apologies for the noise. Dinh
[PATCH] MAINTAINERS: edac: socfpga: transfer SoCFPGA EDAC maintainership
Thor Thayer is leaving Intel and will no longer be able to maintain the EDAC for SoCFPGA, thus transfer maintainership to Dinh Nguyen. Signed-off-by: Dinh Nguyen --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index f0569cf304ca..c53fc9febf12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2466,7 +2466,7 @@ S:Maintained F: drivers/clk/socfpga/ ARM/SOCFPGA EDAC SUPPORT -M: Thor Thayer +M: Dinh Nguyen S: Maintained F: drivers/edac/altera_edac. -- 2.17.1
Re: [PATCH] ARM: socfpga: PM: add missing put_device() call in socfpga_setup_ocram_self_refresh()
On 7/21/20 8:45 AM, Yu Kuai wrote:
> if of_find_device_by_node() succeed, socfpga_setup_ocram_self_refresh
> doesn't have a corresponding put_device(). Thus add a jump target to
> fix the exception handling for this function implementation.
>
> Fixes: 44fd8c7d4005 ("ARM: socfpga: support suspend to ram")
> Signed-off-by: Yu Kuai
> ---
> arch/arm/mach-socfpga/pm.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/pm.c b/arch/arm/mach-socfpga/pm.c
> index 6ed887cf8dc9..365c0428b21b 100644
> --- a/arch/arm/mach-socfpga/pm.c
> +++ b/arch/arm/mach-socfpga/pm.c
> @@ -49,14 +49,14 @@ static int socfpga_setup_ocram_self_refresh(void)
> if (!ocram_pool) {
> pr_warn("%s: ocram pool unavailable!\n", __func__);
> ret = -ENODEV;
> - goto put_node;
> + goto put_device;
> }
>
> ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz);
> if (!ocram_base) {
> pr_warn("%s: unable to alloc ocram!\n", __func__);
> ret = -ENOMEM;
> - goto put_node;
> + goto put_device;
> }
>
> ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
> @@ -67,7 +67,7 @@ static int socfpga_setup_ocram_self_refresh(void)
> if (!suspend_ocram_base) {
> pr_warn("%s: __arm_ioremap_exec failed!\n", __func__);
> ret = -ENOMEM;
> - goto put_node;
> + goto put_device;
> }
>
> /* Copy the code that puts DDR in self refresh to ocram */
> @@ -81,6 +81,8 @@ static int socfpga_setup_ocram_self_refresh(void)
> if (!socfpga_sdram_self_refresh_in_ocram)
> ret = -EFAULT;
>
> +put_device:
> + put_device(>dev);
> put_node:
> of_node_put(np);
>
>
Applied!
Thanks,
Dinh
Re: linux-next: Fixes tags need some work in the arm-soc-fixes tree
On 7/17/20 10:46 AM, Arnd Bergmann wrote: > On Fri, Jul 17, 2020 at 5:36 PM Dinh Nguyen wrote: >> On 7/16/20 3:10 PM, Arnd Bergmann wrote: >>> On Wed, Jul 15, 2020 at 9:14 PM Dinh Nguyen wrote: >>>> >>>> -BEGIN PGP SIGNED MESSAGE- >>>> Hash: SHA512 >>>> >>>> Hi, >>>> >>>> I apologize for this! I have an updated branch that fixes these tags. >>>> Let me know if I need to respin the pull request. >>> >>> I've recreated the branch from scratch now (this was one of only >>> two pull requests I got anyway), it should be fine now. >>> >> >> Thank you! > > I was about to send off the pull request to Linus now, but I now saw > that the tag I pulled was not updated and still has the broken lines. > > Could you make sure you upload a new tag and send the pull > request for that so I can pull it once more? > I just sent you an updated pull request for the tag socfpga_fixes_for_v5.8_v2. Thanks, Dinh
Re: linux-next: Fixes tags need some work in the arm-soc-fixes tree
On 7/16/20 3:10 PM, Arnd Bergmann wrote: > On Wed, Jul 15, 2020 at 9:14 PM Dinh Nguyen wrote: >> >> -BEGIN PGP SIGNED MESSAGE- >> Hash: SHA512 >> >> Hi, >> >> I apologize for this! I have an updated branch that fixes these tags. >> Let me know if I need to respin the pull request. > > I've recreated the branch from scratch now (this was one of only > two pull requests I got anyway), it should be fine now. > Thank you! Dinh
Re: linux-next: Fixes tags need some work in the arm-soc-fixes tree
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi,
I apologize for this! I have an updated branch that fixes these tags.
Let me know if I need to respin the pull request.
Thanks,
Dinh
On 7/13/20 4:57 PM, Stephen Rothwell wrote:
> Hi all,
>
> In commit
>
> 3e189a193471 ("ARM: dts: socfpga: Align L2 cache-controller
> nodename with dtschema")
>
> Fixes tag
>
> Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for
> Altera's Arria10
>
> has these problem(s):
>
> - Subject has leading but no trailing parentheses - Subject has
> leading but no trailing quotes
>
> In commit
>
> 8e343e71b092 ("arm64: dts: stratix10: increase QSPI reg address in
> nand dts file")
>
> Fixes tag
>
> Fixes: 80f132d73709 ("arm64: dts: increase the QSPI reg address for
> Stratix10
>
> has these problem(s):
>
> - Subject has leading but no trailing parentheses - Subject has
> leading but no trailing quotes
>
> In commit
>
> c188c8348836 ("arm64: dts: stratix10: add status to qspi dts
> node")
>
> Fixes tag
>
> Fixes: 0cb140d07fc75 ("arm64: dts: stratix10: Add QSPI support for
>
> has these problem(s):
>
> - Subject has leading but no trailing parentheses - Subject has
> leading but no trailing quotes
>
> In commit
>
> 390a90089db5 ("arm64: dts: agilex: add status to qspi dts node")
>
> Fixes tag
>
> Fixes: c4c8757b2d895 ("arm64: dts: agilex: add QSPI support for
> Intel
>
> has these problem(s):
>
> - Subject has leading but no trailing parentheses - Subject has
> leading but no trailing quotes
>
> Please do not split Fixes tags over more than one line.
>
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Re: [PATCH] fpga: stratix10-soc: make FPGA task un-interruptible
On 7/8/20 1:30 PM, Richard Gong wrote:
> Hi Dinh,
>
>
> On 7/8/20 12:08 PM, Dinh Nguyen wrote:
>> Hi
>>
>> On 7/7/20 11:14 AM, richard.g...@linux.intel.com wrote:
>>> From: Richard Gong
>>>
>>> When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
>>> reconfiguration process stops and the user can't perform a new FPGA
>>> reconfiguration properly.
>>>
>>> Set FPGA complete task to be not interruptible so that the user can
>>> properly perform FPGA reconfiguration after CTRL+C event.
>>>
>>> Signed-off-by: Richard Gong
>>> ---
>>> drivers/fpga/stratix10-soc.c | 23 +++
>>> 1 file changed, 3 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
>>> index 44b7c56..657a70c 100644
>>> --- a/drivers/fpga/stratix10-soc.c
>>> +++ b/drivers/fpga/stratix10-soc.c
>>> @@ -196,17 +196,13 @@ static int s10_ops_write_init(struct
>>> fpga_manager *mgr,
>>> if (ret < 0)
>>> goto init_done;
>>> - ret = wait_for_completion_interruptible_timeout(
>>> + ret = wait_for_completion_timeout(
>>> >status_return_completion, S10_RECONFIG_TIMEOUT);
>>> if (!ret) {
>>> dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
>>> ret = -ETIMEDOUT;
>>> goto init_done;
>>> }
>>> - if (ret < 0) {
>>> - dev_err(dev, "error (%d) waiting for RECONFIG_REQUEST\n", ret);
>>> - goto init_done;
>>> - }
>>> ret = 0;
>>> if (!test_and_clear_bit(SVC_STATUS_OK, >status)) {
>>> @@ -318,7 +314,7 @@ static int s10_ops_write(struct fpga_manager
>>> *mgr, const char *buf,
>>> */
>>> wait_status = 1; /* not timed out */
>>> if (!priv->status)
>>> - wait_status = wait_for_completion_interruptible_timeout(
>>> + wait_status = wait_for_completion_timeout(
>>> >status_return_completion,
>>> S10_BUFFER_TIMEOUT);
>>> @@ -340,13 +336,6 @@ static int s10_ops_write(struct fpga_manager
>>> *mgr, const char *buf,
>>> ret = -ETIMEDOUT;
>>> break;
>>> }
>>> - if (wait_status < 0) {
>>> - ret = wait_status;
>>> - dev_err(dev,
>>> - "error (%d) waiting for svc layer buffers\n",
>>> - ret);
>>> - break;
>>> - }
>>> }
>>> if (!s10_free_buffers(mgr))
>>> @@ -372,7 +361,7 @@ static int s10_ops_write_complete(struct
>>> fpga_manager *mgr,
>>> if (ret < 0)
>>> break;
>>> - ret = wait_for_completion_interruptible_timeout(
>>> + ret = wait_for_completion_timeout(
>>> >status_return_completion, timeout);
>>> if (!ret) {
>>> dev_err(dev,
>>> @@ -380,12 +369,6 @@ static int s10_ops_write_complete(struct
>>> fpga_manager *mgr,
>>> ret = -ETIMEDOUT;
>>> break;
>>> }
>>> - if (ret < 0) {
>>> - dev_err(dev,
>>> - "error (%d) waiting for RECONFIG_COMPLETED\n",
>>> - ret);
>>> - break;
>>> -
>>> /* Not error or timeout, so ret is # of jiffies until
>>> timeout */
>>> timeout = ret;
>>> ret = 0;
>>>
>>
>> Do you need the same change in drivers/fpga/socfpga.c?
> It is not required.
Why not?
> Also, you did not
>> include Moritz Fisher on this. He's the maintainer.
>>
> I did include Moritz Fisher in the submission, is
> something change recently?
>
My bad, I didn't see his name in the email.
Dinh
Re: [PATCH] fpga: stratix10-soc: make FPGA task un-interruptible
Hi
On 7/7/20 11:14 AM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
> reconfiguration process stops and the user can't perform a new FPGA
> reconfiguration properly.
>
> Set FPGA complete task to be not interruptible so that the user can
> properly perform FPGA reconfiguration after CTRL+C event.
>
> Signed-off-by: Richard Gong
> ---
> drivers/fpga/stratix10-soc.c | 23 +++
> 1 file changed, 3 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
> index 44b7c56..657a70c 100644
> --- a/drivers/fpga/stratix10-soc.c
> +++ b/drivers/fpga/stratix10-soc.c
> @@ -196,17 +196,13 @@ static int s10_ops_write_init(struct fpga_manager *mgr,
> if (ret < 0)
> goto init_done;
>
> - ret = wait_for_completion_interruptible_timeout(
> + ret = wait_for_completion_timeout(
> >status_return_completion, S10_RECONFIG_TIMEOUT);
> if (!ret) {
> dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
> ret = -ETIMEDOUT;
> goto init_done;
> }
> - if (ret < 0) {
> - dev_err(dev, "error (%d) waiting for RECONFIG_REQUEST\n", ret);
> - goto init_done;
> - }
>
> ret = 0;
> if (!test_and_clear_bit(SVC_STATUS_OK, >status)) {
> @@ -318,7 +314,7 @@ static int s10_ops_write(struct fpga_manager *mgr, const
> char *buf,
>*/
> wait_status = 1; /* not timed out */
> if (!priv->status)
> - wait_status = wait_for_completion_interruptible_timeout(
> + wait_status = wait_for_completion_timeout(
> >status_return_completion,
> S10_BUFFER_TIMEOUT);
>
> @@ -340,13 +336,6 @@ static int s10_ops_write(struct fpga_manager *mgr, const
> char *buf,
> ret = -ETIMEDOUT;
> break;
> }
> - if (wait_status < 0) {
> - ret = wait_status;
> - dev_err(dev,
> - "error (%d) waiting for svc layer buffers\n",
> - ret);
> - break;
> - }
> }
>
> if (!s10_free_buffers(mgr))
> @@ -372,7 +361,7 @@ static int s10_ops_write_complete(struct fpga_manager
> *mgr,
> if (ret < 0)
> break;
>
> - ret = wait_for_completion_interruptible_timeout(
> + ret = wait_for_completion_timeout(
> >status_return_completion, timeout);
> if (!ret) {
> dev_err(dev,
> @@ -380,12 +369,6 @@ static int s10_ops_write_complete(struct fpga_manager
> *mgr,
> ret = -ETIMEDOUT;
> break;
> }
> - if (ret < 0) {
> - dev_err(dev,
> - "error (%d) waiting for RECONFIG_COMPLETED\n",
> - ret);
> - break;
> - }
> /* Not error or timeout, so ret is # of jiffies until timeout */
> timeout = ret;
> ret = 0;
>
Do you need the same change in drivers/fpga/socfpga.c? Also, you did not
include Moritz Fisher on this. He's the maintainer.
Dinh
Re: [PATCH] arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema
On 6/29/20 3:16 AM, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> intc@fffc1000: $nodename:0:
> 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index d1fc9c2055f4..9498d1de730c 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -77,7 +77,7 @@
> method = "smc";
> };
>
> - intc: intc@fffc1000 {
> + intc: interrupt-controller@fffc1000 {
> compatible = "arm,gic-400", "arm,cortex-a15-gic";
> #interrupt-cells = <3>;
> interrupt-controller;
> @@ -302,7 +302,7 @@
> status = "disabled";
> };
>
> - nand: nand@ffb9 {
> + nand: nand-controller@ffb9 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "altr,socfpga-denali-nand";
> @@ -445,7 +445,7 @@
> clock-names = "timer";
> };
>
> - uart0: serial0@ffc02000 {
> + uart0: serial@ffc02000 {
> compatible = "snps,dw-apb-uart";
> reg = <0xffc02000 0x100>;
> interrupts = <0 108 4>;
> @@ -456,7 +456,7 @@
> status = "disabled";
> };
>
> - uart1: serial1@ffc02100 {
> + uart1: serial@ffc02100 {
> compatible = "snps,dw-apb-uart";
> reg = <0xffc02100 0x100>;
> interrupts = <0 109 4>;
>
Added the correct Fixes annotation and applied, thanks!
Dinh
Re: [PATCH] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
On 6/26/20 3:06 AM, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache@f000: $nodename:0:
> 'l2-cache@f000' does not match
> '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index c2b54af417a2..78f3267d9cbf 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -726,7 +726,7 @@
> };
> };
>
> - L2: l2-cache@fffef000 {
> + L2: cache-controller@fffef000 {
> compatible = "arm,pl310-cache";
> reg = <0xfffef000 0x1000>;
> interrupts = <0 38 0x04>;
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
> b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 3b8571b8b412..8f614c4b0e3e 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -636,7 +636,7 @@
> reg = <0xffcfb100 0x80>;
> };
>
> - L2: l2-cache@f000 {
> + L2: cache-controller@f000 {
> compatible = "arm,pl310-cache";
> reg = <0xf000 0x1000>;
> interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
>
Added the correct Fixes annotation and applied, thanks!
Dinh
[PATCHv4 1/2] spi: dw: add reset control
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v4: no change
v3: allow for other failures
remove tab for rstc reset_control
v2: use _get_optional_exclusive
put IP back into reset if there was an error in probe function
---
drivers/spi/spi-dw-mmio.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 0894b4c09496..a1b87d4606ba 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include "spi-dw.h"
@@ -29,6 +30,7 @@ struct dw_spi_mmio {
struct clk *clk;
struct clk *pclk;
void *priv;
+ struct reset_control *rstc;
};
#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -224,6 +226,14 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
if (ret)
goto out_clk;
+ /* find an optional reset controller */
+ dwsmmio->rstc = devm_reset_control_get_optional_exclusive(>dev,
"spi");
+ if (IS_ERR(dwsmmio->rstc)) {
+ ret = PTR_ERR(dwsmmio->rstc);
+ goto out_clk;
+ }
+ reset_control_deassert(dwsmmio->rstc);
+
dws->bus_num = pdev->id;
dws->max_freq = clk_get_rate(dwsmmio->clk);
@@ -257,6 +267,8 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
clk_disable_unprepare(dwsmmio->pclk);
out_clk:
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
+
return ret;
}
@@ -268,6 +280,7 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
pm_runtime_disable(>dev);
clk_disable_unprepare(dwsmmio->pclk);
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
return 0;
}
--
2.17.1
[PATCHv4 2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
Add optional reset property. Signed-off-by: Dinh Nguyen --- v4: rebased to linux-next 20200529 v3: no change v2: actually document the "resets" and "reset-names" optional properties --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 020e3168ee41..0f21407a7ea3 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -25,6 +25,9 @@ Optional properties: device. Supported values are 2 or 4 (the default). - dmas : Phandle + identifiers of Tx and Rx DMA channels. - dma-names : Contains the names of the DMA channels. Must be "tx" and "rx". +- resets : contains an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : must contain "spi" Child nodes as per the generic SPI binding. @@ -40,5 +43,7 @@ Example: num-cs = <2>; cs-gpios = < 13 0>, < 14 0>; + resets = < SPIM0_RST>; + reset-names = "spi"; }; -- 2.17.1
[PATCHv3 1/2] spi: dw: add reset control
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v3: allow for other failures
remove tab for rstc reset_control
v2: use _get_optional_exclusive
put IP back into reset if there was an error in probe function
---
drivers/spi/spi-dw-mmio.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d..1e921c40d79b 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "spi-dw.h"
@@ -30,6 +31,7 @@ struct dw_spi_mmio {
struct clk *clk;
struct clk *pclk;
void *priv;
+ struct reset_control *rstc;
};
#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -175,6 +177,14 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
if (ret)
goto out_clk;
+ /* find an optional reset controller */
+ dwsmmio->rstc = devm_reset_control_get_optional_exclusive(>dev,
"spi");
+ if (IS_ERR(dwsmmio->rstc)) {
+ ret = PTR_ERR(dwsmmio->rstc);
+ goto out_clk;
+ }
+ reset_control_deassert(dwsmmio->rstc);
+
dws->bus_num = pdev->id;
dws->max_freq = clk_get_rate(dwsmmio->clk);
@@ -208,6 +218,8 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
clk_disable_unprepare(dwsmmio->pclk);
out_clk:
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
+
return ret;
}
@@ -219,6 +231,7 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
pm_runtime_disable(>dev);
clk_disable_unprepare(dwsmmio->pclk);
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
return 0;
}
--
2.17.1
[PATCHv3 2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
Add optional reset property. Signed-off-by: Dinh Nguyen --- v2: actually document the "resets" and "reset-names" optional properties --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 3ed08ee9feba..c679778612f3 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -22,6 +22,9 @@ Optional properties: - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this device. Supported values are 2 or 4 (the default). +- resets : contains an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : must contain "spi" Child nodes as per the generic SPI binding. @@ -37,5 +40,7 @@ Example: num-cs = <2>; cs-gpios = < 13 0>, < 14 0>; + resets = < SPIM0_RST>; + reset-names = "spi"; }; -- 2.17.1
[PATCHv2 1/2] spi: dw: add reset control
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v2: use _get_optional_exclusive
put IP back into reset if there was an error in probe function
---
drivers/spi/spi-dw-mmio.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d..07e015b6d03d 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "spi-dw.h"
@@ -30,6 +31,7 @@ struct dw_spi_mmio {
struct clk *clk;
struct clk *pclk;
void *priv;
+ struct reset_control*rstc;
};
#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -175,6 +177,14 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
if (ret)
goto out_clk;
+ /* find an optional reset controller */
+ dwsmmio->rstc = devm_reset_control_get_optional_exclusive(>dev,
"spi");
+ if (IS_ERR(dwsmmio->rstc)) {
+ if (PTR_ERR(dwsmmio->rstc) == -EPROBE_DEFER)
+ return PTR_ERR(dwsmmio->rstc);
+ }
+ reset_control_deassert(dwsmmio->rstc);
+
dws->bus_num = pdev->id;
dws->max_freq = clk_get_rate(dwsmmio->clk);
@@ -208,6 +218,8 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
clk_disable_unprepare(dwsmmio->pclk);
out_clk:
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
+
return ret;
}
@@ -219,6 +231,7 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
pm_runtime_disable(>dev);
clk_disable_unprepare(dwsmmio->pclk);
clk_disable_unprepare(dwsmmio->clk);
+ reset_control_assert(dwsmmio->rstc);
return 0;
}
--
2.17.1
[PATCHv2 2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
Add optional reset property. Signed-off-by: Dinh Nguyen --- v2: actually document the "resets" and "reset-names" optional properties --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 3ed08ee9feba..c679778612f3 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -22,6 +22,9 @@ Optional properties: - num-cs : The number of chipselects. If omitted, this will default to 4. - reg-io-width : The I/O register width (in bytes) implemented by this device. Supported values are 2 or 4 (the default). +- resets : contains an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : must contain "spi" Child nodes as per the generic SPI binding. @@ -37,5 +40,7 @@ Example: num-cs = <2>; cs-gpios = < 13 0>, < 14 0>; + resets = < SPIM0_RST>; + reset-names = "spi"; }; -- 2.17.1
[PATCH 2/2] dt-bindings: snps,dw-apb-ssi: add optional reset property
Add optional reset property. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 3ed08ee9feba..e01c557a9876 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -37,5 +37,7 @@ Example: num-cs = <2>; cs-gpios = < 13 0>, < 14 0>; + resets = < SPIM0_RST>; + reset-names = "spi"; }; -- 2.17.1
[PATCH 1/2] spi: dw: add reset control
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
drivers/spi/spi-dw-mmio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d..5c813e15ed89 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include "spi-dw.h"
@@ -30,6 +31,7 @@ struct dw_spi_mmio {
struct clk *clk;
struct clk *pclk;
void *priv;
+ struct reset_control*rstc;
};
#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -145,6 +147,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
if (!dwsmmio)
return -ENOMEM;
+ dwsmmio->rstc = devm_reset_control_get_exclusive(>dev, "spi");
+ if (!IS_ERR(dwsmmio->rstc))
+ reset_control_deassert(dwsmmio->rstc);
+
dws = >dws;
/* Get basic io resource and map it */
@@ -220,6 +226,9 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
clk_disable_unprepare(dwsmmio->pclk);
clk_disable_unprepare(dwsmmio->clk);
+ if (dwsmmio->rstc)
+ reset_control_assert(dwsmmio->rstc);
+
return 0;
}
--
2.17.1
[RESEND PATCHv7 1/5] clk: socfpga: stratix10: use new parent data scheme
Convert, where possible, the stratix10 clock driver to the new parent
data scheme by specifying the parent data for clocks that have multiple
parents.
Signed-off-by: Dinh Nguyen
---
v7: no change
v6: no change
v5: no change
v4: no change
v3: no change
v2: add fw_name
---
drivers/clk/socfpga/clk-gate-s10.c | 5 +-
drivers/clk/socfpga/clk-periph-s10.c | 10 +-
drivers/clk/socfpga/clk-pll-s10.c| 4 +-
drivers/clk/socfpga/clk-s10.c| 160 ++-
drivers/clk/socfpga/stratix10-clk.h | 8 +-
5 files changed, 146 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/socfpga/clk-gate-s10.c
b/drivers/clk/socfpga/clk-gate-s10.c
index 8be4722f6064..083b2ec21fdd 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct
stratix10_gate_clock *clks, void __io
struct clk *clk;
struct socfpga_gate_clk *socfpga_clk;
struct clk_init_data init;
- const char * const *parent_names = clks->parent_names;
const char *parent_name = clks->parent_name;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct
stratix10_gate_clock *clks, void __io
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : _name;
+ init.parent_names = parent_name ? _name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
socfpga_clk->hw.hw.init =
clk = clk_register(NULL, _clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-s10.c
b/drivers/clk/socfpga/clk-periph-s10.c
index dd6d4056e9de..397b77b89b16 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct
stratix10_perip_c_clock *clks,
struct clk_init_data init;
const char *name = clks->name;
const char *parent_name = clks->parent_name;
- const char * const *parent_names = clks->parent_names;
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
if (WARN_ON(!periph_clk))
@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct
stratix10_perip_c_clock *clks,
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : _name;
+ init.parent_names = parent_name ? _name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
periph_clk->hw.hw.init =
@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct
stratix10_perip_cnt_clock *clks
struct clk_init_data init;
const char *name = clks->name;
const char *parent_name = clks->parent_name;
- const char * const *parent_names = clks->parent_names;
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
if (WARN_ON(!periph_clk))
@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct
stratix10_perip_cnt_clock *clks
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names ? parent_names : _name;
+ init.parent_names = parent_name ? _name : NULL;
+ if (init.parent_names == NULL)
+ init.parent_data = clks->parent_data;
periph_clk->hw.hw.init =
diff --git a/drivers/clk/socfpga/clk-pll-s10.c
b/drivers/clk/socfpga/clk-pll-s10.c
index a301bb22f36c..bcd3f14e9145 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct
stratix10_pll_clock *clks,
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
- const char * const *parent_names = clks->parent_names;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct
stratix10_pll_clock *clks,
init.flags = clks->flags;
init.num_parents = clks->num_parents;
- init.parent_names = parent_names;
+ init.parent_names = NULL;
+ init.parent_data = clks->parent_data;
pll_clk->hw.hw.init =
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index dea7c6c7d269..c1dfc9b34e4e 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -12,35 +12,137 @@
#include "stratix10-clk.h"
-static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
- "f2s-free-clk",};
-static const c
[RESEND PATCHv7 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v7: Fix license to be "(GPL-2.0-only OR BSD-2-Clause)"
v6: fix build error by adding descriptions for clocks and reg in
properties
v5: update license to GPL-2.0-only
Add additionalProperties
Add clock input for clkmgr
v4: really fix build error(comment formatting was wrong)
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAML
---
.../bindings/clock/intel,agilex.yaml | 46
include/dt-bindings/clock/agilex-clock.h | 70 +++
2 files changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
create mode 100644 include/dt-bindings/clock/agilex-clock.h
diff --git a/Documentation/devicetree/bindings/clock/intel,agilex.yaml
b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
new file mode 100644
index ..cf5a9eb803e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+ - Dinh Nguyen
+
+description:
+ The Intel Agilex Clock controller is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+const: intel,agilex-clkmgr
+
+ '#clock-cells':
+const: 1
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock controller node:
+ - |
+clkmgr: clock-controller@ffd1 {
+ compatible = "intel,agilex-clkmgr";
+ reg = <0xffd1 0x1000>;
+ clocks = <>;
+ #clock-cells = <1>;
+};
+...
diff --git a/include/dt-bindings/clock/agilex-clock.h
b/include/dt-bindings/clock/agilex-clock.h
new file mode 100644
index ..f19cf8ccbdd2
--- /dev/null
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC10
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX_CB_INTOSC_LS_CLK2
+#define AGILEX_L4_SYS_FREE_CLK 3
+#define AGILEX_F2S_FREE_CLK4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK5
+#define AGILEX_MAIN_PLL_C0_CLK 6
+#define AGILEX_MAIN_PLL_C1_CLK 7
+#define AGILEX_MAIN_PLL_C2_CLK 8
+#define AGILEX_MAIN_PLL_C3_CLK 9
+#define AGILEX_PERIPH_PLL_CLK 10
+#define AGILEX_PERIPH_PLL_C0_CLK 11
+#define AGILEX_PERIPH_PLL_C1_CLK 12
+#define AGILEX_PERIPH_PLL_C2_CLK 13
+#define AGILEX_PERIPH_PLL_C3_CLK 14
+#define AGILEX_MPU_FREE_CLK15
+#define AGILEX_MPU_CCU_CLK 16
+#define AGILEX_BOOT_CLK17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK18
+#define AGILEX_NOC_FREE_CLK19
+#define AGILEX_S2F_USR0_CLK20
+#define AGILEX_NOC_CLK 21
+#define AGILEX_EMAC_A_FREE_CLK 22
+#define AGILEX_EMAC_B_FREE_CLK 23
+#define AGILEX_EMAC_PTP_FREE_CLK 24
+#define AGILEX_GPIO_DB_FREE_CLK25
+#define AGILEX_SDMMC_FREE_CLK 26
+#define AGILEX_S2F_USER0_FREE_CLK 27
+#define AGILEX_S2F_USER1_FREE_CLK 28
+#define AGILEX_PSI_REF_FREE_CLK29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK 30
+#define AGILEX_MPU_L2RAM_CLK 31
+#define AGILEX_MPU_PERIPH_CLK 32
+#define AGILEX_L4_MAIN_CLK 33
+#define AGILEX_L4_MP_CLK 34
+#define AGILEX_L4_SP_CLK 35
+#define AGILEX_CS_AT_CLK 36
+#define AGILEX_CS_TRACE_CLK37
+#define AGILEX_CS_PDBG_CLK 38
+#define AGILEX_CS_TIMER_CLK39
+#define AGILEX_S2F_USER0_CLK 40
+#define AGILEX_EMAC0_CLK 41
+#define AGILEX_EMAC1_CLK 43
+#define AGILEX_EMAC2_CLK 44
+#define AGILEX_EMAC_PTP_CLK45
+#define AGILEX_GPIO_DB_CLK 46
+#define AGILEX_NAND_CLK47
+#define AGILEX_PSI_REF_CLK 48
+#define AGILEX_S2F_USER1_CLK 49
+#define AGILEX_SDMMC_CLK 50
+#define AGILEX_SPI_M_CLK 51
+#define AGILEX_USB_CLK 52
+#define AGILEX_NUM_CLKS
[RESEND PATCHv7 3/5] clk: socfpga: add const to _ops data structures
All the static clk_ops data structure need a const.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created
---
drivers/clk/socfpga/clk-pll-a10.c | 2 +-
drivers/clk/socfpga/clk-pll-s10.c | 4 ++--
drivers/clk/socfpga/clk-pll.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c
b/drivers/clk/socfpga/clk-pll-a10.c
index 6d9395106c0c..db54f7d806a0 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
CLK_MGR_PLL_CLK_SRC_MASK;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
};
diff --git a/drivers/clk/socfpga/clk-pll-s10.c
b/drivers/clk/socfpga/clk-pll-s10.c
index 9faa80ff3b53..5c3e1ee44f6b 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
return 0;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = clk_pll_prepare,
};
-static struct clk_ops clk_boot_ops = {
+static const struct clk_ops clk_boot_ops = {
.recalc_rate = clk_boot_clk_recalc_rate,
.get_parent = clk_boot_get_parent,
.prepare = clk_pll_prepare,
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index a001641b2f42..e5fb786843f3 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
CLK_MGR_PLL_CLK_SRC_MASK;
}
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
};
--
2.17.1
[RESEND PATCHv7 2/5] clk: socfpga: remove clk_ops enable/disable methods
The enable/disable clock ops are already defined in the standard clock
ops, so we don't need to assign them.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created
---
drivers/clk/socfpga/clk-pll-a10.c | 2 --
drivers/clk/socfpga/clk-pll-s10.c | 2 --
drivers/clk/socfpga/clk-pll.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c
b/drivers/clk/socfpga/clk-pll-a10.c
index 3816fc04b274..6d9395106c0c 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct
device_node *node,
pll_clk->hw.hw.init =
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, _clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll-s10.c
b/drivers/clk/socfpga/clk-pll-s10.c
index bcd3f14e9145..9faa80ff3b53 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct
stratix10_pll_clock *clks,
pll_clk->hw.hw.init =
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, _clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index dc65cc0fd3bd..a001641b2f42 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct
device_node *node,
pll_clk->hw.hw.init =
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, _clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
--
2.17.1
[RESEND PATCHv7 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: Address Stephen Boyd's comments
v2: update to use clk_parent_data
---
drivers/clk/Makefile| 3 +-
drivers/clk/socfpga/Makefile| 2 +
drivers/clk/socfpga/clk-agilex.c| 454
drivers/clk/socfpga/clk-pll-s10.c | 68 +
drivers/clk/socfpga/stratix10-clk.h | 2 +
5 files changed, 528 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/socfpga/clk-agilex.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f4169cc2fd31..a178e4b6001f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -104,10 +104,11 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_SIRF)+= sirf/
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
+obj-$(CONFIG_ARCH_AGILEX) += socfpga/
+obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_SPRD)+= sprd/
obj-$(CONFIG_ARCH_STI) += st/
-obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_SUNXI_CCU)+= sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index ce5aa7802eb8..bf736f8d201a 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o
clk-periph.o
obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
new file mode 100644
index ..699527f7e764
--- /dev/null
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "stratix10-clk.h"
+
+static const struct clk_parent_data pll_mux[] = {
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data cntr_mux[] = {
+ { .fw_name = "main_pll",
+ .name = "main_pll", },
+ { .fw_name = "periph_pll",
+ .name = "periph_pll", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data boot_mux[] = {
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+};
+
+static const struct clk_parent_data mpu_free_mux[] = {
+ { .fw_name = "main_pll_c0",
+ .name = "main_pll_c0", },
+ { .fw_name = "peri_pll_c0",
+ .name = "peri_pll_c0", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data noc_free_mux[] = {
+ { .fw_name = "main_pll_c1",
+ .name = "main_pll_c1", },
+ { .fw_name = "peri_pll_c1",
+ .name = "peri_pll_c1", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+ { .fw_name = "cb-intosc-hs-div2-clk",
+ .name = "cb-intosc-hs-div2-clk", },
+ { .fw_name = "f2s-free-clk",
+ .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data emaca_free_mux[] = {
+ { .fw_name = "main_pll_c2",
+ .name = "main_pll_c2", },
+ { .fw_name = "peri_pll_c2",
+ .name = "peri_pll_c2", },
+ { .fw_name = "osc1",
+ .name = "osc1", },
+
Re: [RESEND PATCHv1] arm64: defconfig: enable rsu driver
On 10/17/19 3:15 PM, richard.g...@linux.intel.com wrote: > From: Richard Gong > > Enable Intel Stratix10 Remote System Update (RSU) driver > > The Intel Remote System Update (RSU) driver provides a way for customers > to update the boot configuration of a Intel Stratix 10 SoC device with > significantly reduced risk of corrupting the bitstream storage and > bricking the system. > > Signed-off-by: Richard Gong > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index c9adae4..0b626b2 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -90,6 +90,7 @@ CONFIG_ARM_TEGRA186_CPUFREQ=y > CONFIG_ARM_SCPI_PROTOCOL=y > CONFIG_RASPBERRYPI_FIRMWARE=y > CONFIG_INTEL_STRATIX10_SERVICE=y > +CONFIG_INTEL_STRATIX10_RSU=m > CONFIG_TI_SCI_PROTOCOL=y > CONFIG_EFI_CAPSULE_LOADER=y > CONFIG_IMX_SCU=y > Applied! Thanks, Dinh
Re: [PATCHv1] arm64: dts: agilex: add service layer, fpga manager and fpga region
On 10/17/19 2:34 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add service layer, fpga manager and fpga region to the device tree
> on Intel Agilex platform.
>
> Signed-off-by: Richard Gong
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 32
> +++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index 36abc25..94090c6 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -12,6 +12,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + service_reserved: svcbuffer@0 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x0 0x0 0x100>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -81,6 +94,13 @@
> interrupt-parent = <>;
> ranges = <0 0 0 0x>;
>
> + base_fpga_region {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + compatible = "fpga-region";
> + fpga-mgr = <_mgr>;
> + };
> +
> gmac0: ethernet@ff80 {
> compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a",
> "snps,dwmac";
> reg = <0xff80 0x2000>;
> @@ -442,5 +462,17 @@
>
> status = "disabled";
> };
> +
> + firmware {
> + svc {
> + compatible = "intel,stratix10-svc";
> + method = "smc";
> + memory-region = <_reserved>;
> +
> + fpga_mgr: fpga-mgr {
> + compatible =
> "intel,stratix10-soc-fpga-mgr";
> + };
> + };
> + };
> };
> };
>
Applied.
Dinh
Re: [PATCHv2] arm64: dts: agilex: add QSPI support for Intel Agilex
On 10/17/19 8:00 PM, Ley Foon Tan wrote:
> On Wed, 2019-10-16 at 02:40 -0700, Ooi, Joyce wrote:
>> This patch adds QSPI flash interface in device tree for Intel Agilex
>>
>> Signed-off-by: Ooi, Joyce
>> ---
>> v2: update the qspi_rootfs partition size
>> ---
>> arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 35
>> ++
>> 1 file changed, 35 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
>> b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
>> index 7814a9e..8de8118 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
>> @@ -73,3 +73,38 @@
>> {
>> status = "okay";
>> };
>> +
>> + {
>> +flash@0 {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +compatible = "mt25qu02g";
>> +reg = <0>;
>> +spi-max-frequency = <5000>;
> QSPI can support up to 100MHz.
I've updated the patch accordingly.
Dinh
Re: [PATCHv2] arm64: dts: altera: update QSPI reg addresses for Stratix10
On 10/16/19 4:44 AM, Ooi, Joyce wrote:
> This patch updates the reg addresses for QSPI boot and QSPI rootfs in
> the device tree for Stratix10
>
> Signed-off-by: Ooi, Joyce
> ---
> v2: update the qspi_rootfs partition size
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> index 66e4ffb..3704a17 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
> @@ -178,12 +178,12 @@
>
> qspi_boot: partition@0 {
> label = "Boot and fpga data";
> - reg = <0x0 0x400>;
> + reg = <0x0 0x034B>;
> };
>
> - qspi_rootfs: partition@400 {
> + qspi_rootfs: partition@34B {
> label = "Root Filesystem - JFFS2";
> - reg = <0x400 0x400>;
> + reg = <0x034B 0x0CB5>;
> };
> };
> };
>
Applied.
Thanks,
Dinh
Re: [PATCHv2] arm64: defconfig: add JFFS FS support in defconfig
On 10/17/19 1:28 AM, Ooi, Joyce wrote: > This patch adds JFFS2 FS support and remove QSPI Sector 4K size force in > the default defconfig > > Signed-off-by: Ooi, Joyce > --- > v2: disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS using the correct syntax > --- > arch/arm64/configs/defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index c9adae4..6080c6e 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -860,3 +860,5 @@ CONFIG_DEBUG_KERNEL=y > # CONFIG_DEBUG_PREEMPT is not set > # CONFIG_FTRACE is not set > CONFIG_MEMTEST=y > +CONFIG_JFFS2_FS=y > +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set > Can you explain why you're removing CONFIG_MTD_SPI_NOR_USE_4K_SECTORS? Dinh
[PATCH] arm64: defconfig: enable the Cadence QSPI controller
Enable the Cadence QSPI controller driver that is on the Stratix10 and Agilex platforms. Signed-off-by: Dinh Nguyen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8e05c39eab08..cd596df2edfc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -211,6 +211,7 @@ CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y -- 2.20.0
[PATCHv2] reset: build simple reset controller driver for Agilex
The Intel SoCFPGA Agilex platform shares the same reset controller that is on the Stratix10. Signed-off-by: Dinh Nguyen --- v2: rebase to v5.4-rc1 --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7b07281aa0ae..46f7986c3587 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -129,7 +129,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARC + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARC || ARCH_AGILEX help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, -- 2.20.0
Re: [PATCH RESEND] reset: build simple reset controller driver for Agilex
Please ignore this version. I need to rebase it to v5.4-rc1. Sorry for the noise... Dinh On 10/14/19 10:08 AM, Dinh Nguyen wrote: > The Intel SoCFPGA Agilex platform shares the same reset controller that > is on the Stratix10. > > Signed-off-by: Dinh Nguyen > --- > drivers/reset/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 21efb7d39d62..280e69fbf86d 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -118,7 +118,7 @@ config RESET_QCOM_PDC > > config RESET_SIMPLE > bool "Simple Reset Controller Driver" if COMPILE_TEST > - default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || > ARCH_ASPEED || ARCH_BITMAIN > + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || > ARCH_ASPEED || ARCH_BITMAIN || ARCH_AGILEX > help > This enables a simple reset controller driver for reset lines that > that can be asserted and deasserted by toggling bits in a contiguous, >
[PATCH RESEND] reset: build simple reset controller driver for Agilex
The Intel SoCFPGA Agilex platform shares the same reset controller that is on the Stratix10. Signed-off-by: Dinh Nguyen --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 21efb7d39d62..280e69fbf86d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -118,7 +118,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_AGILEX help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, -- 2.20.0
Re: [PATCHv3] ARM: drivers/amba: release and cleanup the resource to allow for deferred probe
On 10/2/19 12:32 PM, Russell King - ARM Linux admin wrote:
> On Wed, Oct 02, 2019 at 09:35:51AM -0500, Dinh Nguyen wrote:
>> With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe", the amba bus driver needs to be deferred probe because the
>> reset driver is probed later. However with a deferred probe, the call to
>> request_resource() in the driver returns -EBUSY. The reason is the driver
>> has not released the resource from the previous probe attempt.
>>
>> This patch fixes how we handle the condition of EPROBE_DEFER that is returned
>> from getting the reset controls. For this condition, the patch will jump
>> to defer_probe, which will iounmap, dev_pm_domain_detach, and release the
>> resource.
>>
>> Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe")
>> Signed-off-by: Dinh Nguyen
>> ---
>> v3: jump to defer_probe where the driver will unmap and pm_detach the
>> driver resource for the next probe attempt
>> v2: release the resource when of_reset_control_array_get_optional_shared()
>> returns EPROBE_DEFER
>> ---
>> drivers/amba/bus.c | 8 ++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
>> index f39f075abff9..4a021b1dab3d 100644
>> --- a/drivers/amba/bus.c
>> +++ b/drivers/amba/bus.c
>> @@ -409,9 +409,12 @@ static int amba_device_try_add(struct amba_device *dev,
>> struct resource *parent)
>> */
>> rstc =
>> of_reset_control_array_get_optional_shared(dev->dev.of_node);
>> if (IS_ERR(rstc)) {
>> -if (PTR_ERR(rstc) != -EPROBE_DEFER)
>> +ret = PTR_ERR(rstc);
>> +if (ret == -EPROBE_DEFER)
>> +goto defer_probe;
>> +else
>> dev_err(>dev, "Can't get amba reset!\n");
>> -return PTR_ERR(rstc);
>> +return ret;
>
> So, if of_reset_control_array_get_optional_shared() returns an error,
> we end up leaking the ioremap(), the resource claim, the pclk enable
> and pm domain? If it returns -EPROBE_DEFER, we end up leaking the
> pclk enable?
>
> I think this is going to be quicker if I write the patch - I haven't
> build-tested this yet though. Please check whether this works for
> you.
>
> Thanks.
>
> 8<=
> From: Russell King
> Subject: [PATCH] drivers/amba: fix reset control error handling
>
> With commit 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control
> to amba bus probe") it is possible for the the amba bus driver to defer
> probing the device for its IDs because the reset driver may be probed
> later.
>
> However when a subsequent probe occurs, the call to request_resource()
> in the driver returns -EBUSY as the driver has not released the resource
> from the initial probe attempt - or cleaned up any of the preceding
> actions.
>
> Fix this both for the deferred probe case as well as a failure to get
> the reset.
>
> Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to amba
> bus probe")
> Signed-off-by: Russell King
> ---
> drivers/amba/bus.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
> index f39f075abff9..fe1523664816 100644
> --- a/drivers/amba/bus.c
> +++ b/drivers/amba/bus.c
> @@ -409,9 +409,11 @@ static int amba_device_try_add(struct amba_device *dev,
> struct resource *parent)
>*/
> rstc =
> of_reset_control_array_get_optional_shared(dev->dev.of_node);
> if (IS_ERR(rstc)) {
> - if (PTR_ERR(rstc) != -EPROBE_DEFER)
> - dev_err(>dev, "Can't get amba reset!\n");
> - return PTR_ERR(rstc);
> + ret = PTR_ERR(rstc);
> + if (ret != -EPROBE_DEFER)
> + dev_err(>dev, "can't get reset: %d\n",
> + ret);
> + goto err_reset;
> }
> reset_control_deassert(rstc);
> reset_control_put(rstc);
> @@ -472,6 +474,12 @@ static int amba_device_try_add(struct amba_device *dev,
> struct resource *parent)
> release_resource(>res);
> err_out:
> return ret;
> +
> + err_reset:
> + amba_put_disable_pclk(dev);
> + iounmap(tmp);
> + dev_pm_domain_detach(>dev, true);
> + goto err_release;
> }
>
> /*
>
Tested-by: Dinh Nguyen
Thanks,
Dinh
Re: [PATCHv3] ARM: drivers/amba: release and cleanup the resource to allow for deferred probe
On 10/2/19 12:32 PM, Russell King - ARM Linux admin wrote:
> On Wed, Oct 02, 2019 at 09:35:51AM -0500, Dinh Nguyen wrote:
>> With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe", the amba bus driver needs to be deferred probe because the
>> reset driver is probed later. However with a deferred probe, the call to
>> request_resource() in the driver returns -EBUSY. The reason is the driver
>> has not released the resource from the previous probe attempt.
>>
>> This patch fixes how we handle the condition of EPROBE_DEFER that is returned
>> from getting the reset controls. For this condition, the patch will jump
>> to defer_probe, which will iounmap, dev_pm_domain_detach, and release the
>> resource.
>>
>> Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe")
>> Signed-off-by: Dinh Nguyen
>> ---
>> v3: jump to defer_probe where the driver will unmap and pm_detach the
>> driver resource for the next probe attempt
>> v2: release the resource when of_reset_control_array_get_optional_shared()
>> returns EPROBE_DEFER
>> ---
>> drivers/amba/bus.c | 8 ++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
>> index f39f075abff9..4a021b1dab3d 100644
>> --- a/drivers/amba/bus.c
>> +++ b/drivers/amba/bus.c
>> @@ -409,9 +409,12 @@ static int amba_device_try_add(struct amba_device *dev,
>> struct resource *parent)
>> */
>> rstc =
>> of_reset_control_array_get_optional_shared(dev->dev.of_node);
>> if (IS_ERR(rstc)) {
>> -if (PTR_ERR(rstc) != -EPROBE_DEFER)
>> +ret = PTR_ERR(rstc);
>> +if (ret == -EPROBE_DEFER)
>> +goto defer_probe;
>> +else
>> dev_err(>dev, "Can't get amba reset!\n");
>> -return PTR_ERR(rstc);
>> +return ret;
>
> So, if of_reset_control_array_get_optional_shared() returns an error,
> we end up leaking the ioremap(), the resource claim, the pclk enable
> and pm domain? If it returns -EPROBE_DEFER, we end up leaking the
> pclk enable?
>
> I think this is going to be quicker if I write the patch - I haven't
> build-tested this yet though. Please check whether this works for
> you.
>
> Thanks.
>
> 8<=
> From: Russell King
> Subject: [PATCH] drivers/amba: fix reset control error handling
>
> With commit 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control
> to amba bus probe") it is possible for the the amba bus driver to defer
> probing the device for its IDs because the reset driver may be probed
> later.
>
> However when a subsequent probe occurs, the call to request_resource()
> in the driver returns -EBUSY as the driver has not released the resource
> from the initial probe attempt - or cleaned up any of the preceding
> actions.
>
> Fix this both for the deferred probe case as well as a failure to get
> the reset.
>
> Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to amba
> bus probe")
> Signed-off-by: Russell King
> ---
> drivers/amba/bus.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
> index f39f075abff9..fe1523664816 100644
> --- a/drivers/amba/bus.c
> +++ b/drivers/amba/bus.c
> @@ -409,9 +409,11 @@ static int amba_device_try_add(struct amba_device *dev,
> struct resource *parent)
>*/
> rstc =
> of_reset_control_array_get_optional_shared(dev->dev.of_node);
> if (IS_ERR(rstc)) {
> - if (PTR_ERR(rstc) != -EPROBE_DEFER)
> - dev_err(>dev, "Can't get amba reset!\n");
> - return PTR_ERR(rstc);
> + ret = PTR_ERR(rstc);
> + if (ret != -EPROBE_DEFER)
> + dev_err(>dev, "can't get reset: %d\n",
> + ret);
> + goto err_reset;
> }
> reset_control_deassert(rstc);
> reset_control_put(rstc);
> @@ -472,6 +474,12 @@ static int amba_device_try_add(struct amba_device *dev,
> struct resource *parent)
> release_resource(>res);
> err_out:
> return ret;
> +
> + err_reset:
> + amba_put_disable_pclk(dev);
> + iounmap(tmp);
> + dev_pm_domain_detach(>dev, true);
> + goto err_release;
> }
>
> /*
>
Tested-by: Dinh Nguyen
Thanks,
Dinh
[PATCHv3] ARM: drivers/amba: release and cleanup the resource to allow for deferred probe
With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
amba bus probe", the amba bus driver needs to be deferred probe because the
reset driver is probed later. However with a deferred probe, the call to
request_resource() in the driver returns -EBUSY. The reason is the driver
has not released the resource from the previous probe attempt.
This patch fixes how we handle the condition of EPROBE_DEFER that is returned
from getting the reset controls. For this condition, the patch will jump
to defer_probe, which will iounmap, dev_pm_domain_detach, and release the
resource.
Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
amba bus probe")
Signed-off-by: Dinh Nguyen
---
v3: jump to defer_probe where the driver will unmap and pm_detach the
driver resource for the next probe attempt
v2: release the resource when of_reset_control_array_get_optional_shared()
returns EPROBE_DEFER
---
drivers/amba/bus.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index f39f075abff9..4a021b1dab3d 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -409,9 +409,12 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
*/
rstc =
of_reset_control_array_get_optional_shared(dev->dev.of_node);
if (IS_ERR(rstc)) {
- if (PTR_ERR(rstc) != -EPROBE_DEFER)
+ ret = PTR_ERR(rstc);
+ if (ret == -EPROBE_DEFER)
+ goto defer_probe;
+ else
dev_err(>dev, "Can't get amba reset!\n");
- return PTR_ERR(rstc);
+ return ret;
}
reset_control_deassert(rstc);
reset_control_put(rstc);
@@ -448,6 +451,7 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = -ENODEV;
}
+ defer_probe:
iounmap(tmp);
dev_pm_domain_detach(>dev, true);
--
2.20.0
[PATCHv2] ARM: drivers/amba: release the resource to allow for deferred probe
With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
amba bus probe", the amba bus driver needs to be deferred probe because the
reset driver is probed later. However with a deferred probe, the call to
request_resource() in the driver returns -EBUSY. The reason is the driver
has not released the resource from the previous probe attempt.
This patch fixes how we handle the condition of EPROBE_DEFER that is returned
from getting the reset controls. For this condition, the patch will jump
to err_release, which will release the resource.
Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
amba bus probe")
Signed-off-by: Dinh Nguyen
---
v2: release the resource when of_reset_control_array_get_optional_shared()
returns EPROBE_DEFER
---
drivers/amba/bus.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index f39f075abff9..1109437815eb 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -409,9 +409,12 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
*/
rstc =
of_reset_control_array_get_optional_shared(dev->dev.of_node);
if (IS_ERR(rstc)) {
- if (PTR_ERR(rstc) != -EPROBE_DEFER)
+ ret = PTR_ERR(rstc);
+ if (ret == -EPROBE_DEFER)
+ goto err_release;
+ else
dev_err(>dev, "Can't get amba reset!\n");
- return PTR_ERR(rstc);
+ return ret;
}
reset_control_deassert(rstc);
reset_control_put(rstc);
--
2.20.0
[PATCH] ARM: drivers/amba: release the resource to allow for deferred probe
With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
amba bus probe", the amba bus driver needs to be deferred probe because the
reset driver is probed later than the amba bus. However with a deferred
probe, the call to request_resource() in the driver returns -EBUSY. The
reason is the driver has not released the resource from the previous probe
attempt.
This patch releases the resource when amba_device_try_add() returns
-EPROBE_DEFER. This allows the deferred probe to continue.
Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
amba bus probe")
Signed-off-by: Dinh Nguyen
---
drivers/amba/bus.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index f39f075abff9..f246b847c991 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -535,6 +535,7 @@ int amba_device_add(struct amba_device *dev, struct
resource *parent)
if (ret == -EPROBE_DEFER) {
struct deferred_device *ddev;
+ release_resource(>res);
ddev = kmalloc(sizeof(*ddev), GFP_KERNEL);
if (!ddev)
--
2.20.0
[PATCH] reset: build simple reset controller driver for Agilex
The Intel SoCFPGA Agilex platform shares the same reset controller that is on the Stratix10. Signed-off-by: Dinh Nguyen --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 21efb7d39d62..280e69fbf86d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -118,7 +118,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_AGILEX help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, -- 2.20.0
[PATCH 2/2] clk: socfpga: agilex: add clock driver for the Agilex platform
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen
---
drivers/clk/Makefile| 1 +
drivers/clk/socfpga/Makefile| 2 +
drivers/clk/socfpga/clk-agilex.c| 332
drivers/clk/socfpga/clk-pll-s10.c | 70 ++
drivers/clk/socfpga/stratix10-clk.h | 3 +
5 files changed, 408 insertions(+)
create mode 100644 drivers/clk/socfpga/clk-agilex.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..ef2c96c0f1e0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ endif
# hardware specific clock types
# please keep this section sorted lexicographically by file path name
+obj-$(CONFIG_ARCH_AGILEX) += socfpga/
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)+= clk-axi-clkgen.o
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index ce5aa7802eb8..bf736f8d201a 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o
clk-periph.o
obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
new file mode 100644
index ..7d5093f0b2c9
--- /dev/null
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "stratix10-clk.h"
+
+static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk",};
+static const char * const cntr_mux[] = { "main_pll", "periph_pll",
+"osc1", "cb-intosc-hs-div2-clk",
+"f2s-free-clk"};
+static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",};
+
+static const char * const mpu_free_mux[] = {"main_pll_c0", "peri_pll_c0",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+
+static const char * const noc_free_mux[] = {"main_pll_c1", "peri_pll_c1",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+
+static const char * const emaca_free_mux[] = {"main_pll_c2", "peri_pll_c2",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const emacb_free_mux[] = {"main_pll_c3", "peri_pll_c3",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const emac_ptp_free_mux[] = {"main_pll_c3", "peri_pll_c3",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const gpio_db_free_mux[] = {"main_pll_c3", "peri_pll_c3",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const psi_ref_free_mux[] = {"main_pll_c3", "peri_pll_c3",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const sdmmc_free_mux[] = {"main_pll_c3", "peri_pll_c3",
+ "osc1", "cb-intosc-hs-div2-clk",
+ "f2s-free-clk"};
+static const char * const s2f_usr0_free_mux[] = {"main_pll_c2", "peri_pll_c2",
+"osc1",
"cb-intosc-hs-div2-clk",
+"f2s-free-clk"};
+static const char * const s2f_usr1_free_mux[] =
[PATCH 1/2] dt-bindings: documentation: add clock bindings information for Agilex
From: Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen
---
.../devicetree/bindings/clock/intc_agilex.txt | 20 ++
include/dt-bindings/clock/agilex-clock.h | 70 +++
2 files changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/intc_agilex.txt
create mode 100644 include/dt-bindings/clock/agilex-clock.h
diff --git a/Documentation/devicetree/bindings/clock/intc_agilex.txt
b/Documentation/devicetree/bindings/clock/intc_agilex.txt
new file mode 100644
index ..bfec71420511
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/intc_agilex.txt
@@ -0,0 +1,20 @@
+Device Tree Clock bindings for Intel's SoCFPGA Agilex platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be
+ "intel,agilex-clkmgr"
+
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the
clock.
+
+- #clock-cells : from common clock binding, shall be set to 1.
+
+Example:
+ clkmgr: clock-controller@ffd1 {
+ compatible = "intel,agilex-clkmgr";
+ reg = <0xffd1 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/agilex-clock.h
b/include/dt-bindings/clock/agilex-clock.h
new file mode 100644
index ..f19cf8ccbdd2
--- /dev/null
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC10
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX_CB_INTOSC_LS_CLK2
+#define AGILEX_L4_SYS_FREE_CLK 3
+#define AGILEX_F2S_FREE_CLK4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK5
+#define AGILEX_MAIN_PLL_C0_CLK 6
+#define AGILEX_MAIN_PLL_C1_CLK 7
+#define AGILEX_MAIN_PLL_C2_CLK 8
+#define AGILEX_MAIN_PLL_C3_CLK 9
+#define AGILEX_PERIPH_PLL_CLK 10
+#define AGILEX_PERIPH_PLL_C0_CLK 11
+#define AGILEX_PERIPH_PLL_C1_CLK 12
+#define AGILEX_PERIPH_PLL_C2_CLK 13
+#define AGILEX_PERIPH_PLL_C3_CLK 14
+#define AGILEX_MPU_FREE_CLK15
+#define AGILEX_MPU_CCU_CLK 16
+#define AGILEX_BOOT_CLK17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK18
+#define AGILEX_NOC_FREE_CLK19
+#define AGILEX_S2F_USR0_CLK20
+#define AGILEX_NOC_CLK 21
+#define AGILEX_EMAC_A_FREE_CLK 22
+#define AGILEX_EMAC_B_FREE_CLK 23
+#define AGILEX_EMAC_PTP_FREE_CLK 24
+#define AGILEX_GPIO_DB_FREE_CLK25
+#define AGILEX_SDMMC_FREE_CLK 26
+#define AGILEX_S2F_USER0_FREE_CLK 27
+#define AGILEX_S2F_USER1_FREE_CLK 28
+#define AGILEX_PSI_REF_FREE_CLK29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK 30
+#define AGILEX_MPU_L2RAM_CLK 31
+#define AGILEX_MPU_PERIPH_CLK 32
+#define AGILEX_L4_MAIN_CLK 33
+#define AGILEX_L4_MP_CLK 34
+#define AGILEX_L4_SP_CLK 35
+#define AGILEX_CS_AT_CLK 36
+#define AGILEX_CS_TRACE_CLK37
+#define AGILEX_CS_PDBG_CLK 38
+#define AGILEX_CS_TIMER_CLK39
+#define AGILEX_S2F_USER0_CLK 40
+#define AGILEX_EMAC0_CLK 41
+#define AGILEX_EMAC1_CLK 43
+#define AGILEX_EMAC2_CLK 44
+#define AGILEX_EMAC_PTP_CLK45
+#define AGILEX_GPIO_DB_CLK 46
+#define AGILEX_NAND_CLK47
+#define AGILEX_PSI_REF_CLK 48
+#define AGILEX_S2F_USER1_CLK 49
+#define AGILEX_SDMMC_CLK 50
+#define AGILEX_SPI_M_CLK 51
+#define AGILEX_USB_CLK 52
+#define AGILEX_NUM_CLKS53
+
+#endif /* __AGILEX_CLOCK_H */
--
2.20.0
Re: mtd raw nand denali.c broken for Intel/Altera Cyclone V
On 9/10/19 8:48 AM, Tim Sander wrote: > Hi > > I have noticed that my SPF records where not in place after moving the server, > so it seems the mail didn't go to the mailing list. Hopefully that's fixed > now. > > Am Dienstag, 10. September 2019, 09:16:37 CEST schrieb Masahiro Yamada: >> On Fri, Sep 6, 2019 at 9:39 PM Tim Sander wrote: >>> Hi >>> >>> I have noticed that there multiple breakages piling up for the denali nand >>> driver on the Intel/Altera Cyclone V. Unfortunately i had no time to track >>> the mainline kernel closely. So the breakage seems to pile up. I am a >>> little disapointed that Intel is not on the lookout that the kernel works >>> on the chips they are selling. I was really happy about the state of the >>> platform before concerning mainline support. >>> >>> The failure starts with kernel 4.19 or stable kernel release 4.18.19. The >>> commit is ba4a1b62a2d742df9e9c607ac53b3bf33496508f. >> >> Just for clarification, this corresponds to >> 0d55c668b218a1db68b5044bce4de74e1bd0f0c8 upstream. >> >>> The problem here is that >>> our platform works with a zero in the SPARE_AREA_SKIP_BYTES register. >> >> Please clarify the scope of "our platform". >> (Only you, or your company, or every individual using this chip?) > The company i work for uses this chip as a base for multiple products. > >> First, SPARE_AREA_SKIP_BYTES is not the property of the hardware. >> Rather, it is about the OOB layout, in other words, this parameter >> is defined by software. >> >> For example, U-Boot supports the Denali NAND driver. >> The SPARE_AREA_SKIP_BYTES is a user-configurable parameter: >> https://github.com/u-boot/u-boot/blob/v2019.10-rc3/drivers/mtd/nand/raw/Kcon >> fig#L112 >> >> >> Your platform works with a zero in the SPARE_AREA_SKIP_BYTES register >> because the NAND chip on the board was initialized with a zero >> set to the SPARE_AREA_SKIP_BYTES register. >> >> If the NAND chip had been initialized with 8 >> set to the SPARE_AREA_SKIP_BYTES register, it would have >> been working with 8 to the SPARE_AREA_SKIP_BYTES. >> >> The Boot ROM is the only (semi-)software that is unconfigurable by users, >> so the value of SPARE_AREA_SKIP_BYTES should be aligned with >> the boot ROM. >> I recommend you to check the spec of the boot ROM. > We boot from NOR flash. That's why i didn't see a problem booting probably. > >> (The maintainer of the platform, Dihn is CC'ed, >> so I hope he will jump in) > Yes i hope so too. > I don't have access to a NAND device at the moment. I'll try to find one and debug. Dinh
[PATCHv7] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals
that are not used are held in reset and are left to Linux to bring them
out of reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset properti
is not present in the device tree node, so the driver will continue to
probe.
Because there are different variants of the controller that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
Reviewed-by: Philipp Zabel
---
v7: added Philipp Zabel's Reviewed-by:
v6: remove the need to reset_control_get_count as
of_reset_control_array_get_optional_shared is already doing that
v5: use of_reset_control_array_get_optional_shared()
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..f39f075abff9 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,19 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ rstc =
of_reset_control_array_get_optional_shared(dev->dev.of_node);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) != -EPROBE_DEFER)
+ dev_err(>dev, "Can't get amba reset!\n");
+ return PTR_ERR(rstc);
+ }
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
/*
* Read pid and cid based on size of resource
--
2.20.0
Re: [PATCHv5] drivers/amba: add reset control to amba bus probe
-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 8/27/19 2:25 PM, Valdis Kl?tnieks wrote: > On Mon, 26 Aug 2019 10:42:52 -0500, Dinh Nguyen said: >> The primecell controller on some SoCs, i.e. SoCFPGA, is held in >> reset by default. Until recently, the DMA controller was brought >> out of reset by the bootloader(i.e. U-Boot). But a recent change >> in U-Boot, the peripherals that are not used are held in reset >> and are left to Linux to bring them out of reset. >> >> Add a mechanism for getting the reset property and de-assert the >> primecell module from reset if found. This is a not a hard fail >> if the reset properti is not present in the device tree node, so >> the driver will continue to probe. > > Does this DTRT for both old and new U-Boots? My naive reading of > this patch What is a DTRT? > says on an old U-Boot, we end up attempting to bring it out of > reset even though they had already been brought out. > If the peripheral is already out of reset, de-asserting the reset has no affect. Dinh -BEGIN PGP SIGNATURE- iQIzBAEBCgAdFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAl1mgtYACgkQGZQEC4Gj KPRKMRAArFO9bQ7FCE4oiVgO/sOLm2M/ngGD3Czi6Y8TcAbIk4EylBGVw634Gs4Z v5vuyxShlfApBb0PqfhLOo5cXrTyMdpWOq9AQ4vEcEU2MPKN8QcyLczvEagyYcwA ianhTLR21v1Gdfm5MHqpKrNxSrb6Nt6cWmYCXjpabLYZg0gKJnsYl2XheHIdUJ02 kD2P6sQC3mf3OC5Gou4JXZGvDMgEwLG9lHsb7YoFq6tzZW3YQvAi3HcxIZZh4J8b jFcPR3RxxQgGwESEGDWQu2EzY/d9qStEQ9VYHl/v6QIL77S1oXUAXLbh3e6ZoSgt M93eK2G9wGCL5JlUbHXQ402OfewHchgQW1bDpjkaZLL+d9jUiGLqALAj0Az2FqX1 HtPPtifB4z6TuaLkxNTZ1Oz7UR0cWtKeSYjsuIwi0XzQMXopgH7oKdzJajNlAfRJ In6fSVuwp47p43wj2dmUtuCSYvzKTHAg/sVGaufEfsT8ZINSOZJY9ivDqkJIzlDR nsOclhfOGs5PgL4NPFW5U5O58DzZ5yl9NEotB4ahacuOqJv1PUdT3gABbL5hUogx QTAPNREbYesG3osFLeEXeachiNChyJ7r+NyWFly7RXA/ukxoer2Rkxt3h0hQib6Q /jhAsa1ar1NEk8dJJfNO7R5pZkG7ZCbhzuSDKPB2yRZPDeQGol8= =SFzc -END PGP SIGNATURE-
[PATCHv6] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals
that are not used are held in reset and are left to Linux to bring them
out of reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset properti
is not present in the device tree node, so the driver will continue to
probe.
Because there are different variants of the controller that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v6: remove the need to reset_control_get_count as
of_reset_control_array_get_optional_shared is already doing that
v5: use of_reset_control_array_get_optional_shared()
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..f39f075abff9 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,19 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ rstc =
of_reset_control_array_get_optional_shared(dev->dev.of_node);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) != -EPROBE_DEFER)
+ dev_err(>dev, "Can't get amba reset!\n");
+ return PTR_ERR(rstc);
+ }
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
/*
* Read pid and cid based on size of resource
--
2.20.0
[PATCHv5] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals
that are not used are held in reset and are left to Linux to bring them
out of reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset properti
is not present in the device tree node, so the driver will continue to
probe.
Because there are different variants of the controller that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v5: use of_reset_control_array_get_optional_shared()
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..f8a7cb74c3cf 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,24 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ count = reset_control_get_count(>dev);
+ while (count > 0) {
+ rstc =
of_reset_control_array_get_optional_shared(dev->dev.of_node);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) != -EPROBE_DEFER)
+ dev_err(>dev, "Can't get amba
reset!\n");
+ return PTR_ERR(rstc);
+ }
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
+ count--;
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
Re: [RESEND PATCHv4 1/1] drivers/amba: add reset control to amba bus probe
Hi Philipp,
On 8/26/19 3:57 AM, Philipp Zabel wrote:
> Hi Dinh, Linus,
>
> On Fri, 2019-08-23 at 10:42 -0500, Dinh Nguyen wrote:
>>
>> On 8/23/19 4:19 AM, Linus Walleij wrote:
>>> On Tue, Aug 20, 2019 at 4:58 PM Dinh Nguyen wrote:
>>>
>>>> @@ -401,6 +402,26 @@ static int amba_device_try_add(struct amba_device
>>>> *dev, struct resource *parent)
>>>> ret = amba_get_enable_pclk(dev);
>>>> if (ret == 0) {
>>>> u32 pid, cid;
>>>> + int count;
>>>> + struct reset_control *rstc;
>>>> +
>>>> + /*
>>>> +* Find reset control(s) of the amba bus and de-assert
>>>> them.
>>>> +*/
>>>> + count = reset_control_get_count(>dev);
>
> The reset_control_get_count() inline stub returns -ENOENT, so the
> compiler can throw away the complete loop.
>
>>>> + while (count > 0) {
>>>> + rstc =
>>>> of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
>
> Since resets are looked up with of_reset_control_get, I'd use
> of_reset_control_get_count() above for consistency. But see below:
>
reset_control_get_count() ultimately calls of_reset_control_get_count()
and it looks like of_reset_control_get_count() is not exported.
>>>> + if (IS_ERR(rstc)) {
>>>> + if (PTR_ERR(rstc) == -EPROBE_DEFER)
>>>> + ret = -EPROBE_DEFER;
>>>> + else
>>>> + dev_err(>dev, "Can't get amba
>>>> reset!\n");
>>>> + break;
>>>> + }
>>>> + reset_control_deassert(rstc);
>>>> + reset_control_put(rstc);
>>>> + count--;
>>>> + }
>
> It looks like the order of deassertions is irrelevant. If so,
> You can use of_reset_control_array_get() to simplify this:
>
> + rstc =
> of_reset_control_array_get_optional_shared(dev->dev.of_node);
> + if (IS_ERR(rstc)) {
> + if (PTR_ERR(rstc) != -EPROBE_DEFER)
> + dev_err(>dev, "Can't get amba reset!\n");
> + return PTR_ERR(rstc);
> + }
> + reset_control_deassert(rstc);
> + reset_control_put(rstc);
>
Thanks for the review! I'll post v5 shortly.
Dinh
Re: [RESEND PATCHv4 1/1] drivers/amba: add reset control to amba bus probe
On 8/23/19 4:19 AM, Linus Walleij wrote:
> On Tue, Aug 20, 2019 at 4:58 PM Dinh Nguyen wrote:
>
>> @@ -401,6 +402,26 @@ static int amba_device_try_add(struct amba_device *dev,
>> struct resource *parent)
>> ret = amba_get_enable_pclk(dev);
>> if (ret == 0) {
>> u32 pid, cid;
>> + int count;
>> + struct reset_control *rstc;
>> +
>> + /*
>> +* Find reset control(s) of the amba bus and de-assert them.
>> +*/
>> + count = reset_control_get_count(>dev);
>> + while (count > 0) {
>> + rstc =
>> of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
>> + if (IS_ERR(rstc)) {
>> + if (PTR_ERR(rstc) == -EPROBE_DEFER)
>> + ret = -EPROBE_DEFER;
>> + else
>> + dev_err(>dev, "Can't get amba
>> reset!\n");
>> + break;
>> + }
>> + reset_control_deassert(rstc);
>> + reset_control_put(rstc);
>> + count--;
>> + }
>
> I'm not normally a footprint person, but the looks of the stubs in
> makes me suspicious whether this will have zero impact
> in size on platforms without reset controllers.
>
> Can you just ls -al on the kernel without CONFIG_RESET_CONTROLLER
> before and after this patch and ascertain that it has zero footprint effect?
Thanks for the review. I checked it, and indeed, it does have a zero
footprint effect.
>
> If it doesn't I'd sure like to break this into its own function and
> stick a if (!IS_ENABLED(CONFIG_RESET_CONTROLLER)) return 0;
> in there to make sure the compiler drops it.
>
> Also it'd be nice to get Philipp's ACK on the semantics, though they
> look correct to me.
>
Dinh
[RESEND PATCHv4 0/1] drivers/amba: add reset control to amba
Hello, Even though this patch is a V4, I'm including more people in this review cycle because I found that there was previous patch[1] that was discussed. Thanks, Dinh [1] https://patchwork.kernel.org/patch/10845695/ Dinh Nguyen (1): drivers/amba: add reset control to amba bus probe drivers/amba/bus.c | 21 + 1 file changed, 21 insertions(+) -- 2.20.0
[RESEND PATCHv4 1/1] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals
that are not used are held in reset and are left to Linux to bring them
out of reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset properti
is not present in the device tree node, so the driver will continue to
probe.
Because there are different variants of the controller that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..76a1cd56a1ab 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,26 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ count = reset_control_get_count(>dev);
+ while (count > 0) {
+ rstc =
of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) == -EPROBE_DEFER)
+ ret = -EPROBE_DEFER;
+ else
+ dev_err(>dev, "Can't get amba
reset!\n");
+ break;
+ }
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
+ count--;
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
Re: [PATCH] ARM: dts: socfpga: update to new Denali NAND binding
On 8/19/19 1:17 AM, Masahiro Yamada wrote:
> On Tue, Jun 25, 2019 at 12:39 AM Dinh Nguyen wrote:
>>
>>
>>
>> On 6/21/19 6:23 AM, Masahiro Yamada wrote:
>>> With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
>>> and NAND chips"), the Denali NAND controller driver migrated to the
>>> new controller/chip representation.
>>>
>>> Update DT for it.
>>>
>>> Signed-off-by: Masahiro Yamada
>>> ---
>>>
>>> arch/arm/boot/dts/socfpga.dtsi| 2 +-
>>> arch/arm/boot/dts/socfpga_arria10.dtsi| 2 +-
>>> .../boot/dts/socfpga_arria10_socdk_nand.dts | 20 ---
>>> 3 files changed, 15 insertions(+), 9 deletions(-)
>>>
>>
>> Applied! Thanks!
>>
>> Dinh
>
>
> You did not send this to upstream for v5.3-rc1.
>
> Which version is this aiming for?
>
Yes, I apologize but I missed the 5.3 window. It'll be in 5.4.
Dinh
[PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: sta...@vger.kernel.org
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-periph-s10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-periph-s10.c
b/drivers/clk/socfpga/clk-periph-s10.c
index 5c50e723ecae..1a191bba 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct
clk_hw *hwclk,
if (socfpgaclk->fixed_div) {
div = socfpgaclk->fixed_div;
} else {
- if (!socfpgaclk->bypass_reg)
+ if (socfpgaclk->hw.reg)
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
}
--
2.20.0
[PATCHv4] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals
that are not used are held in reset and are left to Linux to bring them
out of reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset properti
is not present in the device tree node, so the driver will continue to
probe.
Because there are different variants of the controller that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..76a1cd56a1ab 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,26 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ count = reset_control_get_count(>dev);
+ while (count > 0) {
+ rstc =
of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) == -EPROBE_DEFER)
+ ret = -EPROBE_DEFER;
+ else
+ dev_err(>dev, "Can't get amba
reset!\n");
+ break;
+ }
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
+ count--;
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
Re: [PATCH] clk: socfpga: deindent code to proper indentation
On 8/13/19 7:24 PM, Stephen Boyd wrote: > This code is indented oddly, causing checkpatch to complain. Indent it > properly. > > Cc: Dinh Nguyen > Signed-off-by: Stephen Boyd > --- > drivers/clk/socfpga/clk-gate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Acked-by: Dinh Nguyen
[PATCHv3] drivers/amba: add reset control to amba bus probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
are not used are held in reset and are left to Linux to bring them out of
reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset property
is not present in the device tree node, so the driver will continue to probe.
Because there are different variants of the controller that may have multiple
reset signals, the code will find all reset(s) specified and de-assert them.
Signed-off-by: Dinh Nguyen
---
v3: add a reset_control_put()
add error handling for -EPROBE_DEFER
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..00e68ea416ca 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,28 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ count = reset_control_get_count(>dev);
+ while (count > 0) {
+ rstc =
of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
+ if (IS_ERR(rstc)) {
+ if (PTR_ERR(rstc) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ } else {
+ dev_err(>dev, "Can't get amba
reset!\n");
+ }
+ break;
+ } else {
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
+ count--;
+ }
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
[PATCHv2] drivers/amba: add reset control to primecell probe
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
are not used are held in reset and are left to Linux to bring them out of
reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset property
is not present in the device tree node, so the driver will continue to probe.
Because there are different variants of the controller that may have multiple
reset signals, the code will find all reset(s) specified and de-assert them.
Signed-off-by: Dinh Nguyen
---
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..75e18b9e4808 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
@@ -401,6 +402,18 @@ static int amba_device_try_add(struct amba_device *dev,
struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+* Find reset control(s) of the amba bus and de-assert them.
+*/
+ count = reset_control_get_count(>dev);
+ while (count > 0) {
+ rstc =
of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
+ reset_control_deassert(rstc);
+ count--;
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
Re: [PATCH] drivers/amba: add reset control to primecell probe
On 8/2/19 9:37 AM, Rob Herring wrote:
> On Thu, Aug 1, 2019 at 12:44 PM Dinh Nguyen wrote:
>>
>> From: Dinh Nguyen
>>
>> The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
>> default. Until recently, the DMA controller was brought out of reset by the
>> bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
>> are not used are held in reset and are left to Linux to bring them out of
>> reset.
>
> You can fix this in the kernel, but any versions before this change
> will remain broken. IMO, the u-boot change should be reverted because
> it is breaking an ABI (though not a good one).
>
Right, there exists in U-Boot to support legacy platforms before this
recent change. This would be for future versions.
>> Add a mechanism for getting the reset property and de-assert the primecell
>> module from reset if found. This is a not a hard fail if the reset property
>> is not present in the device tree node, so the driver will continue to probe.
>
> I think this belongs in the AMBA bus code, not the DT code, as that is
> where we already have clock control code for similar reasons.
>
Ok.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> drivers/of/platform.c | 14 ++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
>> index 7801e25e6895..d8945705313d 100644
>> --- a/drivers/of/platform.c
>> +++ b/drivers/of/platform.c
>> @@ -21,6 +21,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> const struct of_device_id of_default_bus_match_table[] = {
>> { .compatible = "simple-bus", },
>> @@ -229,6 +230,7 @@ static struct amba_device *of_amba_device_create(struct
>> device_node *node,
>> struct amba_device *dev;
>> const void *prop;
>> int i, ret;
>> + struct reset_control *rstc;
>>
>> pr_debug("Creating amba device %pOF\n", node);
>>
>> @@ -270,6 +272,18 @@ static struct amba_device *of_amba_device_create(struct
>> device_node *node,
>> goto err_free;
>> }
>>
>> + /*
>> +* reset control of the primecell block is optional
>> +* and will not fail if the reset property is not found.
>> +*/
>> + rstc = of_reset_control_get_exclusive(node, "dma");
>
> 'dma' doesn't sound very generic.
>
how about 'primecell' ?
Thanks for the review!
Dinh
[PATCH] drivers/amba: add reset control to primecell probe
From: Dinh Nguyen
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
are not used are held in reset and are left to Linux to bring them out of
reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset property
is not present in the device tree node, so the driver will continue to probe.
Signed-off-by: Dinh Nguyen
---
drivers/of/platform.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 7801e25e6895..d8945705313d 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
const struct of_device_id of_default_bus_match_table[] = {
{ .compatible = "simple-bus", },
@@ -229,6 +230,7 @@ static struct amba_device *of_amba_device_create(struct
device_node *node,
struct amba_device *dev;
const void *prop;
int i, ret;
+ struct reset_control *rstc;
pr_debug("Creating amba device %pOF\n", node);
@@ -270,6 +272,18 @@ static struct amba_device *of_amba_device_create(struct
device_node *node,
goto err_free;
}
+ /*
+* reset control of the primecell block is optional
+* and will not fail if the reset property is not found.
+*/
+ rstc = of_reset_control_get_exclusive(node, "dma");
+ if (!IS_ERR(rstc)) {
+ reset_control_deassert(rstc);
+ reset_control_put(rstc);
+ } else {
+ pr_debug("amba: reset control not found\n");
+ }
+
ret = amba_device_add(dev, _resource);
if (ret) {
pr_err("amba_device_add() failed (%d) for %pOF\n",
--
2.20.0
Re: [PATCH 6/9] clk: socfpga: Don't reference clk_init_data after registration
Hi Stephen, On 7/31/19 2:35 PM, Stephen Boyd wrote: > A future patch is going to change semantics of clk_register() so that > clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid > referencing this member here so that we don't run into NULL pointer > exceptions. > > Cc: Dinh Nguyen > Signed-off-by: Stephen Boyd > --- > > Please ack so I can take this through clk tree > > drivers/clk/socfpga/clk-gate.c | 21 +++-- > drivers/clk/socfpga/clk-periph-a10.c | 7 --- > 2 files changed, 15 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c > index 3966cd43b552..b3c8143909dc 100644 > --- a/drivers/clk/socfpga/clk-gate.c > +++ b/drivers/clk/socfpga/clk-gate.c > @@ -31,20 +31,20 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) > u32 l4_src; > u32 perpll_src; You need this line here: const char *name = clk_hw_get_name(hwclk); Otherwise, it fails to build. With the above change: Acked-by: Dinh Nguyen Thanks, Dinh
Re: [PATCHv1] ARM64: defconfig: Add LEDS_TRIGGERS_TIMER for blinking leds
On 6/27/19 9:07 AM, Ong, Hean Loong wrote: > Adding LED Triggers Timers for LED blinking support on ARM devices > > Signed-off-by: Ong, Hean Loong > --- > arch/arm64/configs/defconfig |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 4d58351..6fbd651 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -595,6 +595,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y > CONFIG_LEDS_TRIGGER_CPU=y > CONFIG_LEDS_TRIGGER_DEFAULT_ON=y > CONFIG_LEDS_TRIGGER_PANIC=y > +CONFIG_LEDS_TRIGGER_TIMER=y > CONFIG_EDAC=y > CONFIG_EDAC_GHES=y > CONFIG_RTC_CLASS=y > I've applied this patch with this change: --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -590,6 +590,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_DISK=y defconfig CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y Also, the commit header should be "arm64: defconfig". Dinh
